CN202206659U - Double-layered circuit board with buried element - Google Patents
Double-layered circuit board with buried element Download PDFInfo
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- CN202206659U CN202206659U CN2011203650215U CN201120365021U CN202206659U CN 202206659 U CN202206659 U CN 202206659U CN 2011203650215 U CN2011203650215 U CN 2011203650215U CN 201120365021 U CN201120365021 U CN 201120365021U CN 202206659 U CN202206659 U CN 202206659U
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- layer
- patterned line
- dielectric layer
- line layer
- embedded element
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Abstract
The utility model relates to the field of printed wiring boards, in particular to a double-layered circuit board with a buried element. The double-layered circuit board comprises a core layer A and the buried element with two electrodes, wherein the core layer A consists of a first dielectric layer, a first patterned circuit layer and a second patterned circuit layer; and a through-hole is formed in the first dielectric layer. The double-layered circuit board is characterized in that the buried element is fixed in the through-hole through bonding agent; the lower end surfaces of the two electrodes of the buried element and the outer surface of the second patterned circuit layer are on the same horizontal plane; and a layer of conducting resin is coated on the lower surface of the first dielectric layer between the outer side surfaces of the lower ends of the left and the right electrodes of the buried element and the side surface of the second patterned circuit layer. The utility model aims to provide the double-layered circuit board with the buried element, which can increase the wiring density of the circuit layers and effectively reduce the thickness of the whole substrate. Compared with the prior art, the utility model has the advantages of improving the reliability in electric connection, increasing the wiring area, reducing the manufacturing cost, and the like.
Description
Technical field
The utility model relates to the printed wiring board field, especially a kind of double-deck wiring board of embedded element.
Background technology
Generally speaking, circuit base plate mainly be by multi-layered patterned line layer and dielectric layer be superimposed the institute constitute.Wherein, patterned line layer is to be defined through little shadow and etch process by copper foil layer to form, and dielectric layer is disposed between the patterned line layer, in order to isolate two adjacent patterned line layer.In addition, be to see through the conductive through hole that runs through dielectric layer or conduction duct and be electrically connected to each other between the adjacent patterned line layer.At last, at the various electronic components of the surface configuration of circuit base plate (for example active member or passive device), and the circuit design through internal wiring reaches the purpose that electronic signal is transmitted.Yet; Along with market should have demand compact and easy to carry for electronic product; Therefore in present electronic product; The electronic component that originally was welded in circuit base plate surface is designed to be embedded in an embedded element of the inside of circuit base plate, can increases the wiring area on circuit base plate surface like this, to reach the electronic product purpose of thinness.
Fig. 1 be existing a kind of embedded element the printed wiring board structure generalized section, with reference to figure 1, the printed wiring board of existing embedded element comprises core layer A, the first overlapping layers B, the second overlapping layers C and embedded element 8.Wherein:
Said core layer A is made up of first dielectric layer, 1, the first patterned line layer 2 and second patterned line layer 3, and first patterned line layer 2 and second patterned line layer 3 lay respectively at a upper surface 1a and a lower surface 1b of first dielectric layer 2.
In said core layer A, be provided with a perforation, and said embedded element 9 is positioned in the perforation, wherein embedded element 9 has two electrodes 8.
The said first overlapping layers B is made up of the first top layer circuit 5 and second dielectric layer 4; The said second overlapping layers C is made up of the second top layer circuit 7 and the 3rd dielectric layer 6, and second dielectric layer 4 and the 3rd dielectric layer 6 are pressed together on respectively on first patterned line layer 2 and second patterned line layer 3.
Between the said first overlapping layers B, core layer A and the second overlapping layers C three, be provided with the conductive through hole 11 that runs through the three, make win top layer circuit 5 and the second top layer circuit 7 can see through conductive through hole 11 and be electrically connected to each other.
Be provided with conduction duct 10 with embedded element two electrodes, 8 corresponding second dielectric layers 4 and the 3rd dielectric layer 6, make two electrodes 8 of embedded element electrically connect with the first top layer circuit 5 and the second top layer circuit 7 respectively through conduction duct 10.
Because two electrodes 8 of embedded element must just can be electrically connected to the first top layer circuit 5 and the second top layer circuit 7 through conduction duct 10; Can reduce the wiring area of first patterned line layer 2 and second patterned line layer 3 like this, and then reduce the wiring density of first patterned line layer 2 and second patterned line layer 3.In addition, embedded element 9 need pass through the conduction duct 10 and the first top layer circuit 5 and the second top layer circuit 7 and electrically connect, and this mode will increase the thickness of whole circuit base plate, and can't meet compact product design requirement.
Summary of the invention
The main purpose of the utility model is to provide a kind of double-deck wiring board of embedded element; Promoting the wiring density of first patterned line layer, second patterned line layer, the first top layer circuit and the second top layer circuit, and can reduce the thickness of whole base plate effectively.
In order to achieve the above object, the utility model adopts following technical scheme: a kind of double-deck wiring board of embedded element, and it comprises core layer A, the first overlapping layers B, the second overlapping layers C and has the embedded element of two electrodes, wherein:
Said core layer A is made up of first dielectric layer, first patterned line layer and second patterned line layer; First patterned line layer and second patterned line layer lay respectively at the upper surface and the lower surface of first dielectric layer, in described first dielectric layer, are provided with a perforation;
The said first overlapping layers B is made up of the first top layer circuit and second dielectric layer; The said second overlapping layers C is made up of the second top layer circuit and the 3rd dielectric layer, and second dielectric layer and the 3rd dielectric layer are pressed together on respectively on first patterned line layer and second patterned line layer;
Between the said first overlapping layers B, core layer A and the second overlapping layers C three, be provided with the conductive through hole that runs through the three; Making win top layer circuit and the second top layer circuit can see through conductive through hole be electrically connected to each other; It is characterized in that said embedded element is fixed in the perforation of described first dielectric layer by adhesive agent; Solidifying the lower surface of back adhesive agent and the lower surface of described first dielectric layer is on the same horizontal plane; And the lower surface of said embedded element two electrodes and the outer surface of second patterned line layer are on same horizontal plane; Coating one deck conducting resinl on the first dielectric layer lower surface between the side of the lower outside face of left and right two electrodes of said embedded element and second patterned line layer makes the embedded element electrode constitute electric connection through the conducting resinl and second patterned line layer.
Compared to prior art; In the utility model; The electrode of embedded element directly is electrically connected to first patterned line layer or second patterned line layer of internal layer; Therefore, the wiring density of first patterned line layer, second patterned line layer, the first top layer circuit and the second top layer circuit can be promoted, and the reliability of the electric connection of embedded element and first patterned line layer or second patterned line layer can be improved.In addition; The patterned line layer of direct and internal layer electrically connects because embedded element need not see through existing conductive through hole; Therefore, can effectively reduce the thickness of whole base plate, make the electronic product of using this substrate can meet compact product design requirement.
Description of drawings
Fig. 1 is the structural profile sketch map of the printed wiring board of existing a kind of embedded element.
Fig. 2 is the structural profile sketch map of core layer A in the present embodiment.
Fig. 3 is solidificated in the structural profile sketch map among the core layer A for embedded element setting in the present embodiment.
Fig. 4 is the electrode of embedded element in the present embodiment and the structural profile sketch map that second patterned line layer electrically connects.
Fig. 5 is a present embodiment overall structure generalized section.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is further described.
As shown in Figure 5, present embodiment comprises core layer A, the first overlapping layers B, the second overlapping layers C and has the embedded element 9 of two electrodes 8, wherein:
As shown in Figure 2; Said core layer A is made up of first dielectric layer 1, first patterned line layer 2 and second patterned line layer 3; First patterned line layer 2 and second patterned line layer 3 lay respectively at a upper surface 1a and a lower surface 1b of first dielectric layer 1, in described first dielectric layer 1, are provided with a perforation 14;
As shown in Figure 5 again; The said first overlapping layers B is made up of the first top layer circuit 5 and second dielectric layer 4; The said second overlapping layers C is made up of the second top layer circuit 7 and the 3rd dielectric layer 6, and second dielectric layer 4 and the 3rd dielectric layer 6 are pressed together on respectively on first patterned line layer 2 and second patterned line layer 3;
Between the said first overlapping layers B, core layer A and the second overlapping layers C three, be provided with the conductive through hole 11 that runs through the three, make win top layer circuit 5 and the second top layer circuit 7 can see through conductive through hole 11 and be electrically connected to each other.
As shown in Figure 3; Said embedded element 9 is fixed in the said perforation 14 by adhesive agent 12; Solidifying the lower surface of back adhesive agent 12 and the lower surface 1b of described first dielectric layer 1 is on the same horizontal plane; And the lower surface 8b of said embedded element two electrodes 8 and the outer surface 3a of second patterned line layer 3 are on the same horizontal plane; As shown in Figure 4, coating one deck conducting resinl 13 on first dielectric layer, the 1 lower surface 1b between the side 3b of the lower outside face 8a of left and right two electrodes 8 of said embedded element and second patterned line layer 3 makes the embedded element electrode constitute electric connections through the conducting resinl 13 and second patterned line layer 3.
In this mandatory declaration is when the electrode 8 of above-mentioned electric connection embedded element 9 and second patterned line layer 3, can electrically connect the electrode 8 and first patterned line layer 2 of embedded element 9 simultaneously, but not illustrate with drawing at this.
In sum, the utility model compared with prior art has the following advantages:
1, because in the utility model structure; The electrode of embedded element is electrically connected to first patterned line layer or second patterned line layer of internal layer; Therefore can promote the wiring density of first patterned line layer, second patterned line layer, the first top layer circuit and the second top layer circuit, and the reliability of improving the electric connection of embedded element and first patterned line layer or second patterned line layer.
2, first patterned line layer or second patterned line layer of direct and internal layer electrically connect because embedded element need not see through existing conductive through hole; Therefore can reduce the thickness of whole base plate effectively, make the electronic product of using this substrate can meet compact product design requirement.
3, because in the utility model structure; The electrode of embedded element is electrically connected to first patterned line layer or second patterned line layer of internal layer; Transmit the crosstalk effect of electrical signals between the electrode that therefore can reduce embedded element and first patterned line layer or second patterned line layer, and then promote its electrical performance.
4, because in the utility model structure, the electrode of embedded element is not electrically connected to first patterned line layer or second patterned line layer of internal layer with the mode that forms the conduction duct, so the utility model manufacturing cost is lower.
Claims (1)
1. the double-deck wiring board of an embedded element, it comprises core layer A, the first overlapping layers B, the second overlapping layers C and has the embedded element (9) of two electrodes (8), wherein:
Said core layer A is made up of first dielectric layer (1), first patterned line layer (2) and second patterned line layer (3); First patterned line layer (2) and second patterned line layer (3) lay respectively at a upper surface (1a) and a lower surface (1b) of first dielectric layer (1), in described first dielectric layer (1), are provided with a perforation (14);
The said first overlapping layers B is made up of the first top layer circuit (5) and second dielectric layer (4); The said second overlapping layers C is made up of the second top layer circuit (7) and the 3rd dielectric layer (6), and second dielectric layer (4) is pressed together on respectively on first patterned line layer (2) and second patterned line layer (3) with the 3rd dielectric layer (6);
Between the said first overlapping layers B, core layer A and the second overlapping layers C three, be provided with the conductive through hole (11) that runs through the three; Making the top layer circuit (5) of winning can see through conductive through hole (11) with the second top layer circuit (7) is electrically connected to each other; It is characterized in that said embedded element (9) is fixed in the said perforation (14) by adhesive agent (12); Solidifying the lower surface of back adhesive agent (12) and the lower surface (1b) of described first dielectric layer (1) is on the same horizontal plane; And the lower surface (8b) of said embedded element two electrodes (8) is on the same horizontal plane with the outer surface (3a) of second patterned line layer (3); First dielectric layer (1) lower surface (1b) between the side (3b) of the lower outside face (8a) of left and right two electrodes of said embedded element (8) and second patterned line layer (3) is gone up coating one deck conducting resinl (13), the embedded element electrode is constituted with second patterned line layer (3) through conducting resinl (13) electrically connect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011203650215U CN202206659U (en) | 2011-09-22 | 2011-09-22 | Double-layered circuit board with buried element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN2011203650215U CN202206659U (en) | 2011-09-22 | 2011-09-22 | Double-layered circuit board with buried element |
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CN202206659U true CN202206659U (en) | 2012-04-25 |
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CN2011203650215U Expired - Fee Related CN202206659U (en) | 2011-09-22 | 2011-09-22 | Double-layered circuit board with buried element |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104244565A (en) * | 2013-06-17 | 2014-12-24 | 律胜科技股份有限公司 | Build-up material for printed circuit board, manufacturing method thereof and printed circuit board with embedded element |
CN104979325A (en) * | 2014-04-04 | 2015-10-14 | 欣兴电子股份有限公司 | Packaging structure embedded with passive electronic element and manufacturing method thereof |
TWI698158B (en) * | 2018-10-12 | 2020-07-01 | 大陸商慶鼎精密電子(淮安)有限公司 | Embedded circuit board and method for making the same |
-
2011
- 2011-09-22 CN CN2011203650215U patent/CN202206659U/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104244565A (en) * | 2013-06-17 | 2014-12-24 | 律胜科技股份有限公司 | Build-up material for printed circuit board, manufacturing method thereof and printed circuit board with embedded element |
CN104979325A (en) * | 2014-04-04 | 2015-10-14 | 欣兴电子股份有限公司 | Packaging structure embedded with passive electronic element and manufacturing method thereof |
TWI698158B (en) * | 2018-10-12 | 2020-07-01 | 大陸商慶鼎精密電子(淮安)有限公司 | Embedded circuit board and method for making the same |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120425 Termination date: 20150922 |
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EXPY | Termination of patent right or utility model |