CN215183995U - Solar cell and photovoltaic module - Google Patents
Solar cell and photovoltaic module Download PDFInfo
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- CN215183995U CN215183995U CN202120658663.8U CN202120658663U CN215183995U CN 215183995 U CN215183995 U CN 215183995U CN 202120658663 U CN202120658663 U CN 202120658663U CN 215183995 U CN215183995 U CN 215183995U
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Abstract
The utility model provides a solar cell and photovoltaic module, solar cell includes: the semiconductor substrate, electroplate the main grid electrode in the main grid opening of the passivation layer of semiconductor substrate insulation, and electroplate the fine grid electrode in the fine grid opening of the passivation layer of semiconductor substrate insulation; the size of the main gate electrode in a third direction perpendicular to the surface of the semiconductor substrate is larger than the size of the fine gate electrode in the third direction. The utility model discloses in, can be through control electroplating process for thin grid electrode compares in main grid electrode, has the less size in the direction on perpendicular to semiconductor substrate surface, thereby can reduce the quantity of the conductive paste of preparation electrode, reduces solar cell's manufacturing cost. Meanwhile, the structure and the size of the main grid electrode welded with the connecting wires such as the welding strips are not changed, so that the connection strength between the main grid electrode and the connecting wires can be ensured, the main grid electrode is prevented from being desoldered, and the connection reliability between adjacent solar cells is ensured.
Description
Technical Field
The utility model relates to a photovoltaic technology field especially relates to a solar cell and photovoltaic module.
Background
The crystalline silicon solar cell is the solar cell with the highest market share at present due to high energy conversion efficiency. How to reduce the production cost of the crystalline silicon solar cell and the crystalline silicon solar cell module while improving the conversion efficiency of the crystalline silicon solar cell and the crystalline silicon solar cell module is the biggest problem in the industry.
At present, in a large-scale crystalline silicon solar cell manufacturing technology, a main grid electrode and a fine grid electrode which are connected with each other are generally prepared on a silicon substrate in a screen printing or electroplating mode and the like to obtain a solar cell, and finally, a plurality of cells are required to be electrically connected to form a solar cell module so as to converge current collected by the plurality of cells to supply power for external equipment, and adjacent cells are required to be connected through connecting wires such as welding strips and the like. Specifically, the connecting wires are generally welded to the main gate electrodes of the adjacent cells, so as to electrically connect the adjacent cells. Due to the fact that the cost of the conductive paste for preparing the electrode is high, the main grid electrode can be set to be in a discontinuous shape in the prior art, the using amount of the conductive paste is reduced, and the production cost of the solar cell is reduced.
However, in the prior art, the main grid electrode is formed in a discontinuous shape, which reduces the connection strength between the connection lines such as solder strips and the main grid electrode, and leads to the main grid electrode being detached, thereby reducing the connection reliability between the adjacent battery pieces.
SUMMERY OF THE UTILITY MODEL
The utility model provides a solar cell and photovoltaic module when aiming at reducing the conductive paste's of preparation electrode quantity among the solar cell, ensures the joint strength between main grid electrode and the connecting wire.
In a first aspect, an embodiment of the present invention provides a solar cell, the solar cell includes:
the gate structure comprises a semiconductor substrate, a main gate electrode and a fine gate electrode which are electroplated on at least one surface of the semiconductor substrate, and an insulating passivation layer arranged on the surface of the semiconductor substrate;
a main gate opening structure and a fine gate opening structure are arranged in the insulating passivation layer, the main gate electrode is arranged in the main gate opening structure and connected with the semiconductor substrate, and the main gate electrode extends along a first direction of the surface of the semiconductor substrate; the fine gate electrode is arranged in the fine gate opening structure and connected with the semiconductor substrate, the fine gate electrode extends along a second direction of the surface of the semiconductor substrate, and the main gate electrode is connected with the fine gate electrode;
the size of the main gate electrode in a third direction perpendicular to the surface of the semiconductor substrate is larger than that of the fine gate electrode in the third direction; the third direction is perpendicular to the semiconductor substrate surface.
Optionally, the main gate electrode comprises a plurality of first main gate electrode subsections and a plurality of second main gate electrode subsections;
the first main gate electrode subsection is in a block shape, and a plurality of first main gate electrode subsections are arranged at intervals along the first direction;
the second main gate electrode subsection is in a strip shape, the second main gate electrode subsection extends along the first direction, and two ends of the second main gate electrode subsection are connected with two adjacent first main gate electrode subsections;
a dimension of the second main gate electrode subsection in the third direction is equal to a dimension of the first main gate electrode subsection in the third direction, the dimension of the second main gate electrode subsection in the second direction being smaller than the dimension of the first main gate electrode subsection in the second direction.
Optionally, the dimension of the first main gate electrode subsection in the second direction is equal to 3-10 times the dimension of the second main gate electrode subsection in the second direction.
Optionally, the main gate electrode further comprises a third main gate electrode subsection;
the third main gate electrode subsection is arranged in a strip-shaped structure and extends along the second direction;
one end of the third main gate electrode subsection is connected with the first main gate electrode subsection or the second main gate electrode subsection, and the other end of the third main gate electrode subsection is connected with the fine gate electrode;
a dimension of the third main gate electrode subsection in the third direction is equal to a dimension of the first main gate electrode subsection in the third direction.
Optionally, a dimension of the third main gate electrode subsection in the first direction is smaller than a dimension of the second main gate electrode subsection in the second direction and is larger than a dimension of the fine gate electrode subsection in the first direction.
Optionally, a dimension of the third main gate electrode subsection in the first direction is decreasing in a direction away from the first main gate electrode subsection or the second main gate electrode subsection.
Optionally, the shape of the first main gate electrode subsection comprises: any one of circular, rectangular, oval, annular, and irregular patterns, the area of the first main gate electrode subsection being 0.5-10 square millimeters.
Optionally, a difference between a size of the main gate electrode in the third direction and a size of the fine gate electrode in the third direction is 5 to 35 micrometers.
Optionally, the main gate electrode includes a coating metal layer and an electroplated main gate electrode, and the fine gate electrode includes an electroplated fine gate electrode;
the coating metal layer is arranged on the surface of the semiconductor substrate in the main gate opening structure, and the electroplating main gate electrode is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer;
the electroplating fine grid electrode is arranged on the surface of the semiconductor substrate in the fine grid opening structure.
Optionally, the electroplating main gate electrode includes a first main gate metal electrode layer, a second main gate metal electrode layer and a third main gate metal electrode layer, and the electroplating fine gate electrode includes a first fine gate metal electrode layer, a second fine gate metal electrode layer and a third fine gate metal electrode layer;
the first main gate metal electrode layer is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer, the second main gate metal electrode layer is arranged on one surface, far away from the coating metal layer, of the first main gate metal electrode layer, and the third main gate metal electrode layer is arranged on one surface, far away from the first main gate metal electrode layer, of the second main gate metal electrode layer;
the first fine gate metal electrode layer is arranged on the surface of the semiconductor substrate, the second fine gate metal electrode layer is arranged on the surface, far away from the semiconductor substrate, of the first fine gate metal electrode layer, and the third fine gate metal electrode layer is arranged on the surface, far away from the first fine gate metal electrode layer, of the second fine gate metal electrode layer.
In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the above solar cell.
The embodiment of the utility model provides a pair of solar cell and photovoltaic module, among the solar cell, can be through control electroplating process for electroplate the thin grid electrode in the thin grid open structure of semiconductor substrate surface insulation passivation layer, compare in the main grid electrode of electroplating in the main grid open structure of semiconductor substrate surface insulation passivation layer, have the size that has more littleer in the third direction on perpendicular to semiconductor substrate surface, consequently, can reduce the quantity of the electrically conductive thick liquids of preparation electrode among the solar cell, reduce solar cell's manufacturing cost. Meanwhile, the structure and the size of the main grid electrode welded with the connecting wires such as the welding strips are not changed, so that the connection strength between the main grid electrode and the connecting wires can be ensured, the main grid electrode is prevented from being desoldered, and the connection reliability between adjacent solar cells is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows a schematic structural diagram of a solar cell in an embodiment of the present invention;
fig. 2 shows a cross-sectional view of a solar cell in an embodiment of the invention in the direction D-D;
fig. 3 shows a cross-sectional view of a solar cell in an embodiment of the invention in the direction E-E;
fig. 4 shows a schematic structural diagram of another solar cell in an embodiment of the present invention.
Description of the figure numbering:
10-a semiconductor substrate, 20-a main grid electrode, 21-a first main grid electrode subsection, 22-a second main grid electrode subsection, 23-a third main grid electrode subsection, 30-a fine grid electrode, 40-a backlight surface conducting layer, 50-a backlight surface conducting layer, 60-a backlight surface transparent conducting layer, 70-a backlight surface transparent conducting layer, 80-a backlight surface insulating passivation layer, 90-a backlight surface insulating passivation layer, 100-a fine grid opening structure and 110-a main grid opening structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of a solar cell in an embodiment of the present invention, and the solar cell may include: a semiconductor substrate 10, and a main gate electrode 20 and a fine gate electrode 30 plated on at least one side of the semiconductor substrate 10.
The main gate electrode 20 extends along a first direction a of the surface of the semiconductor substrate 10, the fine gate electrode 30 extends along a second direction B of the surface of the semiconductor substrate 10, and the main gate electrode 20 and the fine gate electrode 30 are connected to each other.
Specifically, the semiconductor substrate 10 may be composed of monocrystalline silicon or polycrystalline silicon, and the surface of the semiconductor substrate 10 may be a textured structure having a regular or irregular shape, so as to scatter incident light and reduce the amount of light reflected from the surface of the solar cell, thereby increasing the radiation collection effect of the solar cell. After solar rays irradiate on the semiconductor substrate 10, currents can be generated on the semiconductor substrate 10 through a photovoltaic effect, the thin grid electrodes 30 arranged on the light facing surface and the light backing surface of the semiconductor substrate 10 can collect the currents generated on the semiconductor substrate 10, and the currents are converged to the main grid electrode 20 through the mutual connection of the thin grid electrodes and the main grid electrode, so that the collection and the convergence of the currents of the solar cells are completed, and then after the adjacent solar cells are communicated through connecting wires such as solder strips to form a photovoltaic module, the currents collected and converged in the plurality of solar cells can be further converged, so that power is supplied to external equipment.
The embodiment of the utility model provides an in, connect adjacent solar cell's connecting wire can be through with the main grid electrode (pad) among the solar cell weld, realize connecting wire and solar cell's welded connection, the both ends of connecting wire weld with two adjacent solar cell's electrode respectively promptly to connect two adjacent solar cell.
Furthermore, in the current large-scale solar cell manufacturing, a screen printing method is usually adopted to realize the metallization process of the solar cell, that is, the screen printing method is adopted to print the conductive paste on the surface of the semiconductor substrate, so as to form the main gate electrode and the fine gate electrode, and with the expansion of the market and the productivity of the photovoltaic industry, the continuous and stable supply of the silver paste serving as the conductive paste has become a serious test, and the cost of the conductive paste is higher due to the rising silver price, so that the consumption of the conductive paste for preparing the electrode in the solar cell is reduced, and the production cost of the solar cell can be reduced.
The embodiment of the present invention provides a semiconductor device, which can be manufactured by using the method of manufacturing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of thin gate electrodes, and the thin gate electrodes are arranged on the surface of the semiconductor substrate.
Specifically, fig. 2 shows a cross-sectional view of a solar cell in the D-D direction in an embodiment of the present invention, fig. 3 shows a cross-sectional view of a solar cell in the E-E direction in an embodiment of the present invention, and referring to fig. 2 and 3, a dimension H1 of the main gate electrode 20 on the light-facing surface and the backlight surface of the solar cell in the third direction C perpendicular to the surface of the semiconductor substrate 10 is greater than a dimension H2 of the fine gate electrode 30 in the third direction C. That is, in the solar cell, the height of the fine gate electrode 30 for collecting current generated on the semiconductor substrate 10 is smaller than the height of the main gate electrode 20 for collecting current and bonding with the connection line. In this structure, since the structure and size of the main gate electrode 20 to be bonded to the connection line such as the solder ribbon are not changed, it is possible to secure the connection strength between the main gate electrode 20 and the connection line, and to avoid the main gate electrode 20 from being detached, thereby securing the connection reliability between the adjacent solar cells. Meanwhile, the thin grid electrode 30 is only used for collecting current, so that the height of the thin grid electrode 30 can be properly reduced, the volume of the thin grid electrode 30 is reduced, the using amount of conductive paste for preparing the thin grid electrode 30 is reduced, the using amount of the conductive paste for preparing the electrode in the solar cell is reduced, and the production cost of the solar cell is reduced.
In an embodiment of the present invention, the solar cell may further include: and an insulating passivation layer. Referring to fig. 2 and 3, an insulation passivation layer may be simultaneously disposed on the backlight surface and the light-facing surface of the semiconductor substrate 10, forming a light-facing surface insulation passivation layer 80 on the light-facing surface and a backlight surface insulation passivation layer 90 on the backlight surface. The insulating passivation layer may be provided with a main gate opening structure and a fine gate opening structure, and correspondingly, the main gate electrode 20 may be an electrode deposited in the main gate opening structure of the insulating passivation layer during the electroplating process, and the fine gate electrode may be an electrode deposited in the fine gate opening structure of the insulating passivation layer during the electroplating process.
Taking the light-facing surface insulating passivation layer 80 on the light-facing surface as an example, a main gate opening structure 110 and a fine gate opening structure 100 are disposed in the light-facing surface insulating passivation layer 80, wherein the main gate electrode 20 is disposed in the main gate opening structure 110 and connected to the semiconductor substrate 10, and the fine gate electrode 30 is disposed in the fine gate opening structure 100 and connected to the semiconductor substrate 10. The insulating passivation layer may improve light absorption characteristics of the solar cell.
Specifically, the insulating passivation layer is provided with a main gate opening structure and a fine gate opening structure, and an opening structure penetrating through the insulating passivation layer can be formed in the insulating passivation layer through wet etching or laser ablation and other technologies, so that the semiconductor substrate located at the bottom of the insulating passivation layer is exposed, and then the main gate electrode and the fine gate electrode can be arranged in the main gate opening structure and the fine gate opening structure, so that the main gate electrode and the fine gate electrode can be in contact with the semiconductor substrate.
The embodiment of the utility model provides an in, can prepare different insulating passivation layer respectively on the light facing surface and the backlight surface of semiconductor substrate, for example, can prepare the insulating passivation layer that contains silicon oxide and silicon nitride at the light facing surface of semiconductor substrate, prepare the insulating passivation layer that contains aluminum oxide and silicon nitride at the backlight surface of semiconductor substrate to improve the passivation effect of solar cell light facing surface, promote solar cell's conversion efficiency.
It should be noted that, if the heights of the main gate electrode and the fine gate electrode are reduced to reduce the amount of the conductive paste, the volume of the main gate electrode welded to the connection line is reduced, and the amount of the "silver" which is a weldable material for welding the main gate electrode to the connection line is insufficient, so that the welding strength between the main gate electrode and the connection line is reduced, and the main gate electrode and the connection line are detached from each other. In addition, if the height of the main grid electrode is reduced, the connection line may be in contact with the fine grid electrode, because in general, in order to reduce the light shielding of the fine grid electrode on the solar cell, the width of the fine grid electrode is smaller, that is, the volume of the fine grid electrode is smaller, the amount of the weldable material "silver" contained in the fine grid electrode is smaller, and if the fine grid electrode is in contact with the connection line, the soldering tin coating on the surface of the connection line can dissolve and phagocytose the weldable material "silver" contained in the fine grid electrode, so that the fine grid electrode is welded and disconnected, and the current collection efficiency of the solar cell is reduced.
In summary, in the embodiment of the present invention, the solar cell includes: a semiconductor substrate, a main gate electrode and a fine gate electrode plated on at least one side of the semiconductor substrate; the main grid electrode extends along a first direction of the surface of the semiconductor substrate, the fine grid electrode extends along a second direction of the surface of the semiconductor substrate, and the main grid electrode and the fine grid electrode are connected with each other; the size of the main gate electrode in a third direction perpendicular to the surface of the semiconductor substrate is larger than the size of the fine gate electrode in the third direction. In the solar cell, in the third direction, the size of the fine grid electrode is smaller than that of the main grid electrode, namely the height of the fine grid electrode is smaller than that of the main grid electrode, so that the using amount of conductive paste for preparing the electrode in the solar cell can be reduced, and the production cost of the solar cell is reduced. Meanwhile, the structure and the size of the main grid electrode welded with the connecting wires such as the welding strips are not changed, so that the connection strength between the main grid electrode and the connecting wires can be ensured, the main grid electrode is prevented from being desoldered, and the connection reliability between adjacent solar cells is ensured.
Alternatively, referring to fig. 1, the main gate electrode 20 may include a plurality of first main gate electrode subsections 21 and a plurality of second main gate electrode subsections 22.
The first main gate electrode subsections 21 may be in a block shape, the plurality of first main gate electrode subsections 21 are arranged at intervals along the first direction a of the surface of the semiconductor substrate 10, the second main gate electrode subsection 22 may be in a strip shape, the second main gate electrode subsection 22 extends along the first direction a of the surface of the semiconductor substrate 10, two ends of the second main gate electrode subsection 22 are connected with two adjacent first main gate electrode subsections 21, the size of the second main gate electrode subsection 22 in a third direction C perpendicular to the surface of the semiconductor substrate 10 is equal to the size of the first main gate electrode subsection 21 in the third direction C, and the size of the second main gate electrode subsection 22 in the second direction B of the surface of the semiconductor substrate 10 is smaller than the size of the first main gate electrode subsection 21 in the second direction B of the surface of the semiconductor substrate 10.
In the embodiment of the present invention, the size of the main grid electrode 20 along the second direction B is not uniform, that is, the width of the main grid electrode 20 is not uniform, but the width of the first main grid electrode subsection 21 is greater than the width of the second main grid electrode subsection 22, therefore, when the main grid electrode 20 is welded to the connecting wire, the contact area between the first main grid electrode subsection 21 with a larger width and the connecting wire is larger, so as to ensure the welding strength between the main grid electrode 20 and the connecting wire, the second main grid electrode subsection 22 with a smaller width is mainly used for conducting the adjacent first main grid electrode subsection 21, so as to further reduce the amount of conductive paste used for preparing the electrode in the solar cell, and reduce the production cost of the solar cell.
Optionally, the dimension of the first main gate electrode subsection in the second direction is equal to 3-10 times the dimension of the second main gate electrode subsection in the second direction.
Optionally, the main gate electrode may further include a third main gate electrode subsection, fig. 4 shows a schematic structural diagram of another solar cell in an embodiment of the present invention, as shown in fig. 4, the third main gate electrode subsection 23 may be disposed in a strip-shaped structure, the third main gate electrode subsection 23 is disposed to extend along the second direction B of the surface of the semiconductor substrate 10, and one end of the third main gate electrode subsection 23 is connected to the first main gate electrode subsection 21 or the second main gate electrode subsection 22, and the other end of the third main gate electrode subsection 23 is connected to the fine gate electrode 30, wherein a dimension of the third main gate electrode subsection 23 in the third direction C is equal to a dimension of the first main gate electrode subsection 21 in the third direction C, that is, a height of the third main gate electrode subsection 23 is equal to a height of the first main gate electrode subsection 21 and the second main gate electrode subsection 22.
In the embodiment of the present invention, since one end of the third main gate electrode subsection 23 is connected to the first main gate electrode subsection 21 or the second main gate electrode subsection 22, and the other end of the third main gate electrode subsection 23 is connected to the fine gate electrode 30, the third main gate electrode subsection 23 can achieve the purpose of isolating the fine gate electrode 30, and avoid the contact between the connection line and the fine gate electrode 30, thereby avoiding the fine gate electrode to be disconnected by welding. Since the height of the third main gate electrode subsection 23 is equal to the height of the first main gate electrode subsection 21, the volume of the third main gate electrode subsection 23 that takes over the contact of the fine gate electrode 30 with the connection line is increased compared to the volume of the fine gate electrode 30, so that the reliability of the connection with the connection line can be improved.
Alternatively, referring to fig. 4, the size of the third main gate electrode subsection 23 in the first direction a may be smaller than the size of the second main gate electrode subsection 22 in the second direction B, so that excessive conductive paste may be prevented from being used in preparing the main gate electrode 20, and at the same time, the size of the third main gate electrode subsection 23 in the first direction a may be larger than the size of the fine gate electrode 30 in the first direction a, so that connection reliability between the third main gate electrode subsection 23 and the connection line may be ensured when the third main gate electrode subsection 23 is in contact with the connection line.
Alternatively, referring to fig. 4, the dimension of the third main gate electrode subsection 23 in the first direction a, i.e. the width of the third main gate electrode subsection 23, decreases in a direction away from the first main gate electrode subsection 21 or the second main gate electrode subsection 22. Since the third main gate electrode subsection 23 is less likely to contact the connection line in a direction away from the first main gate electrode subsection 21 or the second main gate electrode subsection 22, a portion of the third main gate electrode subsection 23 close to the first main gate electrode subsection 21 or the second main gate electrode subsection 22 may be set to have a larger width to improve the connection reliability between the third main gate electrode subsection 23 and the connection line, and a portion of the third main gate electrode subsection 23 away from the first main gate electrode subsection 21 or the second main gate electrode subsection 22 may be set to have a smaller width to save the conductive paste.
In an embodiment of the present invention, the ratio of the width of the wide portion to the width of the narrow portion of the third main gate electrode subsection 23 may be greater than 2. The third main gate electrode subsection 23 may be discontinuously arranged between the first main gate electrode subsection 21 or the second main gate electrode subsection 22 and the fine gate electrode 30.
Optionally, the shape of the first main gate electrode subsection may comprise: the area of the first main gate electrode subsection may be 0.5-10 square millimeters, in any one of a circular, rectangular, oval, annular, and irregular pattern.
For example, a first main gate electrode subsection of rectangular configuration may be provided, which may have dimensions of 1.2mm x 1mm, 0.7mm x 0.8mm or 1mm x 0.5 mm.
The embodiment of the utility model provides an in, first main grid electrode subsection is at the length of first direction A, or the area of first main grid electrode subsection, can confirm according to actual conditions, if length overlength or area are too big, then lead to solar cell's cost to be increased, if length section or area undersize, then welding strength between first main grid electrode subsection and the connecting wire reduces, the reliability of being connected between first main grid electrode subsection and the connecting wire reduces, cause the desoldering of first main grid electrode subsection easily, consequently, can synthesize cost and welding strength and confirm suitable length or area.
The embodiment of the utility model provides an in, the number of first main grid electrode subsection in the main grid electrode also can be synthesized cost and welding strength and confirm, if the number of first main grid electrode subsection in the main grid electrode is too much, then lead to solar cell's cost to be increased, if the number of first main grid electrode subsection in the main grid electrode is too little, then welding strength between first main grid electrode subsection and the connecting wire reduces, the reliability of being connected between first main grid electrode subsection and the connecting wire reduces, causes the desoldering of first main grid electrode subsection easily. Preferably, 6-10 first main gate electrode subsections can be arranged in one main gate electrode, adjacent first main gate electrode subsections are connected through a second main gate electrode subsection, and the length of the first main gate electrode subsection along the first direction is smaller than that of the second main gate electrode subsection along the first direction.
In addition, when the first main grid electrode sub-portions are welded with the connecting lines, the tensile force between the first main grid electrode sub-portions located at the edges of the solar cells and the connecting lines is large, so when a plurality of first main grid electrode sub-portions are arranged in one main grid electrode, the first main grid electrode sub-portions can be uniformly arranged along the first direction, the first main grid electrode sub-portions with high density can also be arranged at the edges of the solar cells, the first main grid electrode sub-portions with low density are arranged at the middle parts of the solar cells, namely the first main grid electrode sub-portions are arranged along the central position to the edge position in the solar cells, the spacing distance between the first main grid electrode sub-portions is in a decreasing trend, the bonding force between the first main grid electrode sub-portions and the connecting lines at the positions with large tensile force is increased, and the connection reliability between the first main grid electrode sub-portions and the connecting lines is improved.
Alternatively, the difference between the size of the main gate electrode 20 in the third direction C and the size of the fine gate electrode 30 in the third direction C may be 5 to 35 micrometers.
Referring to fig. 1, the thickness of the solar cell may be 175 micrometers, and the size of the solar cell in the first direction a is 166 mm, and the size in the second direction B is 166 mm. On both the light-facing surface and the backlight surface of the solar cell, 4 sets of main grid electrodes 20 were provided at equal intervals of 39 mm, and the main grid electrodes 20 were provided extending in the first direction a. Each set of main gate electrodes 20 has a dimension in the second direction B, i.e. a width of 1mm, and a dimension in the first direction a, i.e. a length of 155 mm, and meanwhile, the main gate electrodes 20 may include a first main gate electrode subsection 21 and a second main gate electrode subsection 22, wherein the first main gate electrode subsection 21 from head to tail in each main gate electrode 20 may be located at the edge portion of the solar cell. Meanwhile, the light facing surface and the backlight surface of the solar cell are both provided with fine grid electrodes with the size along the first direction A, namely the width of 30-100 micrometers, the size along the second direction B, namely the length of 154 millimeters, and the size along the third direction, namely the height of 10-20 micrometers, the fine grid electrodes 30 are arranged in an extending manner along the second direction B, therefore, the main grid electrodes are perpendicularly intersected with the fine grid electrodes, 78-155 fine grid electrodes 30 are arranged in the solar cell, a plurality of fine grid electrodes 30 are arranged at equal intervals at intervals of 1-2 millimeters, and the interval between adjacent fine grid electrodes 30 can be 6 millimeters.
It should be noted that, the structures and positions of the main grid electrode and the fine grid electrode in the light-facing surface and the backlight surface of the solar cell can be consistent with each other.
Optionally, the solar cell may further include a conductive layer and a transparent conductive layer, and the conductive layer and the transparent conductive layer may be disposed on both the light-facing surface and the backlight surface of the semiconductor substrate. Referring to fig. 2 and 3, a light-facing surface of the semiconductor substrate 10 may be provided with a light-facing surface conductive layer 40 and a light-facing surface transparent conductive layer 60, the light-facing surface conductive layer 40 is disposed on the light-facing surface of the semiconductor substrate 10, the light-facing surface transparent conductive layer 60 is disposed on a surface of the light-facing surface conductive layer 40 away from the semiconductor substrate 10, a light-facing surface insulating passivation layer 80 is disposed on a surface of the light-facing surface transparent conductive layer 60 away from the light-facing surface conductive layer 40, and when the fine grid opening structure 100 and the main grid opening structure 110 are a penetrating structure, the light-facing surface transparent conductive layer 60 located at the bottom of the light-facing surface insulating passivation layer 80 is exposed, so that the main grid electrode 20 and the fine grid electrode 30 can contact the light-facing surface transparent conductive layer 60.
Similarly, the backlight surface of the semiconductor substrate 10 may be provided with a backlight surface conductive layer 50 and a backlight surface transparent conductive layer 70, the backlight surface conductive layer 50 is disposed on the backlight surface of the semiconductor substrate 10, the backlight surface transparent conductive layer 70 is disposed on the side of the backlight surface conductive layer 50 far away from the semiconductor substrate 10, the backlight surface insulating passivation layer 90 is disposed on the side of the backlight surface transparent conductive layer 70 far away from the backlight surface conductive layer 50, and when the fine grid opening structure 100 and the main grid opening structure 110 are through structures, the backlight surface transparent conductive layer 70 located at the bottom of the backlight surface insulating passivation layer 90 is exposed, so that the main grid electrode 20 and the fine grid electrode 30 can be in contact with the backlight surface transparent conductive layer 70.
In the embodiment of the present invention, the light-facing surface conductive layer 40 and the backlight surface conductive layer 50 may be formed by depositing dopants in the semiconductor substrate by using a conventional doping process, and the light-facing surface conductive layer 40 and the backlight surface conductive layer 50 may also be prepared by using a Chemical Vapor Deposition (CVD) process, a low pressure CVD (lpcvd), an atmospheric pressure CVD (apcvd), a plasma enhanced CVD (pecvd), a thermal growth, or a sputtering technique.
Alternatively, the main gate electrode may include a coating metal layer and an electroplated main gate electrode, and the fine gate electrode may include an electroplated fine gate electrode. The coating metal layer is arranged on the surface of the semiconductor substrate in the main gate opening structure, the electroplating main gate electrode is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer, and the electroplating fine gate electrode is arranged on the surface of the semiconductor substrate in the fine gate opening structure.
Specifically, a conductive paste containing a conductive material may be applied (screen-printed) to a region of the semiconductor substrate corresponding to the main gate opening structure without using a printing mask, wherein the conductive paste applied in the region corresponding to the first main gate electrode subsection may form, after firing, a conductive dot which may be a precursor of the first main gate electrode subsection, and a size in the third direction, i.e., a height, of the conductive dot may be 5 to 30 micrometers; and the conductive paste applied in the region corresponding to the second main gate electrode subsection may form a metal layer after firing, which may serve as a precursor of the second main gate electrode subsection. The conductive points and the metal layer jointly form a coating metal layer in the main grid electrode, and the coating metal layer is arranged on the surface of the semiconductor substrate in the main grid opening structure.
Furthermore, the conductive point can be used as an electric connection point for electroplating, and is connected with electroplating equipment in the electroplating process, and electroplating can be carried out in the main gate opening structure and the fine gate opening structure after electrification, so that the main gate electrode and the fine gate electrode are deposited and electroplated. Specifically, the conductive points and the metal layer in the main grid opening structure are thickened to form an electroplating main grid electrode in the electroplating process, the electroplating main grid electrode is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer in the main grid opening structure, and the coating metal layer and the electroplating main grid electrode jointly form the main grid electrode of the solar cell. And directly forming an electroplating fine grid electrode in the fine grid opening structure in the electroplating process, so that the electroplating fine grid electrode is arranged on the surface of the semiconductor substrate in the fine grid opening structure to form the fine grid electrode of the solar cell.
It should be noted that the main gate opening structure in the insulating passivation layer may also be a non-through opening structure, and a fire-through conductive paste (such as an aluminum paste) may be used, so that after the conductive paste is applied (screen-printed) to a region of the semiconductor substrate corresponding to the main gate opening structure and fired, the conductive paste may fire through the non-through opening structure, thereby exposing the semiconductor substrate at the bottom of the insulating passivation layer. The damage to the semiconductor substrate when forming the through opening structure in the insulating passivation layer by wet etching or laser ablation or other techniques is reduced.
In the embodiment of the present invention, the thickness of the electroplated main gate electrode and the electroplated fine gate electrode prepared in the electroplating process may be 1 to 15 micrometers, preferably 5 to 10 micrometers. In the electroplating process, the current in the main gate opening structure can be controlled to be larger than the current in the fine gate opening structure, so that the electrodeposition rate of the main gate opening structure can be faster, and the electroplated main gate electrode deposited in the main gate opening structure is higher than the electroplated fine gate electrode deposited in the fine gate opening structure. Wherein the electroplating process is a deposition process in an acidic electroplating solution.
Optionally, the plated main gate electrode may include a first main gate metal electrode layer, a second main gate metal electrode layer, and a third main gate metal electrode layer, and the plated fine gate electrode may include a first fine gate metal electrode layer, a second fine gate metal electrode layer, and a third fine gate metal electrode layer. That is, the plated main gate electrode and the plated fine gate electrode deposited in the plating process may have a multi-layered structure.
Specifically, the first main gate metal electrode layer, the second main gate metal electrode layer and the third main gate metal electrode layer are sequentially arranged on one surface of the semiconductor substrate, and the first fine gate metal electrode layer, the second fine gate metal electrode layer and the third fine gate metal electrode layer are also sequentially arranged on one surface of the semiconductor substrate. The first main gate metal electrode layer is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer, the second main gate metal electrode layer is arranged on one surface, far away from the coating metal layer, of the first main gate metal electrode layer, and the third main gate metal electrode layer is arranged on one surface, far away from the first main gate metal electrode layer, of the second main gate metal electrode layer; the first fine gate metal electrode layer is arranged on the surface of the semiconductor substrate, the second fine gate metal electrode layer is arranged on one surface, far away from the semiconductor substrate, of the first fine gate metal electrode layer, and the third fine gate metal electrode layer is arranged on one surface, far away from the first fine gate metal electrode layer, of the second fine gate metal electrode layer.
In an embodiment of the present invention, the first main gate metal electrode layer and the first fine gate metal electrode layer may include materials such as nickel, tungsten, titanium, cobalt, etc., and the first main gate metal electrode layer and the first fine gate metal electrode layer may form a low-resistance metal silicide at an interface with the semiconductor substrate or the conductive layer (e.g., a doped polysilicon layer) through annealing heat treatment, thereby improving ohmic contact performance; the second main gate metal electrode layer and the second fine gate metal electrode layer may include aluminum, copper, silver, gold, and/or nickel, tungsten, titanium, cobalt, etc., and thus have a low resistance (e.g., a lower resistance than the first metal electrode layer) property, which may function to improve electrical characteristics; the third main gate metal electrode layer and the third fine gate metal electrode layer are portions connected to the connection lines, and thus, the third main gate metal electrode layer and the third fine gate metal electrode layer may include tin or silver, so that the third main gate metal electrode layer and the third fine gate metal electrode layer have excellent solderability, thereby enhancing the soldering strength between the remaining connection lines.
In summary, in the embodiment of the present invention, the solar cell includes: a semiconductor substrate, a main gate electrode and a fine gate electrode plated on at least one side of the semiconductor substrate; the main grid electrode extends along a first direction of the surface of the semiconductor substrate, the fine grid electrode extends along a second direction of the surface of the semiconductor substrate, and the main grid electrode and the fine grid electrode are connected with each other; the size of the main gate electrode in a third direction perpendicular to the surface of the semiconductor substrate is larger than the size of the fine gate electrode in the third direction. In the solar cell, in the third direction, the size of the fine grid electrode is smaller than that of the main grid electrode, namely the height of the fine grid electrode is smaller than that of the main grid electrode, so that the using amount of conductive paste for preparing the electrode in the solar cell can be reduced, and the production cost of the solar cell is reduced. Meanwhile, the structure and the size of the main grid electrode welded with the connecting wires such as the welding strips are not changed, so that the connection strength between the main grid electrode and the connecting wires can be ensured, the main grid electrode is prevented from being desoldered, and the connection reliability between adjacent solar cells is ensured.
In addition, the main grid electrode can also comprise a third main grid electrode subsection, one end of the third main grid electrode subsection is connected with the first main grid electrode subsection or the second main grid electrode subsection, and the other end of the third main grid electrode subsection is connected with the fine grid electrode, so that the third main grid electrode subsection can achieve the purpose of isolating the fine grid electrode, a connecting line is prevented from being in contact with the fine grid electrode, and the fine grid electrode is prevented from being welded and disconnected. Since the size of the third main gate electrode subsection in the third direction is equal to the size of the first main gate electrode subsection in the third direction, the volume of the third main gate electrode subsection replacing the fine gate electrode in contact with the connection line is increased compared with the volume of the fine gate electrode, and therefore the connection reliability between the third main gate electrode subsection and the connection line can be improved.
An embodiment of the utility model provides a photovoltaic module, including above-mentioned solar cell.
Specifically, a plurality of the solar cells may be connected by using a connecting wire, thereby obtaining a photovoltaic module.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (11)
1. A solar cell, comprising:
the gate structure comprises a semiconductor substrate, a main gate electrode and a fine gate electrode which are electroplated on at least one surface of the semiconductor substrate, and an insulating passivation layer arranged on the surface of the semiconductor substrate;
a main gate opening structure and a fine gate opening structure are arranged in the insulating passivation layer, the main gate electrode is arranged in the main gate opening structure and connected with the semiconductor substrate, and the main gate electrode extends along a first direction of the surface of the semiconductor substrate; the fine gate electrode is arranged in the fine gate opening structure and connected with the semiconductor substrate, the fine gate electrode extends along a second direction of the surface of the semiconductor substrate, and the main gate electrode is connected with the fine gate electrode;
the size of the main gate electrode in the third direction is larger than that of the fine gate electrode in the third direction; the third direction is perpendicular to the semiconductor substrate surface.
2. The solar cell of claim 1, wherein the main gate electrode comprises a plurality of first main gate electrode subsections and a plurality of second main gate electrode subsections;
the first main gate electrode subsection is in a block shape, and a plurality of first main gate electrode subsections are arranged at intervals along the first direction;
the second main gate electrode subsection is in a strip shape, the second main gate electrode subsection extends along the first direction, and two ends of the second main gate electrode subsection are connected with two adjacent first main gate electrode subsections;
a dimension of the second main gate electrode subsection in the third direction is equal to a dimension of the first main gate electrode subsection in the third direction, the dimension of the second main gate electrode subsection in the second direction being smaller than the dimension of the first main gate electrode subsection in the second direction.
3. The solar cell of claim 2, wherein the dimension of the first main gate electrode subsection in the second direction is equal to 3-10 times the dimension of the second main gate electrode subsection in the second direction.
4. The solar cell of claim 2, wherein the main gate electrode further comprises a third main gate electrode subsection;
the third main gate electrode subsection is arranged in a strip-shaped structure and extends along the second direction;
one end of the third main gate electrode subsection is connected with the first main gate electrode subsection or the second main gate electrode subsection, and the other end of the third main gate electrode subsection is connected with the fine gate electrode;
a dimension of the third main gate electrode subsection in the third direction is equal to a dimension of the first main gate electrode subsection in the third direction.
5. The solar cell of claim 4, wherein the dimension of the third main gate electrode subsection in the first direction is smaller than the dimension of the second main gate electrode subsection in the second direction and larger than the dimension of the fine gate electrode subsection in the first direction.
6. The solar cell of claim 4, wherein the dimension of the third main gate electrode subsection in the first direction decreases in a direction away from the first or second main gate electrode subsection.
7. Solar cell according to any of claims 2-6, characterized in that the shape of the first main gate electrode subsection comprises: any one of circular, rectangular, oval, annular, and irregular patterns, the area of the first main gate electrode subsection being 0.5-10 square millimeters.
8. The solar cell according to any of claims 1-6, wherein the difference between the dimension of the main gate electrode in the third direction and the dimension of the fine gate electrode in the third direction is 5-35 μm.
9. The solar cell of claim 1, wherein the primary gate electrode comprises a layer of a coated metal and an electroplated primary gate electrode, and the fine gate electrode comprises an electroplated fine gate electrode;
the coating metal layer is arranged on the surface of the semiconductor substrate in the main gate opening structure, and the electroplating main gate electrode is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer;
the electroplating fine grid electrode is arranged on the surface of the semiconductor substrate in the fine grid opening structure.
10. The solar cell of claim 9, wherein the electroplated main gate electrode comprises a first main gate metal electrode layer, a second main gate metal electrode layer, and a third main gate metal electrode layer, and the electroplated fine gate electrode comprises a first fine gate metal electrode layer, a second fine gate metal electrode layer, and a third fine gate metal electrode layer;
the first main gate metal electrode layer is arranged on one surface, far away from the semiconductor substrate, of the coating metal layer, the second main gate metal electrode layer is arranged on one surface, far away from the coating metal layer, of the first main gate metal electrode layer, and the third main gate metal electrode layer is arranged on one surface, far away from the first main gate metal electrode layer, of the second main gate metal electrode layer;
the first fine gate metal electrode layer is arranged on the surface of the semiconductor substrate, the second fine gate metal electrode layer is arranged on the surface, far away from the semiconductor substrate, of the first fine gate metal electrode layer, and the third fine gate metal electrode layer is arranged on the surface, far away from the first fine gate metal electrode layer, of the second fine gate metal electrode layer.
11. A photovoltaic module comprising the solar cell of any one of claims 1-10.
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