CN214898454U

CN214898454U - Local passivation contact battery

Info

Publication number: CN214898454U
Application number: CN202121492859.0U
Authority: CN
Inventors: 霍亭亭; 李森; 殷丽; 杜文星
Original assignee: Trina Solar Changzhou Technology Co ltd; Trina Solar Co Ltd
Current assignee: Trina Solar Changzhou Technology Co ltd; Trina Solar Co Ltd
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2021-11-26
Anticipated expiration: 2031-07-02

Abstract

The utility model relates to a local passivation contact battery, which comprises a front electrode, an N-type silicon doping layer, a P-type silicon substrate layer, a back passivation layer and a back electrode which are sequentially stacked; the back passivation layer comprises an intrinsic amorphous silicon layer, a P-type polycrystalline silicon layer and a conducting layer which are sequentially stacked; the intrinsic amorphous silicon layer is close to the P-type silicon substrate layer. Local passivation contact battery can not only improve battery efficiency and two-sided rate simultaneously on the basis that has higher open circuit voltage and fill factor, and need not laser fluting alright realize the contact and the carrier transmission of metal and silicon, has avoided the silicon surface damage that laser caused, can also save the shading area.

Description

Local passivation contact battery

Technical Field

The utility model relates to a battery technology field especially relates to a local passivation contact battery.

Background

The perc (passivated Emitter and reader cell) crystalline silicon solar cell adopts the dielectric layer as the back passivation layer, and the performance of the cell is improved due to the extra generated energy on the back, so that the research on improving the efficiency and the double-sided rate of the double-sided cell is very important.

At present, the PERC double-sided battery is usually back-printed with aluminum grid lines, and the limitation of the arrangement mode is that if the double-sided rate and the battery efficiency are improved, on one hand, the shading area of the grid lines needs to be considered, and if the shading area is larger, the short-circuit current (I) on the back side can be reduced_sc) If the shading area is small, the contact resistance of aluminum and silicon is large, and the Filling Factor (FF) is small, the shading area is a balanced choice, the plasticity of the existing aluminum paste needs to be improved, and the grid line cannot be thin; therefore, the back pattern optimization space is small. On the other hand, the back of the PERC double-sided battery with the back printed with the aluminum grid line at present needs to be subjected to laser grooving and then aluminum paste printing on a silicon nitride coating, so that aluminum-silicon contact can be formed. Laser damages the silicon surface to a certain extent, forms a recombination center and causes an open-circuit voltage (V)_oc) (ii) a decrease; some laser parts have silicon cavities, and even after aluminum paste is printed, sintered and filled, the cavities still exist, so that the contact resistance of aluminum and silicon is increased, and the laser grooving has certain process application limitation.

CN110581198A discloses a local contact passivation solar cell and a method for making the same, which includes: performing texturing treatment on a silicon wafer; respectively depositing a tunneling SiO layer on the front surface and the back surface of the silicon substrate by a thermal oxidation device₂A film; depositing a phosphorus-doped microcrystalline silicon or amorphous silicon thin film; depositing a patterned mask on the front side of a silicon waferA material; secondary texturing; phosphorus diffusion; etching; growing a passivation layer; opening the film by laser; and (4) screen printing. The disclosed local contact passivation solar cell adopts the selective carrier transport characteristic of a microcrystalline silicon/silicon oxide lamination layer to realize contact passivation, so that ohmic contact of a metal electrode is ensured, and simultaneously metal area recombination is completely eliminated; the patterning of the microcrystalline silicon is realized by adopting a mask and secondary texturing, so that local contact passivation is formed, and parasitic absorption is reduced; and a lightly-expanded region is formed and the passivation of the microcrystalline silicon layer is activated at the same time by adopting one-step diffusion, so that the process is simplified. The preparation method disclosed by the invention is suitable for large-scale industrial application, and can greatly improve the conversion efficiency of the battery and reduce the electricity consumption cost.

CN110828583A discloses a crystalline silicon solar cell with locally passivated front contact and its preparation method. The crystalline silicon solar cell comprises a front electrode, a front passivation layer, an N-type silicon doping layer, a P-type silicon substrate, a back passivation layer and a back electrode, wherein the back passivation layer is formed on the back of the P-type silicon substrate, the back electrode is formed on the back passivation layer and partially penetrates through the back passivation layer to form ohmic contact with the P-type silicon substrate, the N-type silicon doping layer is formed on the front of the P-type silicon substrate, a patterned silicon oxide thin layer is formed on the N-type silicon doping layer, and an N-type silicon oxide thin layer is formed on the silicon oxide thin layer in a covering mode⁺A polysilicon layer with a front electrode formed on N via the front passivation layer⁺On the upper surface of the type polysilicon layer and N⁺The type polysilicon layer forms an ohmic contact. The disclosed crystalline silicon solar cell reduces the recombination rate of the non-metal contact area and further reduces the recombination rate of the metal contact area.

Under the existing metal slurry condition, the battery efficiency and the double-sided rate are improved simultaneously through the back pattern, and the optimization space is very limited; in addition, after the silicon nitride film is plated on the back surface, the aluminum-silicon contact can be realized only by opening a hole by laser, but the application of the laser also brings about certain disadvantages such as damage layers on the silicon surface, cavities at the aluminum-silicon contact position and the like.

In conclusion, it is important to develop a local passivation contact cell which can improve the cell efficiency and the double-sided rate, can realize metal silicon contact and carrier transmission without laser grooving, avoid silicon surface damage caused by laser, and save the shading area.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art, the utility model aims to provide a local passivation contact battery, local passivation contact battery can not only improve battery efficiency and two-sided rate simultaneously, and need not laser fluting alright realize the contact and the carrier transmission of metal and silicon, has avoided the silicon surface damage that laser caused, can also save the shading area.

To achieve the purpose, the utility model adopts the following technical proposal:

the utility model provides a local passivation contact battery, which comprises a front electrode, an N-type silicon doping layer, a P-type silicon substrate layer, a back passivation layer and a back electrode which are sequentially stacked;

the back passivation layer comprises an intrinsic amorphous silicon layer, a P-type polycrystalline silicon layer and a conducting layer which are sequentially stacked;

the intrinsic amorphous silicon layer is close to the P-type silicon substrate layer;

the thickness of the intrinsic amorphous silicon layer is 2-10nm, such as 3nm, 5nm, 8nm, 9nm, 10nm, etc.

The local passivation contact battery of the utility model firstly utilizes the intrinsic amorphous silicon layer with excellent passivation performance as a passivation layer; secondly, a P-type polycrystalline silicon layer is arranged on the surface of the intrinsic amorphous silicon layer with a specific thickness, and the P-type polycrystalline silicon layer can prevent minority carriers in the silicon substrate from being compounded towards the surface, so that the carrier collection capacity is improved; in addition, the P-type polycrystalline silicon layer and the amorphous silicon are matched for use as a passivation layer, so that the step of back laser grooving can be omitted, the cost is saved, and the damage to a laser area and a nearby silicon structure caused by laser grooving is avoided, so that the V-shaped groove is prevented_ocDecrease; finally, the utility model discloses still set up the conducting layer, whole face is laid and is favorable to the conduction nearby of current carrier, has reduced current carrier transmission path to reduce compound probability, be of value to FF and V that promote the battery_oc。

The "intrinsic amorphous silicon layer" of the present invention is formed of amorphous silicon without impurities.

Preferably, the P-type polycrystalline silicon layer has a thickness of 30-100nm, such as 35nm, 40nm, 45nm, 50nm, 55nm, 6nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, etc.

Illustratively, the P-type polysilicon layer includes silane and at least any one of elements of the third main group.

The elements of the third main group of the utility model mainly refer to boron, aluminum and gallium.

Preferably, the thickness of the conductive layer is 10-80nm, such as 15nm, 20nm, 25nm, 30nm, 35nm, 4nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, and the like.

Illustratively, the material of the conductive layer includes aluminum-doped zinc oxide, boron-doped zinc oxide, or gallium-doped zinc oxide.

Preferably, the surface of the intrinsic amorphous silicon layer is further provided with a heavily doped layer, and the heavily doped layer is located in the region where the back electrode is located.

The utility model discloses add heavily doped layer, can increase ohmic contact, improve the contact performance of metal and silicon, reduce contact resistance and improve the carrier and collect speed, be of value to FF and V that promote the battery_oc。

Preferably, the width of the heavily doped layer is 2-5mm, such as 2mm, 2.5mm, 3mm, 4mm, 4.5mm, etc.

Illustratively, the material of the heavily doped layer comprises elements of the third main group.

Preferably, the back electrode is disposed on the heavily doped layer.

Illustratively, the material of the back electrode is silver.

Preferably, the width of the back electrode is 1-3mm, such as 1.2mm, 1.4mm, 1.6mm, 1.8mm, 2mm, 2.2mm, 2.4mm, 2.6mm, 2.8mm, etc., and is less than the width of the heavily doped layer.

Compared with the prior art, the utility model discloses following beneficial effect has:

local passivation contact battery can not only improve battery efficiency and two-sided rate simultaneously on the basis that has higher open circuit voltage and fill factor, and need not laser fluting alright realize the contact and the carrier transmission of metal and silicon, has avoided the silicon surface damage that laser caused, can also save the shading area. Partial passivation contact battery's open circuit voltage is more than 0.698V, and fill factor is more than 82.87%, and battery efficiency is more than 23.32%, and double-sided rate is more than 73.2%.

Drawings

FIG. 1 is a schematic diagram of a partially passivated contact cell as described in example 1;

wherein, 1-front electrode; 2-N type silicon doping layer; a 3-P type silicon substrate layer; 4-a back side passivation layer; 5-a back electrode; 41-intrinsic amorphous silicon layer; 42-heavily doped layer; a 43-P type polysilicon layer; 44-conductive layer.

Detailed Description

To facilitate understanding of the present invention, the present invention has the following embodiments. It should be understood by those skilled in the art that the described embodiments are merely provided to assist in understanding the present invention and should not be construed as specifically limiting the present invention.

Example 1

The embodiment provides a local passivation contact battery, a schematic structural diagram of which is shown in fig. 1, wherein the local passivation contact battery is composed of a front electrode 1, an N-type silicon doped layer 2, a P-type silicon substrate layer 3, a back passivation layer 4 and a back electrode 5 which are sequentially stacked;

the back passivation layer comprises an intrinsic amorphous silicon layer 41, a heavily doped layer 42, a P-type polycrystalline silicon layer 43 and a conducting layer 44 which are sequentially stacked;

the intrinsic amorphous silicon layer is close to the P-type silicon substrate layer.

The preparation method of the local passivation contact battery comprises the following steps:

(1) sequentially stacking an N-type silicon doping layer and a P-type silicon substrate layer, and arranging intrinsic amorphous silicon on the P-type silicon substrate layer through physical vapor deposition to form an intrinsic amorphous silicon layer with the thickness of 5 nm;

(2) screen printing boron paste (the width of a grid line is 1.3mm) in the subsequent area where the back electrode is located, and drying to form a heavily doped layer;

(3) adding SiH₄Gas and BH₃Depositing gas on the intrinsic amorphous silicon layer in a plasma enhanced chemical vapor deposition mode to form a P-type polycrystalline silicon layer with the thickness of 50 nm;

(4) depositing boron-doped zinc oxide on the P-type polycrystalline silicon layer in a magnetron sputtering mode to form a conductive layer with the thickness of 30nm to obtain a back passivation layer;

(5) and forming a back electrode by using silver paste in a screen printing mode (the width of a grid line is 1.5mm), forming a front electrode in the same mode, drying, and sintering at 250 ℃ to obtain the local passivation contact battery.

Example 2

The embodiment provides a local passivation contact battery, which comprises a front electrode, an N-type silicon doping layer, a P-type silicon substrate layer, a back passivation layer and a back electrode which are sequentially stacked;

the back passivation layer comprises an intrinsic amorphous silicon layer, a heavily doped layer, a P-type polycrystalline silicon layer and a conducting layer which are sequentially stacked;

(1) sequentially stacking an N-type silicon doping layer and a P-type silicon substrate layer, and arranging intrinsic amorphous silicon on the P-type silicon substrate layer through physical vapor deposition to form an intrinsic amorphous silicon layer with the thickness of 2 nm;

(2) screen printing (the width of a grid line is 2mm) liquid slurry doped with boron and gallium in a subsequent area where the back electrode is located, and drying to form a heavily doped layer;

(3) adding SiH₄And BH₃Depositing on the intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition to form a P-type polycrystalline silicon layer with the thickness of 30 nm;

(4) depositing aluminum-doped zinc oxide on the P-type polycrystalline silicon layer in a magnetron sputtering mode to form a conductive layer with the thickness of 20nm to obtain a back passivation layer;

(5) and forming a back electrode by using silver paste in a screen printing mode (the width of a grid line is 1mm), forming a front electrode in the same mode, drying, and sintering at 180 ℃ to obtain the local passivation contact battery.

Example 3

(1) sequentially stacking an N-type silicon doping layer and a P-type silicon substrate layer, and arranging intrinsic amorphous silicon on the P-type silicon substrate layer through physical vapor deposition to form an intrinsic amorphous silicon layer with the thickness of 10 nm;

(2) screen printing (the width of a grid line is 3mm) liquid boron paste in a subsequent area where the back electrode is located, and drying to form a heavily doped layer;

(3) adding SiH₄And BH₃Depositing on the intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition to form a P-type polycrystalline silicon layer with the thickness of 80 nm;

(4) depositing gallium-doped zinc oxide on the P-type polycrystalline silicon layer in a magnetron sputtering mode to form a conductive layer with the thickness of 40nm to obtain a back passivation layer;

(5) and forming a back electrode by using silver paste in a screen printing mode (the width of a grid line is 1mm), forming a front electrode in the same mode, drying, and sintering at 250 ℃ to obtain the local passivation contact battery.

Comparative example 1

The difference between the comparative example and the example 1 is that the back passivation layer is a 10nm thick aluminum oxide layer and a 75nm thick silicon nitride layer which are sequentially stacked, the aluminum oxide layer is close to the P-type silicon substrate layer, then the groove is formed by laser, the silver back electrode and the aluminum grid line are printed by silk screen printing, and finally the local passivation contact cell is obtained by sintering.

Performance testing

The partially passivated contact cells described in examples 1-3 and comparative example 1 were tested using a line IV tester, and the relevant data included: open circuit voltage (V)_oc) Short-circuit current (I)_sc) Fill Factor (FF), cell efficiency and bifacial rate.

TABLE 1

	V_oc/V	I_sc/A	FF/％	Cell efficiency/%)	Double face ratio/%
						Example 1	0.701	11.016	82.95	23.36	73.2
Example 2	0.698	11.025	83.11	23.33	74.5
						Example 3	0.702	10.992	82.87	23.32	74.6
Comparative example 1	0.694	11.281	81.54	23.29	69.7

The analysis table 1 data can know that the open circuit voltage of local passivation contact battery is more than 0.698V, and the fill factor is more than 82.87%, and battery efficiency is more than 23.32%, and double-sided rate is more than 73.2%, local passivation contact battery still has higher battery efficiency and double-sided rate simultaneously on the basis that has higher open circuit voltage and fill factor.

As can be seen from the analysis of comparative example 1 and example 1, the performance of comparative example 1 is inferior to that of example 1, which proves that the back passivation layer of the present invention is advantageous for the performance of the local passivation contact cell, i.e., the local passivation contact cell performance of the present invention is superior to that of the PERC prepared by the conventional process in the prior art.

The applicant states that the present invention is described in detail by the above embodiments, but the present invention is not limited to the above detailed method, i.e. the present invention is not meant to be implemented by relying on the above detailed method. It should be clear to those skilled in the art that any improvement of the present invention, to the equivalent replacement of each raw material of the present invention, the addition of auxiliary components, the selection of specific modes, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A local passivation contact battery is characterized by comprising a front electrode, an N-type silicon doping layer, a P-type silicon substrate layer, a back passivation layer and a back electrode which are sequentially stacked;

the thickness of the intrinsic amorphous silicon layer is 2-10 nm.

2. The locally passivated contact cell according to claim 1 wherein the P-type polysilicon layer has a thickness of 30-100 nm.

3. The locally passivated contact cell according to claim 1 or 2, wherein the thickness of the conductive layer is 10-80 nm.

4. The locally passivated contact cell according to claim 1 or 2 wherein the intrinsic amorphous silicon layer is further provided with a heavily doped layer on the surface, the heavily doped layer being located in the region of the back electrode.

5. The locally passivated contact cell according to claim 4 wherein the width of the heavily doped layer is 2-5 mm.

6. The locally passivated contact cell of claim 4 wherein the back electrode is disposed on the heavily doped layer.

7. The locally passivated contact cell according to claim 6 wherein the width of the back side electrode is 1-3mm and is less than the width of the heavily doped layer.