CN214625075U - Nitride semiconductor element - Google Patents

Nitride semiconductor element Download PDF

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CN214625075U
CN214625075U CN202120309052.2U CN202120309052U CN214625075U CN 214625075 U CN214625075 U CN 214625075U CN 202120309052 U CN202120309052 U CN 202120309052U CN 214625075 U CN214625075 U CN 214625075U
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nitride semiconductor
semiconductor layer
type nitride
semiconductor element
type
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闵大泓
尹俊皓
郭雨澈
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Seoul Viosys Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

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Abstract

A nitride semiconductor device is provided. The nitride semiconductor element according to an embodiment includes: a first n-type nitride semiconductor layer having an irregular concave-convex surface; and a second n-type nitride semiconductor layer disposed above the first n-type nitride semiconductor layer and forming an interface therebetween, wherein a silicon concentration of the interface is greater than silicon concentrations in the first and second n-type nitride semiconductor layers, and a threading dislocation density in the second n-type nitride semiconductor layer is lower than a threading dislocation density in the first n-type nitride semiconductor layer.

Description

Nitride semiconductor element
Technical Field
The present invention relates to a light emitting diode, and more particularly, to a nitride semiconductor device having an in-situ etching layer and a method for manufacturing the same.
Background
The nitride semiconductor may be used as a light source of a display device, a signal lamp, a lighting device, or an optical communication device, and may be used for a light emitting diode (light emitting diode) or a laser diode (laser diode) that emits ultraviolet, blue, green, or yellow light. Also, the present invention can be applied to a Heterojunction Bipolar Transistor (HBT), a High Electron Mobility Transistor (HEMT), and the like.
For nitride semiconductors, a lattice-matched substrate is not easily obtained, and thus is generally grown on a hetero-substrate such as a sapphire substrate, a silicon carbide substrate, or a silicon substrate. Accordingly, the nitride semiconductor grown on the substrate as described above has about 1E9/cm2The above relatively high Threading Dislocation Density (TDD).
Threading dislocations provide electron trap sites to induce non-luminescent recombination or provide current leakage paths. Further, when an overvoltage such as static electricity is applied to the semiconductor element, current is concentrated by threading dislocation, and damage caused by electrostatic discharge (ESD) occurs.
In order to compensate for the poor electrostatic discharge characteristics of the nitride semiconductor element, a zener diode may be used together with the nitride semiconductor element. However, there is a problem in that the overall product cost and the process time are increased due to the use of the zener diode.
As another scheme, a substrate lattice-matched with a nitride semiconductor such as a GaN substrate may be used, but the manufacturing cost of the GaN substrate is very high, and thus there is a problem in that it is difficult to apply except for a specific element such as a laser.
In addition, a technique of reducing the threading dislocation density by utilizing epitaxial lateral overgrowth (epitaxial lateral overgrowth) is being used. For example, for epitaxial lateral overgrowth, a mask pattern may be formed and a gallium nitride semiconductor may be grown using the mask pattern to reduce the threading dislocation density.
However, in order to form a mask pattern of a specific structure, it is necessary to take out a wafer from a deposition apparatus for a nitride semiconductor layer, then deposit and pattern a mask layer, and then deposit the nitride semiconductor layer again, so that there is a problem in that a process time increases.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to a nitride semiconductor device and a method for manufacturing the same, which reduces threading dislocation density by using in-situ etching.
It is another object of the present invention to provide a nitride semiconductor device and a method for manufacturing the same, which can improve the electrostatic discharge characteristics by using the in-situ etching technique.
According to an embodiment of the present invention, a nitride semiconductor device includes: a first n-type nitride semiconductor layer having an irregular concave-convex surface; and a second n-type nitride semiconductor layer disposed over the first n-type nitride semiconductor layer and forming an interface therebetween.
In addition, the silicon concentration at the interface may be more than 10 times the silicon concentration in the first n-type nitride semiconductor layer or the second n-type nitride semiconductor layer.
The nitride semiconductor element may further include: and a hetero-substrate positioned under the first n-type nitride semiconductor layer.
In one embodiment, the foreign substrate may be a patterned sapphire substrate.
The nitride semiconductor element may further include a nitride semiconductor layer contacting a lower surface of the first n-type nitride semiconductor layer and forming a lower interface therebetween, wherein the interface may be rougher than the lower interface.
The nitride semiconductor element may further include a nitride semiconductor layer contacting an upper surface of the second n-type nitride semiconductor layer and forming an upper interface therebetween, wherein the interface may be rougher than the upper interface.
The nitride semiconductor element may further include: an active layer disposed on the second n-type nitride semiconductor layer; and a p-type nitride semiconductor layer disposed on the active layer, the nitride semiconductor element being capable of emitting light in an ultraviolet or visible light region.
The irregular uneven surface of the first n-type nitride semiconductor layer may include being SiH-doped in the absence of a nitrogen source gas4And etching the formed concave-convex surface.
Further, the irregular uneven surface of the first n-type nitride semiconductor layer may include a surface that passes through the SiH4Together with introduction of H2To etch the resulting uneven surface.
In one embodiment, the second n-type nitride semiconductor layer may be thicker than the first n-type nitride semiconductor layer.
In one embodiment, the interface may have a silicon concentration greater than the silicon concentration in the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer.
In one embodiment, the threading dislocation density in the second n-type nitride semiconductor layer may be lower than the threading dislocation density in the first n-type nitride semiconductor layer.
A nitride semiconductor element manufacturing method according to still another embodiment of the present invention includes the steps of: a substrate is loaded in the chamber; introducing a source gas of a group III element and a source gas of nitrogen into the chamber and growing a first n-type nitride semiconductor layer on the substrate; blocking the introduction of the source gas of the group III element and the source gas of nitrogen; introducing SiH into the chamber4Gas and etch the surface of the said first n-type nitride semiconductor layer; introducing a source gas of a group III element and a source gas of nitrogen into the chamber and growing a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the etched surface.
According to an embodiment of the present invention, when the first n-type nitride semiconductor layer is formed with an irregular uneven surface, specifically, thermally etched V-pits (TEV), and thus the second n-type nitride semiconductor layer is grown thereon, threading dislocations of the grown second n-type nitride semiconductor layer are reduced, that is, the threading dislocation density in the second n-type nitride semiconductor layer is lower than the threading dislocation density in the first n-type nitride semiconductor layer.
According to the utility model discloses an embodiment, through utilizing the SiH4The surface of the first n-type nitride semiconductor layer is etched and then a second n-type nitride semiconductor layer is grown on the etched first n-type nitride semiconductor layer, so that the threading dislocation density of the second n-type nitride semiconductor layer can be reduced. Accordingly, a nitride semiconductor element in which the threading dislocation density is reduced by growing a semiconductor on the second n-type nitride semiconductor layer can be provided.
Further, the first n-type nitride semiconductor layer may be etched using an in-situ etching technique, and thus, a nitride semiconductor element in which electrostatic discharge characteristics are improved by using an in-situ process may be provided.
Drawings
Fig. 1 is a schematic cross-sectional view for explaining a nitride semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic view for explaining a method of manufacturing a nitride semiconductor element according to an embodiment of the present invention.
Fig. 3a, 3b, and 3c are SEM images showing the surface of the first n-type nitride semiconductor layer according to various etching techniques.
Fig. 4a, 4b and 4c are CL images for explaining the reduction of threading dislocations using the in-situ etching technique.
Fig. 5 is a Cathodoluminescence (CL) image showing a cross section of a nitride semiconductor element manufactured by applying an in-situ etching technique.
Fig. 6 is a diagram for explaining electrostatic discharge characteristics of the nitride semiconductor element according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below are provided as examples in order to fully convey the concept of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, and may be embodied in other forms. In the drawings, the widths, lengths, thicknesses, and the like of the constituent elements may be exaggerated for convenience. When a description is made that one constituent element is located "on" or "above" another constituent element, the description includes not only a case where each of the portions is located "directly" on "or" above "another portion, but also a case where another constituent element is interposed between each constituent element and another constituent element. Throughout the specification, the same reference numerals denote the same constituent elements.
According to an embodiment of the present invention, a nitride semiconductor device includes: a first n-type nitride semiconductor layer having an irregular concave-convex surface; and a second n-type nitride semiconductor layer disposed above the first n-type nitride semiconductor layer and forming an interface therebetween, wherein a silicon concentration of the interface is greater than silicon concentrations in the first and second n-type nitride semiconductor layers, and a threading dislocation density in the second n-type nitride semiconductor layer is lower than a threading dislocation density in the first n-type nitride semiconductor layer.
The irregular uneven surface may be formed using an in-situ etching technique, and thus, the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer may be formed by an in-situ process.
In addition, the interface may have a silicon concentration that is greater than 10 times the silicon concentration in the first n-type nitride semiconductor layer or the second n-type nitride semiconductor layer.
The nitride semiconductor element may further include: and a hetero-substrate positioned under the first n-type nitride semiconductor layer. In one embodiment, the foreign substrate may be a patterned sapphire substrate.
The nitride semiconductor element may further include a nitride semiconductor layer contacting a lower surface of the first n-type nitride semiconductor layer and forming a lower interface therebetween, wherein the interface may be rougher than the lower interface.
The nitride semiconductor element may further include a nitride semiconductor layer contacting an upper surface of the second n-type nitride semiconductor layer and forming an upper interface therebetween, wherein the interface may be rougher than the upper interface.
The nitride semiconductor element may further include: an active layer disposed over the second n-type nitride semiconductor layer; and a p-type nitride semiconductor layer disposed on the active layer, the nitride semiconductor element being capable of emitting light in an ultraviolet or visible light region.
The irregular uneven surface of the first n-type nitride semiconductor layer may be SiH-free with a nitrogen-free source gas4And etching to form the mask. Further, the irregular concave-convex surface of the first n-type nitride semiconductor layer may be formed by reaction with the SiH4Together with introduction of H2Is etched to form.
In one embodiment, the second n-type nitride semiconductor layer may be thicker than the first n-type nitride semiconductor layer.
A nitride semiconductor element manufacturing method according to still another embodiment of the present invention includes the steps of: a substrate is loaded in the chamber; introducing a source gas of a group III element and a source gas of nitrogen into the chamber and growing a first n-type nitride semiconductor layer on the substrate; blocking the introduction of the source gas of the group III element and the source gas of nitrogen; introducing SiH into the chamber4Gas and etch the surface of the said first n-type nitride semiconductor layer; introducing a source gas of a group III element and a source gas of nitrogen into the chamber and growing a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the etched surface.
By introducing a source gas which blocks nitrogen and using SiH4A large number of thermally etched V-pits (TEV) may be formed on the surface of the first n-type nitride semiconductor layer, which may be utilized to reduce threading dislocations of the second n-type nitride semiconductor layer.
In particular, by blocking the introduction of the source gas of nitrogen, the generation of silicon nitride islands having uneven sizes can be suppressed.
Further, the SiH may be introduced4Blocking N during etching of the surface of the first N-type nitride semiconductor layer by gas2Gases and a source gas of nitrogen are introduced into the chamber.
In one embodiment, the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer may be n-type GaN.
The nitride semiconductor element manufacturing method may further include the steps of: and growing an active layer and a p-type nitride semiconductor layer on the second n-type nitride semiconductor layer.
In addition, the substrate may be a patterned sapphire substrate.
As the surface of the first n-type nitride semiconductor layer is etched, the roughness of the surface of the first n-type nitride semiconductor layer increases.
In one embodiment, SiH may be introduced into the chamber4Are introduced together with H2A gas.
In an embodiment, the second n-type nitride semiconductor layer has a lower threading dislocation density than the first n-type nitride semiconductor layer.
Embodiments of the present invention will be specifically described below with reference to the drawings.
Fig. 1 is a schematic cross-sectional view for explaining a nitride semiconductor device according to an embodiment of the present invention.
Referring to fig. 1, the nitride semiconductor element may include a substrate 21, a lower nitride semiconductor layer 23, a high-temperature buffer layer 25, an intermediate layer 27, a first n-type semiconductor layer 29a, a second n-type semiconductor layer 29b, an active layer 31, and a p-type nitride semiconductor layer 33.
The substrate 21 is used for growing the gallium nitride semiconductor layer, and a heterogeneous substrate such as a sapphire substrate, a SiC substrate, a Si substrate, or a spinel substrate can be used. In particular, the substrate 21 may be a patterned sapphire substrate.
The lower nitride semiconductor layer 23 fills the region between the projections on the substrate 21. The lower nitride semiconductor layer 23 may cover the projections on the substrate 21. The lower nitride semiconductor layer 23 may be formed as a single layer or a plurality of layers. In particular, the lower nitride semiconductor layer 23 may include a low temperature buffer layer. The low-temperature buffer layer may be formed on the substrate 21 using (Al, Ga) N at a low temperature of 400 to 600 c, and may be formed using GaN or AlN as an example. The low-temperature buffer layer may be formed, for example, with a thickness of about 25 nm. The lower nitride semiconductor layer 23 may be formed using, for example, an undoped layer.
In order to alleviate defects such as dislocations generated between substrate 21 and n-type nitride semiconductor layer 25, high-temperature buffer layer 25 may be grown at a relatively higher temperature than lower nitride semiconductor layer 23. The high temperature buffer layer 25 may be formed using undoped GaN or GaN doped with n-type impurities. However, the threading dislocation formed in the lower nitride semiconductor layer 23 may be transferred to the high temperature buffer layer 25.
The intermediate layer 27 may contain Al. For example, the intermediate layer 27 may be formed using AlGaN, AlInGaN, or AlInN. The intermediate layer 27 may assist in the lateral direction dispersion of electrons.
The first n-type nitride semiconductor layer 29a is a nitride semiconductor layer doped with an n-type impurity, and may be formed using a nitride semiconductor layer doped with Si, for example. The doping concentration of Si doped to the first n-type nitride semiconductor layer 29a may be 5E18/cm2To 5E19/cm2Within the range of (1).
The first n-type nitride semiconductor layer 29a may be grown under a growth pressure of, for example, about 150 Torr (Torr) to 200 Torr (cvd) at 1000 ℃ to 1200 ℃ (e.g., 1050 ℃ to 1100 ℃) by supplying a source gas of a group III element and a source gas of nitrogen into the chamber using a Metal Organic Chemical Vapor Deposition (MOCVD) technique. The threading dislocation formed at the high-temperature buffer layer 25 may be generally transferred to the first n-type nitride semiconductor layer 29 a.
In addition, the first n-type nitride semiconductor layer 29a may have an irregular uneven surface. The irregular concave-convex surface can be formed by adding SiH4Gas is introduced into the chamber and formed by surface etching. In this case, H may be introduced together to maintain the temperature in the chamber2A gas. By the surface etching, the end portions of the threading dislocations exposed to the surface of the first n-type nitride semiconductor layer 29a are etched relatively quickly, so that V-shaped pits can be formed. These V-shaped pits may be referred to as thermally etched V-pits (TEV). Therefore, a recess can be generally formed at the end portion of these threading dislocations. The distance between the peaks and valleys of the irregular uneven structure is smaller than the thickness of the first n-type nitride semiconductor layer 29 a.
The second n-type nitride semiconductor layer 29b is grown on the first n-type nitride semiconductor layer 29 a. The second n-type nitride semiconductor layer 29b is a nitride-based semiconductor layer doped with n-type impurities, and may be formed using a nitride semiconductor layer doped with Si, for example. The doping concentration of Si doped to the second n-type nitride semiconductor layer 29b may be 5E18/cm2To 5E19/cm2Within the range of (1). In one embodiment, the Si doping concentration in the second n-type nitride semiconductor layer 29b may be substantially the same as the Si doping concentration in the first n-type nitride semiconductor layer 29 a. The second n-type nitride semiconductor layer 29b may be grown in the same chamber under the same or similar conditions as those of the first n-type nitride semiconductor layer 29 a.
An interface 30 is formed between the second n-type nitride semiconductor layer 29b and the first n-type nitride semiconductor layer 29 a. Since the first n-type nitride semiconductor layer 29a has an irregular uneven surface, the interface between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b has a relatively rougher shape than the other interfaces. For example, the interface 30 has a shape rougher than any lower interface between the first n-type nitride semiconductor layer 29a and the high-temperature buffer layer 25. Also, interface 30 has a shape that is rougher than any upper interface formed between second n-type nitride semiconductor layer 29b and p-type nitride semiconductor layer 33.
The silicon concentration in the interface 30 is higher than the silicon concentration in the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29 b. For example, the silicon concentration in the interface 30 may be more than 10 times the silicon concentration in the first n-type nitride semiconductor layer 29a or the second n-type nitride semiconductor layer 29 b. Si accumulated at the interface 30 can prevent the threading dislocation from transferring to the second n-type nitride semiconductor layer 29 b.
Threading dislocations within the first n-type nitride semiconductor layer 29a may be blocked at the interface 30 or may be bent in the lateral direction to disappear near the interface 30, and therefore, the threading dislocation density within the second n-type nitride semiconductor layer 29b is lower than that within the first n-type nitride semiconductor layer 29 a.
The second n-type nitride semiconductor layer 29b may be thicker than the first n-type nitride semiconductor layer 29a, and thus, the V-shaped pits formed on the surface of the first n-type nitride semiconductor layer 29a may be completely covered by the second n-type nitride semiconductor layer 29 b. Further, the upper surface of the second n-type nitride semiconductor layer 29b may be flatter than the surface of the first n-type nitride semiconductor layer 29 a.
The active layer 31 is disposed on the second n-type nitride semiconductor layer 29 b. Another nitride semiconductor layer, for example, a superlattice layer, may be added between the active layer 31 and the second n-type nitride semiconductor layer 29 b.
The active layer 31 may be formed using a nitride semiconductor layer that emits light in the ultraviolet or visible light region. The active layer 31 may have a single quantum well structure or a Multiple Quantum Well (MQW) structure in which quantum barrier layers and quantum well layers are alternately stacked. The quantum barrier layer may be formed using a nitride semiconductor layer of GaN, InGaN, AlGaN, AlInGaN, or the like having a wider band gap than the quantum well layer.
The quantum well layer is formed using a nitride semiconductor layer having a relatively narrower band gap than the quantum barrier layer, and may be formed using a gallium nitride semiconductor layer such as InGaN, for example. Light of a desired wavelength can be realized by the composition ratio of the quantum well layer.
The p-type nitride semiconductor layer 33 may be formed using a semiconductor layer doped with a p-type impurity such as Mg. The p-type nitride semiconductor layer 33 may be a single layer or a plurality of layers, and may include a p-type cladding layer and a p-type contact layer. Also, a transparent electrode such as ITO or a reflective metal such as Al may be located on the p-type nitride semiconductor layer 33. Further, although not shown, an electron blocking layer may be interposed between the active layer 31 and the p-type nitride semiconductor layer 33.
In the present embodiment, a light emitting diode including the active layer 31 is described as an example of a nitride semiconductor element, but the present invention is not limited thereto. For example, the nitride semiconductor device of the present invention includes a Heterojunction Bipolar Transistor (HBT) or a High Electron Mobility Transistor (HEMT) including the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29 b.
Fig. 2 is a schematic view for explaining a method of manufacturing a nitride semiconductor element according to an embodiment of the present invention. Here, the growth of the first n-type nitride semiconductor layer 29a, the generation of TEV by surface etching, and the growth of the second n-type nitride semiconductor layer 29b will be mainly described.
Referring to fig. 1 and 2, first, a substrate 21 is loaded in a chamber. The chamber provides an environment for growing the nitride semiconductor layer using the MOCVD technique.
The lower nitride semiconductor layer 23, the high-temperature buffer layer 25, and the intermediate layer 27 may be sequentially grown on the substrate 21. These layers may be grown in situ using conventional techniques.
Subsequently, the first n-type nitride semiconductor layer 29a is grown. The first n-type nitride semiconductor layer 29a may be grown at the first temperature T1 for a predetermined time. The first temperature may be, for example, about 1100 ℃. The first n-type nitride semiconductor layer 29a may be formed by mixing a source gas of a group III element such as TMG and a source gas such as NH3Is introduced into the chamber to grow. At this time, N2And H2May be introduced together as an ambient gas or carrier gas. And, for doping Si, such as SiH may be added4Into the chamber.
When the growth of the first n-type nitride semiconductor layer 29a is completed,the introduction of the source gas of the group III element and the source gas of nitrogen is blocked. May also block nitrogen-containing gases (e.g., N)2Gas) is introduced. H2The gas may be continuously introduced into the chamber, and the gas within the chamber is exhausted to the outside by the vacuum pump. In addition, SiH4The gas may be exhausted through a bypass before being introduced into the chamber.
After a predetermined time (e.g., about 10 seconds) has elapsed to sufficiently exhaust the nitrogen source gas and the source gas of the group III element in the chamber, SiH4Gas will be introduced into the chamber. H2The gas may be mixed with SiH4The gases are introduced into the chamber together. With introduction of SiH4The gas, the surface of the first n-type nitride semiconductor layer 29a is etched to form TEV. The surface of the first n-type nitride semiconductor layer 29a is etched using an in-situ etching technique, so that vacuum breakage of the chamber does not occur. After performing etching for a predetermined time (e.g., about 5 minutes), a source gas of a group III element such as TMG and the like and NH3Is again introduced into the chamber, thereby growing the second n-type nitride semiconductor layer 29 b.
By SiH4Surface etching of gas or at the initial stage of growth of the second n-type nitride semiconductor layer 29b, Si of high concentration may accumulate on the surface of the first n-type nitride semiconductor layer 29 a.
In addition, threading dislocations of the first n-type nitride semiconductor layer 29a may be blocked by Si or the like when the second n-type nitride semiconductor layer 29b is grown, or may be lost by changing the path in the lateral direction.
Subsequently, the active layer 31 and the p-type nitride semiconductor layer 33 may be grown on the second n-type nitride semiconductor layer 29b, after which the substrate 21 is taken out to the outside of the chamber, and a nitride semiconductor element may be manufactured through various processing processes.
According to the present embodiment, by using SiH4To etch the surface of the first n-type nitride semiconductor layer 29a, the density of threading dislocations in the nitride semiconductor layer can be greatly reduced using an in-situ technique that increases the process time by only a few minutes.
In the present embodiment, the growth step of the first n-type nitride semiconductor layer 29a, the degassing step, the surface etching step, and the growth step of the second n-type nitride semiconductor layer 29a may all be performed at the same temperature. However, the present invention is not necessarily limited thereto, and the temperature may be adjusted in each step.
Fig. 3a, 3b, and 3c are SEM images showing the surface of the first n-type nitride semiconductor layer according to various etching techniques. Here, FIG. 3a shows that no SiH is introduced in the surface etching step4But only introduce H2And the surface of the etched first n-type nitride semiconductor layer 29a, shown in FIG. 3b as H2Introducing SiH together4And NH3The surface of the first n-type nitride semiconductor layer 29a thereafter, and FIG. 3c shows that only H is introduced2And SiH4And the surface of the etched first n-type nitride semiconductor layer 29 a.
Referring to fig. 3a, it can be observed that surface of first n-type nitride semiconductor layer 29a is covered with H2Etching, but no V-shaped pits were formed.
With reference to FIG. 3b, SiH is introduced together4And NH3In the case of (1), by SiH4And NH3To form islands of silicon nitride. The islands are of irregular size and are arranged irregularly. The islands are expected to cover the ends of threading dislocations. However, due to the islands, threading dislocations may be formed again on the second n-type nitride semiconductor layer 29b grown on the islands. And, since SiH is introduced together4And NH3Etching of the first n-type nitride semiconductor layer 29a occurs while the islands are formed. Accordingly, the second n-type nitride semiconductor layer 29b covering the islands needs to be grown relatively thick, for example, twice or more as thick as the first n-type nitride semiconductor layer 29a, in order to planarize the upper surface thereof. Accordingly, the process time is increased. Further, islands formed of silicon nitride may remain between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b to reduce the extraction efficiency of light generated from the active layer.
Referring to FIG. 3c, NH is not introduced3To introduce H2And SiH4In the case of (2), a large number of small V-shapes are formedAnd (4) pits. V-pits are understood to be SiH-pits through a gallium nitride layer4And etching the substrate. At this time, the V-shaped pits can be more easily formed at the ends of the threading dislocations.
As a result of measuring the surface roughness with an Atomic Force Microscope (AFM), the surface roughness of the first n-type nitride semiconductor layer 29a of fig. 3c has an Ra value of about 1.78nm and an Rq value of about 2.27nm in a region having a size of 2 μm × 2 μm. In contrast, without surface etching, first n-type nitride semiconductor layer 29a has Ra of about 0.176nm and Rq of about 0.140 in a region of the same size. Therefore, it is found that the surface of the first n-type nitride semiconductor layer 29a is coated with SiH4And (6) etching.
Fig. 4a, 4b and 4c are CL images for explaining the reduction of threading dislocations using the in-situ etching technique. Here, each CL image shows the surface of the second n-type nitride semiconductor layer 29 b.
The second n-type nitride semiconductor layer of fig. 4a is grown on the first n-type nitride semiconductor layer 29a without etching the surface of the first n-type nitride semiconductor layer 29 a. The second n-type nitride semiconductor layer of FIG. 4b is formed using SiH as in FIG. 3b4And NH3Silicon nitride islands are formed on the first n-type nitride semiconductor layer 29a and then grown thereon. The second n-type nitride semiconductor layer of FIG. 4c is formed using SiH as in FIG. 3c4To etch the first n-type nitride semiconductor layer 29a and then grow on the first n-type nitride semiconductor layer 29 a.
Referring to FIGS. 4a, 4b and 4c, SiH is used4Without using NH3The number and size of threading dislocations of the embodiment of fig. 4c to etch the first n-type nitride semiconductor layer 29a are minimized. The sample of fig. 4a, which was not surface etched, had a significant number of threading dislocations agglomerated and caked, and a significant number of threading dislocations agglomerated and caked were also observed from the sample of fig. 4b, which formed silicon nitride islands. In contrast, the size of threading dislocations observed for the embodiment of fig. 4c is very small.
Fig. 5 is a Cathodoluminescence (CL) image showing a cross section of a nitride semiconductor element manufactured by applying an in-situ etching technique.
Referring to fig. 5, the interface 30 between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b can be clearly confirmed. The interface 30 is rougher than the interface between the first n-type nitride semiconductor layer 29a and the high-temperature buffer layer 25. Further, the height of interface 30 is found to be smaller than the thickness of first n-type nitride semiconductor layer 29 a.
In addition, in order to compare the electrical characteristics of the nitride semiconductor element according to whether TEV is applied or not, the light emitting diode of the example to which TEV is applied and the light emitting diode of the comparative example to which TEV is not applied were manufactured, and the reverse current Ir and the reverse voltage Vr were measured. As a result of measuring the reverse current and the reverse voltage of each light emitting diode at the wafer level, the light emitting diodes of the embodiments showed lower Ir and higher Vr on average. The forward voltage, the peak wavelength, and the light emission intensity were not greatly different in the light emitting diodes of the examples and comparative examples.
Fig. 6 is a diagram for explaining electrostatic discharge characteristics of the nitride semiconductor device according to an embodiment of the present invention.
In order to measure the electrostatic discharge characteristics, light emitting diode chips were fabricated on a wafer on which no TEV was formed (comparative example), and light emitting diode chips were fabricated on a wafer to which TEV was applied (example). The structures of the light emitting diode chips of the comparative example and the example were the same except whether TEV was applied.
Fig. 6 shows a graph in which initial defects of the light emitting diodes, primary defects after applying a voltage of 8000V to each light emitting diode once, and secondary defects after applying 8000V again are accumulated.
Referring to fig. 6, the cumulative defect rate of the comparative example to which TEV is not applied is about 12.7%, and the cumulative defect rate of the example to which TEV is applied is about 8.7%. That is, by applying TEV, the defect rate can be reduced by 30% or more.
As described above, the present invention has been described in detail with reference to the embodiments of the accompanying drawings, but the above description is illustrative of specific embodiments for the understanding of the present invention, and should not be construed as limiting the present invention to the above embodiments, and the scope of the appended claims should be construed as being limited to the claims and their equivalents.

Claims (13)

1. A nitride semiconductor element, comprising:
a first n-type nitride semiconductor layer having an irregular concave-convex surface; and
a second n-type nitride semiconductor layer disposed over the first n-type nitride semiconductor layer and forming an interface therebetween.
2. The nitride semiconductor element according to claim 1,
the interface has a silicon concentration that is greater than 10 times the silicon concentration in the first n-type nitride semiconductor layer or the second n-type nitride semiconductor layer.
3. The nitride semiconductor element according to claim 1, further comprising:
and a hetero-substrate positioned under the first n-type nitride semiconductor layer.
4. The nitride semiconductor element according to claim 3,
the foreign substrate is a patterned sapphire substrate.
5. The nitride semiconductor element according to claim 3, characterized by further comprising:
a nitride semiconductor layer contacting a lower surface of the first n-type nitride semiconductor layer and forming a lower interface therebetween,
wherein the interface is rougher than the lower interface.
6. The nitride semiconductor element according to claim 5, characterized by further comprising:
a nitride semiconductor layer contacting an upper surface of the second n-type nitride semiconductor layer and forming an upper interface therebetween,
wherein the interface is rougher than the upper interface.
7. The nitride semiconductor element according to claim 1, further comprising:
an active layer disposed on the second n-type nitride semiconductor layer;
a p-type nitride semiconductor layer disposed on the active layer,
the nitride semiconductor element emits light in the ultraviolet or visible light region.
8. The nitride semiconductor element according to claim 1,
the irregular uneven surface of the first n-type nitride semiconductor layer comprises SiH in the absence of a nitrogen source gas4And etching the formed concave-convex surface.
9. The nitride semiconductor element according to claim 8,
the irregular concave-convex surface of the first n-type nitride semiconductor layer includes a surface passing through the SiH4Together with introduction of H2To etch the resulting uneven surface.
10. The nitride semiconductor element according to claim 1,
the second n-type nitride semiconductor layer is thicker than the first n-type nitride semiconductor layer.
11. The nitride semiconductor element according to claim 1,
the interface has a silicon concentration greater than the silicon concentration in the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer.
12. The nitride semiconductor element according to claim 1,
the threading dislocation density in the second n-type nitride semiconductor layer is lower than the threading dislocation density in the first n-type nitride semiconductor layer.
13. The nitride semiconductor element according to claim 1,
the irregular uneven surface of the first n-type nitride semiconductor layer includes thermally etched V-shaped pits.
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