KR20210099884A - Nitride semiconductor device with in-situ etched layer and method of fabricating the same - Google Patents

Abstract

A nitride semiconductor device according to an embodiment includes: a first n-type nitride semiconductor layer having an irregular uneven surface; and a second n-type nitride semiconductor layer disposed on the first n-type nitride semiconductor layer to form an interface with the first n-type nitride semiconductor layer. A silicon concentration at the interface is higher than a silicon concentration in the first and second n-type nitride semiconductor layers. An actual dislocation density in the second n-type nitride semiconductor layer is lower than an actual dislocation density in the first n-type nitride semiconductor layer. An object of the present invention is to provide a nitride semiconductor device having a reduced actual dislocation density using an in-situ etching technique.

Description

A nitride semiconductor device having an in-situ etch layer and a method for manufacturing the same

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode having an in-situ etched layer and a method of manufacturing the same.

The nitride semiconductor is used as a light source of a display device, a traffic light, lighting, or an optical communication device, and may be used in a light emitting diode or a laser diode that emits ultraviolet light, blue, green, or yellow. In addition, it may be used in a heterojunction bipolar transistor (HBT) and a high electron mobility transistor (HEMT).

Since it is not easy to obtain a lattice-matched substrate, the nitride semiconductor is generally grown on a sapphire substrate, a silicon carbide substrate, or a heterogeneous substrate such as a silicon substrate. Accordingly, the nitride semiconductor grown on the substrate as described above has a fairly high threading dislocation density (TDD) of about 1E9/cm 2 or more.

The real potential provides an electron trap site to induce non-luminescent recombination or provide a path for current leakage. Furthermore, when an overvoltage such as static electricity is applied to the semiconductor device, current is concentrated through an actual potential, thereby causing damage due to electrostatic discharge (ESD).

In order to compensate for the poor electrostatic discharge characteristics of the nitride semiconductor device, a Zener diode may be used together with the nitride semiconductor device. However, there is a problem in that the overall product cost and process time increase due to the use of the Zener diode.

Alternatively, a substrate that is lattice-matched with a nitride semiconductor such as a GaN substrate may be used, but the GaN substrate has a problem in that it is difficult to apply except for a specific device such as a laser because the manufacturing cost is quite high.

On the other hand, a technique for reducing the actual dislocation density using epitaxial lateral overgrowth is being used. For example, the actual dislocation density may be reduced by forming a mask pattern for epitaxial lateral growth and growing a gallium nitride semiconductor using the mask pattern.

However, in order to form a mask pattern of a specific structure, the process time increases because the wafer must be removed from the nitride semiconductor layer deposition equipment, the mask layer is deposited and patterned, and then the nitride semiconductor layer is deposited again.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device having a reduced actual dislocation density using an in-situ etching technique, and a method for manufacturing the same.

Another problem to be solved by the present invention is to provide a nitride semiconductor device having improved electrostatic discharge characteristics using an in-situ etching technique, and a method for manufacturing the same.

A nitride semiconductor device according to an embodiment of the present invention includes: a first n-type nitride semiconductor layer having an irregular uneven surface; and a second n-type nitride semiconductor layer disposed on the first n-type nitride semiconductor layer to form an interface with the first n-type nitride semiconductor layer, wherein the silicon concentration at the interface is the first and a silicon concentration in the second n-type nitride semiconductor layer, and an actual dislocation density in the second n-type nitride semiconductor layer is lower than an actual dislocation density in the first n-type nitride semiconductor layer.

In a method for manufacturing a nitride semiconductor device according to another embodiment of the present invention, a first n-type nitride semiconductor is loaded onto the substrate by loading a substrate into a chamber, and introducing a source gas of a group III element and a source gas of nitrogen into the chamber. growth of the layer, blocking the flow of the source gas of the group III element and the source gas of nitrogen, and introducing a SiH ₄ gas into the chamber to etch the surface of the first n-type nitride semiconductor layer, and introducing a source gas of a group element and a source gas of nitrogen to grow a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the etched surface.

According to embodiments of the present invention, _{by etching the surface of the first n-type nitride semiconductor layer using SiH 4} and then growing a second n-type nitride semiconductor layer on the etched first n-type nitride semiconductor layer. 2 It is possible to reduce the actual dislocation density of the n-type nitride semiconductor layer. Accordingly, it is possible to provide a nitride semiconductor device having a reduced actual dislocation density by growing semiconductor layers on the second n-type nitride semiconductor layer.

Furthermore, the first n-type nitride semiconductor layer may be etched using an in-situ etching technique, and thus, a nitride semiconductor device having improved electrostatic discharge characteristics using an in-situ process may be provided.

1 is a schematic cross-sectional view for explaining a nitride semiconductor device according to an embodiment of the present invention.
2 is a schematic diagram for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.
3A, 3B, and 3C are SEM images showing the surface of the first n-type nitride semiconductor layer according to various etching techniques.
4A, 4B, and 4C are CL (chathodluminescence) images for explaining the reduction of real dislocations using the in-situ etching technique.
5 is a CL (chathodluminescence) image showing a cross section of a nitride semiconductor device fabricated by applying an in-situ etching technique.
6 is a graph for explaining electrostatic discharge characteristics of a nitride semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples so that the spirit of the present disclosure can be sufficiently conveyed to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. In addition, when one component is described as being “on” or “on” another component, each component is different from each component, as well as when each component is “immediately above” or “directly on” the other component. It includes the case where another component is interposed between them. Like reference numerals refer to like elements throughout.

A nitride semiconductor device according to an embodiment of the present invention includes: a first n-type nitride semiconductor layer having an irregular uneven surface; and a second n-type nitride semiconductor layer disposed on the first n-type nitride semiconductor layer to form an interface with the first n-type nitride semiconductor layer, wherein the silicon concentration at the interface is the first and a silicon concentration in the second n-type nitride semiconductor layer, and an actual dislocation density in the second n-type nitride semiconductor layer is lower than an actual dislocation density in the first n-type nitride semiconductor layer.

The irregular uneven surface may be formed using an in-situ etching technique, and thus, the first and second n-type nitride semiconductor layers may be formed through an in-situ process.

Meanwhile, the silicon concentration at the interface may exceed 10 times the silicon concentration in the first or second n-type nitride semiconductor layer.

The nitride semiconductor device may further include a heterogeneous substrate positioned under the first n-type nitride semiconductor layer. In an embodiment, the heterogeneous substrate may be a patterned sapphire substrate.

The nitride semiconductor device may further include a nitride semiconductor layer in contact with a lower surface of the first n-type nitride semiconductor layer to form a lower interface between the first n-type nitride semiconductor layer, and the interface is the lower surface. It can be rougher than the interface.

The nitride semiconductor device may further include a nitride semiconductor layer that is in contact with an upper surface of the second n-type nitride semiconductor layer and forms an upper interface between the second n-type nitride semiconductor layer, and the interface is the upper surface. It can be rougher than the interface.

The nitride semiconductor device may include an active layer disposed on the second n-type nitride semiconductor layer; and a p-type nitride semiconductor layer disposed on the active layer, and may emit light in an ultraviolet or visible light region.

The irregular uneven surface of the first n-type nitride semiconductor layer may be etched by _{SiH 4 without a nitrogen source gas.} Furthermore, the irregular uneven surface of the first n-type nitride semiconductor layer may be etched by introducing _{H 2} together with _{SiH 4 .}

In an embodiment, the second n-type nitride semiconductor layer may be thicker than the first n-type nitride semiconductor layer.

In a method for manufacturing a nitride semiconductor device according to another embodiment of the present invention, a first n-type nitride semiconductor is loaded onto the substrate by loading a substrate into a chamber, and introducing a source gas of a group III element and a source gas of nitrogen into the chamber. growth of the layer, blocking the flow of the source gas of the group III element and the source gas of nitrogen, and introducing a SiH ₄ gas into the chamber to etch the surface of the first n-type nitride semiconductor layer, and introducing a source gas of a group element and a source gas of nitrogen to grow a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the etched surface.

By blocking the inflow of the nitrogen source gas _{and using the SiH 4} gas, a large number of thermally etched V-pits (TEVs) may be formed on the surface of the first n-type nitride semiconductor layer. It is possible to reduce the actual potential of the second n-type nitride semiconductor layer by using it.

In particular, it is possible to suppress the generation of silicon nitride islands having non-uniform sizes by blocking the inflow of the nitrogen source gas.

Furthermore, while the SiH ₄ gas is introduced to etch the surface of the first n-type nitride semiconductor layer, the N ₂ gas and the nitrogen source gas from flowing into the chamber may be blocked.

In an embodiment, the first and second n-type nitride semiconductor layers may be n-type GaN.

The method for manufacturing a nitride semiconductor device may further include growing an active layer and a p-type nitride semiconductor layer on the second n-type nitride semiconductor layer.

Meanwhile, the substrate may be a patterned sapphire substrate.

As the surface of the first n-type nitride semiconductor layer is etched, the roughness of the surface of the first n-type nitride semiconductor layer is increased.

_{In an embodiment, while the SiH 4} gas is introduced into the chamber, the _{H 2} gas may also be introduced.

In some embodiments, the second n-type nitride semiconductor layer has a lower actual dislocation density than the first n-type nitride semiconductor layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a cross-sectional view for explaining a nitride semiconductor device according to an embodiment of the present invention.

1, the nitride semiconductor device includes a substrate 21, a lower nitride semiconductor layer 23, a high-temperature buffer layer 25, an intermediate layer 27, a first n-type semiconductor layer 29a, and an n-th semiconductor layer ( 29b), an active layer 31 and a p-type nitride semiconductor layer 39 may be included.

The substrate 21 is for growing a gallium nitride-based semiconductor layer, and a heterogeneous substrate such as a sapphire substrate, a SiC substrate, a Si substrate, or a spinel substrate may be used. In particular, the substrate 21 may be a patterned sapphire substrate.

The lower nitride semiconductor layer 23 fills the region between the protrusions on the substrate 21 . The lower nitride semiconductor layer 23 may cover the protrusions on the substrate 21 . The lower nitride semiconductor layer 23 may be formed as a single layer or multiple layers. In particular, the lower nitride semiconductor layer 23 may include a low-temperature buffer layer. The low-temperature buffer layer may be formed of (Al, Ga)N on the substrate 21 at a low temperature of 400° C. to 600° C. For example, it may be formed of GaN or AlN. The low-temperature buffer layer may be formed, for example, to a thickness of about 25 nm. The lower nitride semiconductor layer 23 may be formed of, for example, an undoped layer.

The high-temperature buffer layer 25 may be grown at a relatively higher temperature than the lower nitride semiconductor layer 23 in order to mitigate the occurrence of defects such as dislocations between the substrate 21 and the n-type nitride semiconductor layer 25 . The high temperature buffer layer 25 may be formed of undoped GaN or GaN doped with n-type impurities. However, actual dislocations formed in the lower nitride semiconductor layer 23 may be transferred to the high temperature buffer layer 25 .

The intermediate layer 27 may contain Al. For example, the intermediate layer 27 may be formed of AlGaN, AlInGaN, or AlInN. The intermediate layer 27 may help lateral dispersion of electrons.

Meanwhile, the first n-type nitride semiconductor layer 29a may be formed of a nitride-based semiconductor layer doped with n-type impurities, for example, a nitride semiconductor layer doped with Si. The Si doping concentration doped into the first n-type nitride semiconductor layer 29a may be in the range of 5E18/cm 2 to 5E19/cm 2 .

The first n-type nitride semiconductor layer 29a is formed at 1000°C to 1200°C (eg, 1050°C to 1100°C) by supplying a source gas of a group III element and a source gas of nitrogen into the chamber using MOCVD technology, for example. It may be grown under a growth pressure of about 150 Torr to 200 Torr. Actual dislocations formed in the high-temperature buffer layer 25 may be transferred to the first n-type nitride semiconductor layer 29a.

Meanwhile, the first n-type nitride semiconductor layer 29a may have an irregular uneven surface. The irregular uneven surface may be formed by surface etching by introducing _{SiH 4 gas into the chamber.} At this time, in order to maintain the temperature in the chamber, H ₂ gas may be introduced together. The end portions of the actual dislocations exposed on the surface of the first n-type nitride semiconductor layer 29a may be etched relatively quickly by surface etching to form V-pits. These V-pits may be referred to as thermally etched V-pits (TEVs). Accordingly, recesses may be generally formed at the distal end of these actual dislocations. The irregular uneven peak-valley distance is smaller than the thickness of the first n-type nitride semiconductor layer 29a.

The second n-type nitride semiconductor layer 29b is grown on the first n-type nitride semiconductor layer 29a. The second n-type nitride semiconductor layer 29b may be a nitride-based semiconductor layer doped with n-type impurities, for example, a nitride semiconductor layer doped with Si. The Si doping concentration doped into the second n-type nitride semiconductor layer 29b may be in the range of 5E18/cm 2 to 5E19/cm 2 . In an embodiment, the Si doping concentration in the second n-type nitride semiconductor layer 29b may be substantially the same as the Si doping concentration in the first n-type nitride semiconductor layer 29a. The second n-type nitride semiconductor layer 29b may be grown in the same chamber under the same or similar conditions as those of the first n-type nitride semiconductor layer 29a.

The second n-type nitride semiconductor layer 29b forms an interface 30 with the first n-type nitride semiconductor layer 29a. Since the first n-type nitride semiconductor layer 29a has an irregular uneven surface, the interface between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b is relatively higher than other interfaces. has a rough shape. For example, the interface 30 has a rougher shape than any underlying interface between the first n-type nitride semiconductor layer 29a and the high temperature buffer layer 25 . Also, the interface 30 has a rougher shape than any upper interface formed between the second n-type nitride semiconductor layer 29b and the p-type nitride semiconductor layer 33 .

Meanwhile, the silicon concentration at the interface 30 is higher than the silicon concentration in the first and second n-type nitride semiconductor layers 29a and 29b. For example, the silicon concentration in the interface 30 may exceed 10 times the silicon concentration in the first or second n-type nitride semiconductor layers 29a and 29b. The Si accumulated in the interface 30 may prevent an actual potential from being transferred to the second n-type nitride semiconductor layer 29b.

The actual dislocation in the first n-type nitride semiconductor layer 29a may be blocked at the interface 30 or may be dissipated by bending in the lateral direction near the interface, and thus, the actual dislocation density in the second n-type nitride semiconductor layer 29b is lower than the actual dislocation density in the first n-type nitride semiconductor layer 29a.

The second n-type nitride semiconductor layer 29b may be thicker than the first n-type nitride semiconductor layer 29a, and thus, the V-pits formed on the surface of the first n-type nitride semiconductor layer 29a are the first n-type nitride semiconductor layer 29a. All of them may be covered by the nitride semiconductor layer 29b. Furthermore, a top surface of the second n-type nitride semiconductor layer 29b may be flatter than a surface of the first n-type nitride semiconductor layer 29a.

The active layer 31 is disposed on the second n-type nitride semiconductor layer 29b. Another nitride semiconductor layer, for example, a superlattice layer, may be added between the active layer 31 and the second n-type nitride semiconductor layer 29b.

The active layer 31 may be formed of a nitride semiconductor layer emitting light in the ultraviolet or visible region. The active layer 31 may have a single quantum well structure or a multiple quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately stacked. The quantum barrier layer may be formed of a nitride semiconductor layer such as GaN, InGaN, AlGaN, or AlInGaN, which has a wider bandgap than the quantum well layer.

The quantum well layer is formed of a nitride semiconductor layer having a relatively narrower bandgap than the quantum barrier layer, and may be formed of, for example, a gallium nitride-based semiconductor layer such as InGaN. Light of a desired wavelength may be realized through the composition ratio of the quantum well layer.

The p-type nitride semiconductor layer 33 may be formed of a semiconductor layer doped with a p-type impurity such as Mg. The p-type nitride semiconductor layer 33 may be a single layer or a multi-layer, and may include a p-type cladding layer and a p-type contact layer. In addition, a transparent electrode such as ITO or a reflective metal such as Al may be positioned on the p-type nitride semiconductor layer 33 . Also, although not shown, an electron blocking layer may be interposed between the active layer 31 and the p-type nitride semiconductor layer 33 .

In this embodiment, a light emitting diode including the active layer 31 is described as an example of the nitride semiconductor device, but the present invention is not limited thereto. For example, the nitride semiconductor device of the present invention includes a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (HEMT) including a first n-type nitride semiconductor layer 29a and a second n-type nitride semiconductor layer 29b. ) is included.

2 is a schematic diagram for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention. Here, growth of the first n-type nitride semiconductor layer 29a, generation of TEV through surface etching, and growth of the second n-type nitride semiconductor layer 29b will be mainly described.

1 and 2 , first, a substrate 21 is loaded into a chamber. The chamber provides an environment in which the nitride semiconductor layer can be grown using the MOCVD technique.

A lower nitride semiconductor layer 23 , a high temperature buffer layer 25 , and an intermediate layer 27 may be sequentially grown on the substrate 21 . These layers can be grown in-situ using conventional techniques.

Next, the first n-type nitride semiconductor layer 29a is grown. The first n-type nitride semiconductor layer 29a may be grown at a first temperature T1 for a predetermined time. The first temperature may be, for example, about 1100°C. The first n-type nitride semiconductor layer 29a may be grown by introducing a source gas of a _{group III element such as TMG and a source gas of nitrogen such as NH 3 into the chamber.} In this case, N ₂ and H ₂ may be introduced together as an atmosphere gas or a carrier gas. Also, _{a source gas of Si such as SiH 4} may be introduced into the chamber for doping of Si.

When the growth of the first n-type nitride semiconductor layer 29a is completed, the inflow of the group III element source gas and nitrogen source gas is blocked. The inflow of a gas containing nitrogen, such as N ₂ gas, may also be blocked. H ₂ gas may be continuously introduced into the chamber, and the gas in the chamber is exhausted to the outside by the vacuum pump. Meanwhile, the SiH ₄ gas may be vented through a bypass before being introduced into the chamber.

After a predetermined time, for example, about 10 seconds, the nitrogen source gas and the group III element source _{gas in the chamber are sufficiently exhausted, the SiH 4} gas is introduced into the chamber. The H ₂ gas may be introduced into the chamber together with the _{SiH 4 gas.} As the SiH ₄ gas is introduced, the surface of the first n-type nitride semiconductor layer 29a is etched to form TEVs. The surface of the first n-type nitride semiconductor layer 29a is etched using an in-situ etching technique, so that vacuum breaking of the chamber does not occur. After etching is performed for a predetermined time, for example, about 5 minutes, a source gas of a group III element such as TMG and a source gas of _{nitrogen such as NH 3} are again introduced into the chamber to form the second n-type nitride semiconductor layer 29b. is grown

A high concentration of Si may be accumulated on the surface of the first n-type nitride semiconductor layer 29a at the beginning of surface etching by the _{SiH 4 gas or growth of the second n-type nitride semiconductor layer 29b.}

Meanwhile, the actual potentials of the first n-type nitride semiconductor layer 29a may be blocked by Si or the like while the second n-type nitride semiconductor layer 29b is growing, or may be dissipated by changing a path in the lateral direction.

Subsequently, the active layer 31 and the p-type nitride semiconductor layer 33 may be grown on the second n-type nitride semiconductor layer 29b, and then, the substrate 21 is taken out of the chamber, and various processing processes are performed. A nitride semiconductor device may be manufactured through the

According to the present embodiment, the density of real dislocations in the nitride semiconductor layer using an in-situ technique in which the process time of only a few minutes is increased by etching the surface of the first n-type nitride semiconductor layer 29a using _{SiH 4 .} can be significantly reduced.

In this embodiment, the first n-type nitride semiconductor layer 29a growth step, the venting step, the surface etching step, and the second n-type nitride semiconductor layer 29a growth step may all be performed at the same temperature. However, the present invention is not necessarily limited thereto, and the temperature may be adjusted in each step.

3A, 3B, and 3C are SEM images showing the surface of the first n-type nitride semiconductor layer according to various etching techniques. Here, FIG. 3a shows the surface of the first n-type nitride semiconductor layer 29a etched by introducing only _{H 2} without introducing _{SiH 4 in the surface etching step, and FIG. 3b is SiH 4} and NH ₃ together with _{H 2} The surface of the first n-type nitride semiconductor layer 29a is shown after introduction, and FIG. 3C shows the surface of the first n-type nitride semiconductor layer 29a etched by introducing only _{H 2} and SiH _{4 .}

Referring to FIG. 3A , it can be observed that the surface of the first n-type nitride semiconductor layer 29a is etched by _{H 2 , but V pits are not formed.}

Referring to FIG. 3B , when SiH ₄ and NH ₃ were introduced together, silicon nitride islands were formed through their reaction. The islands have an irregular size and are irregularly arranged. The islands are expected to cover the ends of the actual dislocation. However, due to the islands, an actual potential can be formed again in the second n-type nitride semiconductor layer 29b grown thereon. In addition, as SiH ₄ and NH ₃ are introduced together, islands are formed and the first n-type nitride semiconductor layer 29a is etched. Accordingly, the second n-type nitride semiconductor layer 29b covering the islands needs to be grown to be relatively thick, for example, twice as thick as that of the first n-type nitride semiconductor layer 29a in order to planarize the top surface. Accordingly, the processing time is increased. Furthermore, the islands formed of silicon nitride may remain between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b to decrease the extraction efficiency of light generated in the active layer.

Referring to FIG. 3C , when _{H 2} and SiH ₄ were introduced without introducing _{NH 3} , small V pits were formed in large quantities. It is understood that the V pits are generated by etching the gallium nitride layer by _{SiH 4 .} At this time, V pits will be better formed at the ends of actual dislocations.

As a result of measuring the surface roughness using an atomic force microscope (AFM), the surface roughness of the first n-type nitride semiconductor layer 29a of FIG. 3c shows a value of Ra of about 1.78 nm in a region of 2 μm×2 μm, Rq showed a value of about 2.27 nm. In contrast, when the surface etching was not performed, the first n-type nitride semiconductor layer 29a exhibited values of Ra of about 0.176 nm and Rq of about 0.140 in an area of the same size. Accordingly, it can be seen that the surface of the first n-type nitride semiconductor layer 29a is etched by _{SiH 4 .}

4A, 4A, and 4C are CL (chathodluminescence) images for explaining the reduction of real dislocations using the in-situ etching technique. Here, each of the CL images represents the surface of the second n-type nitride semiconductor layer 29b.

The second n-type nitride semiconductor layer of FIG. 4A was grown on the first n-type nitride semiconductor layer 29a without surface etching of the first n-type nitride semiconductor layer. The second n-type nitride semiconductor layer of FIG. 4B was grown thereon after forming silicon nitride islands on the first n-type nitride semiconductor layer 29a using SiH4 and NH3 as shown in FIG. 3B. The second n-type nitride semiconductor layer of FIG. 4C was grown on the first n-type nitride semiconductor layer 29a after etching the first n-type nitride semiconductor layer 29a using SiH4 as shown in FIG. 3C .

4A, 4B and 4C, the embodiment of FIG. 4C in which the first n-type nitride semiconductor layer 29a was etched using _{SiH 4} without using _{NH 3 had the smallest number and size of actual dislocations.} . In the sample of FIG. 4A that was not subjected to surface etching, a large number of aggregated dislocations were present in the sample of FIG. 4A , and a large number of aggregated actual dislocations were observed in the sample of FIG. 4B , which formed islands of silicon nitride. In contrast, in the embodiment of FIG. 4C, the magnitude of the actual dislocation was observed to be quite small.

5 is a CL (chathodluminescence) image showing a cross section of a nitride semiconductor device fabricated by applying an in-situ etching technique.

Referring to FIG. 5 , the interface 30 between the first n-type nitride semiconductor layer 29a and the second n-type nitride semiconductor layer 29b can be clearly identified. The interface 30 is rougher than the interface between the first n-type nitride semiconductor layer 29a and the high temperature buffer layer 25 . In addition, it can be seen that the height of the interface 30 is smaller than the thickness of the first n-type nitride semiconductor layer 29a.

On the other hand, in order to compare the electrical characteristics of the nitride semiconductor device according to whether or not TEV is applied, the light emitting diode of the embodiment to which TEV is applied and the light emitting diode of the comparative example to which TEV is not applied were manufactured and reverse current (Ir) and reverse voltage (Vr) were measured. did. As a result of measuring the reverse current and the reverse voltage of each light emitting diode at the wafer level, the light emitting diodes of the example exhibited low Ir and high Vr on average. Forward voltage, peak wavelength, and emission intensity were not significantly different between the light emitting diodes of Examples and Comparative Examples.

Meanwhile, FIG. 6 is a graph for explaining the electrostatic discharge characteristics of a nitride semiconductor device according to an embodiment of the present invention.

To measure the electrostatic discharge characteristics, light emitting diode chips (Comparative Example) were fabricated on a wafer on which TEV was not formed, and light emitting diode chips (Example) were fabricated on a wafer to which TEV was applied. The structures of the light emitting diode chips of Comparative Examples and Examples are all the same except for whether or not TEV is applied.

The initial failure of these light emitting diodes, the primary failure after applying a voltage of 8000 V to each of the light emitting diodes once, and the secondary failure after applying 8000 V again are accumulated and shown in the graph of FIG. 6 .

Referring to FIG. 6 , the cumulative defective rate of the comparative example to which TEV was not applied was about 12.7%, but the cumulative defective rate of the example to which TEV was applied was about 8.7%. That is, it was possible to reduce the defective rate by 30% or more by applying TEV.

As described above, the detailed description of the present invention has been made by the embodiments with reference to the accompanying drawings, but the above description has been described by taking specific embodiments as an example for the understanding of the present invention, and the present invention is based on the embodiments It should not be construed as being limited, and the scope of the present invention should be understood as the following claims and their equivalents.

Claims (18)

a first n-type nitride semiconductor layer having an irregular uneven surface; and
a second n-type nitride semiconductor layer disposed on the first n-type nitride semiconductor layer to form an interface between the first n-type nitride semiconductor layer;
The silicon concentration at the interface is higher than the silicon concentration in the first and second n-type nitride semiconductor layers,
An actual dislocation density in the second n-type nitride semiconductor layer is lower than an actual dislocation density in the first n-type nitride semiconductor layer. The method according to claim 1,
The silicon concentration at the interface exceeds 10 times the silicon concentration in the first or second n-type nitride semiconductor layer. The method according to claim 1,
The nitride semiconductor device further comprising a heterogeneous substrate positioned below the first n-type nitride semiconductor layer. 4. The method according to claim 3,
The heterogeneous substrate is a nitride semiconductor device that is a patterned sapphire substrate. 4. The method according to claim 3,
Further comprising a nitride semiconductor layer in contact with the lower surface of the first n-type nitride semiconductor layer to form a lower interface between the first n-type nitride semiconductor layer,
The interface is coarser than the lower interface. 6. The method of claim 5,
Further comprising a nitride semiconductor layer in contact with the upper surface of the second n-type nitride semiconductor layer to form an upper interface between the second n-type nitride semiconductor layer,
The interface is coarser than the upper interface. The method according to claim 1,
an active layer disposed on the second n-type nitride semiconductor layer; and
Further comprising a p-type nitride semiconductor layer disposed on the active layer,
A nitride semiconductor device emitting light in the ultraviolet or visible region. The method according to claim 1,
A nitride semiconductor device formed by etching the irregular uneven surface of the first n-type nitride semiconductor layer _{by SiH 4 without a source gas of nitrogen.} 9. The method of claim 8,
The irregular uneven surface of the first n-type nitride semiconductor layer is formed by etching _{H 2} together with _{SiH 4 .} The method according to claim 1,
The second n-type nitride semiconductor layer is thicker than the first n-type nitride semiconductor layer. loading the substrate into the chamber;
Growing a first n-type nitride semiconductor layer on the substrate by introducing a source gas of a group III element and a source gas of nitrogen into the chamber;
Blocking the inflow of the source gas of the group III element and the source gas of nitrogen,
Etching the surface of the first n-type nitride semiconductor layer by introducing a _{SiH 4} gas into the chamber,
and growing a second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer having the etched surface by introducing a source gas of a group III element and a source gas of nitrogen into the chamber. . 12. The method of claim 11,
While the surface of the first n-type nitride semiconductor layer is etched by introducing the SiH4 gas, inflow of the source gas of N2 gas and nitrogen into the chamber is blocked. 12. The method of claim 11,
The first and second n-type nitride semiconductor layers are n-type GaN nitride semiconductor device manufacturing method. 12. The method of claim 11,
and growing an active layer and a p-type nitride semiconductor layer on the second n-type nitride semiconductor layer. 12. The method of claim 11,
The method for manufacturing a nitride semiconductor device, wherein the substrate is a patterned sapphire substrate. 12. The method of claim 11,
As the surface of the first n-type nitride semiconductor layer is etched, the roughness of the surface of the first n-type nitride semiconductor layer is increased. 12. The method of claim 11,
A method of manufacturing a nitride semiconductor device in which _{H 2 gas is also introduced while the SiH 4} gas is introduced into the chamber. 12. The method of claim 11,
The second n-type nitride semiconductor layer may have a lower actual dislocation density than the first n-type nitride semiconductor layer.

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