US20110163295A1 - Semiconductor with low dislocation - Google Patents

Semiconductor with low dislocation Download PDF

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US20110163295A1
US20110163295A1 US13/048,905 US201113048905A US2011163295A1 US 20110163295 A1 US20110163295 A1 US 20110163295A1 US 201113048905 A US201113048905 A US 201113048905A US 2011163295 A1 US2011163295 A1 US 2011163295A1
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layer
semiconductor
semiconductor layer
oxide
epitaxial
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Peng Yi Wu
Shih Cheng Huang
Po Min Tu
Ying Chao Yeh
Wen Yu Lin
Shih Hsiung Chan
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Advanced Optoelectronic Technology Inc
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Advanced Optoelectronic Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Definitions

  • the present invention relates to semiconductor with low dislocation, and a light emitting diode with the semiconductor.
  • LED light emitting diodes
  • laser diodes laser diodes
  • semiconductor RF radio frequency
  • the light emitting diode, the laser diode, or the semiconductor RF device includes a semiconductor device such as an RF device and a light emitting device with a p-n junction formed on the epitaxial substrate.
  • the structure of a blue or red light emitting diode comprises a sapphire substrate, a buffer layer formed on the sapphire substrate, an N-type GaN semiconductor layer, an active layer partly covering the N-type GaN semiconductor layer, a P-type GaN semiconductor layer formed on the active layer, and two contact electrodes respectively formed on the aforesaid two semiconductor layers.
  • the luminous efficiency of LEDs is affected by some factors such as internal quantum efficiency and external quantum efficiency.
  • the major factor affecting the internal quantum efficiency is the amount of dislocation existing in the active layer.
  • lattice mismatch always occurs in the materials of a sapphire substrate and a GaN layer. Therefore, the threading dislocation also occurs during the epitaxial process.
  • FIG. 1A is a schematic diagram of a prior art disclosed by Taiwanese patent publication No. TW561632.
  • the device comprises a sapphire substrate 10 , an N-type semiconductor layer 11 formed on the sapphire substrate 10 , an active layer 12 capable of generating light with default wavelengths formed on the N-type semiconductor layer 11 , and a P-type semiconductor layer 13 formed on the active layer 12 .
  • a plurality of recesses 14 are periodically arranged and formed on the sapphire substrate 10 using photolithography equipment and a reactive ion etching process. Therefore, the N-type semiconductor layer 11 on the sapphire substrate 10 without crystal defects is filled in each of the recesses 14 .
  • the depth and width of each of the recesses 14 are respectively 1 ⁇ m and 10 ⁇ m.
  • the pitch, defined as the distance between the centers of two adjacent recesses, is 10 ⁇ m.
  • Shulij Nakamura, Masayuki Senoh, Shinichi Nagahama, Naruhito Iwasa, Takao Tamada, et al., researchers of Nichia Chemical Co. propose a laser diode of modulation-doped strained-layer superlattices formed on an epitaxial lateral overgrowth GaN substrate in Appl. Phys. Lett. 72(2), 211-213.
  • a buffer layer 91 and a GaN layer with a thickness of 2 ⁇ m are sequentially formed on a sapphire substrate 90 .
  • a silica layer 93 with a thickness of 0.1 ⁇ m is further formed on the GaN layer 92 , and the silica layer 93 has stripe-shaped windows 94 with a width of 4 ⁇ m by a photolithography process.
  • the windows 94 of the silica layer 93 act as a mask (silica mask) on the GaN layer 92 .
  • an N-type GaN layer 95 is sequentially formed on the mask by a two jet-flow MOCVD method so that a sequential device can be formed thereon.
  • Nichia utilize an amorphous mask to direct epitaxial vertical overgrowth layers in the windows 94 to be laterally merged with each other so as to form epitaxial lateral overgrowth layers on the mask. Accordingly, the dislocation density of the epitaxial layer is reduced.
  • Finding a means to reduce the dislocation density of an epitaxial layer during an epitaxial process and improving the luminous characteristics of the epitaxial layer are still critical issues for the manufacturers currently investing significant resources on research in the epitaxial field.
  • FIGS. 1A and 1B are schematic structure diagrams of a prior art
  • FIG. 2 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor layer in accordance with the present invention
  • FIG. 3 is an SEM picture showing recesses on the semiconductor in accordance with the present invention.
  • FIG. 4 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor in accordance with another embodiment of the present invention.
  • the present invention is related to a semiconductor and a method for blocking the dislocation propagation of the semiconductor.
  • the descriptions below illustrate detailed steps and the compositions thereof.
  • the embodiment of the present invention is not limited to the particular method or the system familiar to those skilled in the art of blocking the dislocation propagation of a semiconductor.
  • the ordinary skills in the art are not illustrated to avoid unnecessary limitations on the present invention.
  • the preferred embodiments are illustrated below but the present invention may be utilized in other practices and should not be limited by such illustrated embodiments.
  • the scope of the present invention should be interpreted in light of the claims.
  • U.S. Pat. No. 6,861,270 interposes a silicon nitride layer between N-type and P-type group III nitride semiconductor layers by depositing so as to enable the spatial fluctuation of band-gap in an active layer.
  • the defective density of the internal material cannot be reduced.
  • U.S. Pat. No. 6,462,357 forms island crystals by using group II nitride material ([Be, Mg, Ca, Sr, Ba, Zn, Cd, Hg]N) on a substrate or a group III nitride semiconductor layer. Because the adjustable parameters for epitaxial growth are limited, the optimal result is not easily obtained.
  • group II nitride material [Be, Mg, Ca, Sr, Ba, Zn, Cd, Hg]N
  • U.S. Pat. No. 6,627,974 utilizes an additional CVD process to form a protective film (SiO x , Si x N y , TiO x , or ZrO x ) which is regularly arranged. However, the dislocation defects cannot be completely blocked.
  • U.S. Pat. No. 6,345,063 utilizes silica or silicon nitride as a patterned mask layer having a regular layout. However, the dislocation defects cannot be completely blocked. In this patent, InGaN is directly grown on the patterned mask layer. Therefore, an epitaxial layer of high quality is not easily formed thereon.
  • TW patent No. 1242898 puts forth a method blocking the propagation of line dislocation occurring only in hexagon vias.
  • a TEM (Transmission Electron Microscopy) picture cannot show any redirection effects on the dislocation because of lateral growth.
  • the present invention provides a method for blocking the dislocation propagation of a semiconductor.
  • an epitaxial blocking layer with orientation is used to block the extension, in contrast to the epitaxial blocking layers without orientation as seen in the prior arts.
  • the line dislocation is likely to be blocked because of lateral growth mechanism.
  • a semiconductor layer is formed by epitaxial process on a substrate. Recesses are formed on the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. The aforesaid plurality of recesses can be formed by etching the semiconductor layer. When the semiconductor layer is etched, the fragile locations of the semiconductor layer resulted from the dislocation defects are etched to be recesses by etchant.
  • a blocking layer is formed on each of the recesses.
  • the steps of forming the blocking layer on a plurality of recesses comprise: depositing a blocking layer on the semiconductor layer; coating photoresist on the blocking layer to fill in the plurality of recesses; removing the photoresist outside the plurality of recesses; removing the blocking layer outside the plurality of recesses by etching and leaving the blocking layer existing in the plurality of recesses; and removing the photoresist remaining on the plural areas of the blocking layer to expose the blocking layer existing in the recesses.
  • the same semiconductor layer undergoes epitaxial process again on the aforesaid semiconductor layer, and laterally grows to redirect the dislocation defects.
  • the present invention further provides a method for blocking the dislocation propagation of a semiconductor.
  • the aforesaid steps are performed at least one time.
  • a compound semiconductor multilayer is formed by epitaxial process on the latter semiconductor layer to form an LED.
  • the compound semiconductor multilayer comprises an N-type semiconductor conductive layer, a P-type semiconductor conductive layer, and an active layer, wherein the active layer is between the N-type semiconductor conductive layer and the P-type semiconductor conductive layer.
  • the material of the aforesaid substrate is sapphire (Al 2 O 3 ), silicon carbide (SiC), AlLiO 2 , LiGaO 2 , silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), zinc selenide (ZnSe), or other metal.
  • the present invention further comprises a buffer layer interposed between the aforesaid substrate and the compound semiconductor multilayer.
  • the present invention also comprises a P-type semiconductor electron barrier layer interposed between the active layer and the P-type semiconductor conductive layer.
  • FIG. 2 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor layer.
  • a substrate 100 is provided.
  • a semiconductor layer 102 is formed on the substrate 100 .
  • the material of the substrate 100 is sapphire (Al 2 O 3 ), silicon carbide (SiC), AlLiO 2 , LiGaO 2 , silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), or zinc selenide (ZnSe).
  • II-VI semiconductor compound is commonly and preferably formed on a zinc selenide substrate or a zinc oxide substrate as an epitaxial base.
  • Group III arsenide or Group III phosphide is commonly formed on a gallium arsenide substrate, a gallium phosphide substrate, an indium phosphide substrate, or an indium arsenide substrate.
  • Group III nitride is commonly formed on a sapphire substrate, or a silicon carbide substrate, and an AlLiO 2 substrate, a LiGaO 2 substrate, a silicon substrate, or an aluminum zinc oxide substrate is also used in an experimental stage.
  • the structure and coefficient of crystal lattice are another consideration for selecting the epitaxial substrate.
  • a buffer layer needs to be first formed on the lower layer to obtain a good quality upper epitaxial layer.
  • the epitaxial material is Group III nitride, particularly gallium nitride
  • the common epitaxial substrate is a sapphire substrate or a silicon carbide substrate which is used in the current LED market.
  • the epitaxial material is not limited to the Group III nitride or even the gallium nitride. Any III-VI semiconductor compound or II-V semiconductor compound can be applied to the present invention.
  • a buffer layer 101 is formed on the substrate prior to the formation of Group III nitride because the mismatch of the crystal lattice between the sapphire substrate and gallium nitride is as high as 14%.
  • the mismatch of the crystal lattice between the silicon carbide substrate and gallium nitride is also as high as 3.5%.
  • the material of the buffer layer 101 can be gallium nitride, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a superlattice structure of InGaN/InGaN. As to the superlattice structure of InGaN/InGaN, TW Patent Application No.
  • the buffer layer 101 is deposited in epitaxial equipment such as MOCVD (metal organic chemical vapor deposition) equipment or MBE (molecular beam epitaxy) equipment under a temperature lower than the temperatures of forming sequential epitaxial layers.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the precursor of nitrogen can be NH3 or N2
  • the precursor of gallium can be trimethylgallium or Triethylgallium
  • the precursor of aluminum can be trimethylaluminum or Triethylaluminum
  • the reaction chamber can be set to low pressure or normal pressure.
  • a plurality of recesses 110 is formed by etching the fragile locations of the semiconductor layer 102 where dislocation occurs.
  • a blocking layer 103 is formed on the semiconductor layer 102 , as shown in Step 3 .
  • a photoresist is coated on the blocking layer 103 to form a photoresist layer 109 filling in the plurality of recesses 110 , as shown in Step 4 .
  • Step 5 the photoresist layer 109 outside the plurality of recesses 110 is removed and the photoresist layer 109 inside the plurality of recesses 110 is left in place.
  • Step 6 the blocking layer 103 outside the plurality of recesses 110 is removed and the blocking layer 103 existing in the plurality of recesses 110 is also left in place.
  • the photoresist layer 109 remaining in the plurality of recesses 110 is removed by a photolithography process, as shown in Step 7 .
  • the material of the blocking layer 103 can be dielectric comprising magnesium nitride (Mg x N y ), silicon nitride (Si x N y ), silicon oxide (Si x O y ), titanium oxide (TWO, zirconium oxide (Zr x O y ), hafnium oxide (Hf x O y ), tantalum oxide (Ta x O y ), silicon nitride (SiN), and silicon oxide (SiO).
  • magnesium nitride Mg x N y
  • silicon nitride Si x N y
  • silicon oxide Si x O y
  • titanium oxide TWO, zirconium oxide (Zr x O y ), hafnium oxide (Hf x O y ), tantalum oxide (Ta x O y ), silicon nitride (SiN), and silicon oxide (SiO).
  • a re-epitaxial semiconductor layer 104 is formed by epitaxial process on the semiconductor layer 102 .
  • the aforesaid blocking layer 103 can block the growth of the semiconductor layer 104 , and hence, the semiconductor layer 104 laterally overgrows toward the plurality of recesses 110 . Accordingly, the dislocation is redirected so the defects of the dislocation are stopped in the re-epitaxial semiconductor layer 104 , as shown in Steps 9 , 10 , and 11 .
  • FIG. 3 is an SEM (scanning electron microscope) picture showing recesses on the semiconductor layer in accordance with the present invention.
  • the present invention applies the aforesaid method for blocking the dislocation propagation of a semiconductor to the LED fabrication so as to have a method for restraining dislocation defects inside LEDs.
  • this method performs at least one cycle of the aforesaid method for blocking the dislocation propagation of a semiconductor, and a re-epitaxial semiconductor layer 404 .
  • a compound semiconductor multilayer 420 is formed on the re-epitaxial semiconductor layer 404 to obtain an LED. Therefore, the density of dislocation defects inside the LED can be dramatically reduced by implementing the aforesaid method.
  • the defects of the material are effectively restrained to improve the lighting characteristics and the electrical characteristics of light emitting devices.
  • Step 20 a buffer layer 401 is formed on a substrate 400 , and a semiconductor layer 402 is formed on the buffer layer 401 .
  • Step 21 a plurality of recesses 410 is formed on the semiconductor layer 402 by etching the semiconductor layer 402 where dislocation occurs.
  • Step 22 a blocking layer 403 is formed on the semiconductor layer 402 .
  • photoresist is coated on the blocking layer 403 as a photoresist layer 409 to fill in the plurality of recesses 410 .
  • Step 24 the photoresist layer 409 outside the plurality of recesses 410 is removed.
  • Step 25 the photoresist layer 409 outside the plurality of recesses 410 is etched, and the photoresist layer 409 is left as a plurality of areas in the recesses 410 .
  • Step 26 the remaining photoresist layer 409 is removed by a photolithography process.
  • Step 27 the same semiconductor layer 402 undergoes epitaxial process again on the aforesaid semiconductor layer 402 , and laterally grows to form as a re-epitaxial semiconductor layer 404 for redirecting the dislocation defects.
  • Step 27 the dislocation defects cannot be completely restrained in the re-epitaxial semiconductor layer 404 . Therefore, the aforesaid steps are performed again to further block the other dislocation, whereby the density of dislocation defects inside the device can be dramatically reduced.
  • a compound semiconductor multilayer 420 is formed by epitaxial process on the re-epitaxial semiconductor layer 404 to form an LED.
  • the compound semiconductor multilayer 420 comprises an N-type semiconductor conductive layer 405 , an active layer 406 , and a P-type semiconductor conductive layer 408 .
  • the aforesaid LED further comprises a P-type semiconductor electron barrier 407 between the active layer 406 and the P-type semiconductor conductive layer 408 so as to improve the light extraction efficiency of the LED.
  • the N-type semiconductor conductive layer 405 , the active layer 406 , the P-type semiconductor electron barrier layer 407 , and the P-type semiconductor conductive layer 408 can all be group III nitride.
  • the N-type semiconductor conductive layer 405 can be a layer of gallium nitride or aluminum gallium nitride acting as a cladding layer of the N-type conduction of the LED.
  • the N-type conduction of gallium nitride or aluminum gallium nitride is formed in MOCVD equipment or MBE equipment.
  • group IV atoms are simultaneously doped.
  • the group IV atoms are silicon atoms.
  • the precursor of silicon is silane or disilane suitable for the MOCVD equipment.
  • a gallium nitride layer (not shown) without dopant and a contact layer (not shown) of the N-type conduction can be previously and sequentially formed on the buffer layer, and the formation steps of the two layers are optional for this embodiment.
  • the gallium nitride layer without dopant can improve the epitaxial quality of the cladding layer of the N-type conduction.
  • the material of the contact layer of the N-type conduction can be highly-doped gallium nitride or highly-doped aluminum gallium nitride to have a superior conductive effect with the N-type electrodes.
  • the aforesaid active layer 406 can be a single heterostructure structure, a double heterostructure structure, a single quantum well structure, or a structure of multi quantum well layers/barrier layers.
  • the material of the quantum well layer can be indium gallium nitride
  • the material of the barrier can be a ternary component structure such as aluminum gallium nitride.
  • a quaternary component structure can also be selected. That is, Al x In y Ga 1-x-y N can be used as the quantum well layer and the barrier layer, wherein the proportion of aluminum and indium can be adjusted to obtain the barrier layer with high energy band gap and the quantum well layer with lower energy band gap.
  • the formation of the active layer is similar that of the aforesaid cladding layer of N-type conduction.
  • the precursor of indium can be trimethyl indium or triethyl indium.
  • the active layer can be doped with N-type or P-type dopants, and can be doped with both or neither.
  • the quantum layer can be without dopants, and the barrier layer can be with dopants; the quantum layer and the barrier layer can be both with dopants or both without dopants.
  • the partial regions of the quantum well layer can be with delta dopants.
  • the steps of forming the P-type semiconductor electron barrier layer 407 on the active layer 406 are optional.
  • the P-type semiconductor electron barrier layer 407 comprises a first III-V semiconductor layer and a second III-V semiconductor layer. These two III-V semiconductor layers with different energy band gaps are periodically and repeatedly disposed on the aforesaid active layers to act as an electron barrier with an energy band gap higher than the energy band gap of the active layer. Excessive electrons (e ⁇ ) can prevented from overflowing to the active layer 406 .
  • the details and formation of the electron barrier layer of P-type conduction can be found by referring to TW application No. 097128065 filed by the present applicant.
  • the P-type semiconductor conductive layer 408 can be a layer of gallium nitride or aluminum gallium nitride acting as a cladding layer of the P-type conduction of the LED.
  • the P-type conductive of gallium nitride or aluminum gallium nitride is formed in MOCVD equipment or MBE equipment. During the formation of the nitride layer, group II atoms are simultaneously doped. In this embodiment, the group II atoms are magnesium atoms.
  • the precursor of magnesium is Cp 2 Mg suitable for the MOCVD equipment.
  • a contact layer (not shown) of P-type conduction can be formed thereon.
  • the material of the contact layer of P-type conduction can be highly-doped gallium nitride or highly-doped aluminum gallium nitride to have a superior conductive effect with the P-type electrodes.

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Abstract

A semiconductor includes a semiconductor layer, a plurality of recesses and a blocking layer. The recesses are formed on a surface of the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. The blocking layer is filled in each recess. The semiconductor further includes a re-epitaxial semiconductor layer grown from a surface of the semiconductor layer without the covering of blocking layer, and the re-epitaxial semiconductor layer laterally overgrows toward areas of the recesses for overlaying the blocking layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This patent application is a divisional application of patent application Ser. No. 12/579,779, filed on Oct. 15, 2009, entitled “METHOD FOR BLOCKING DISLOCATION PROPAGATION OF SEMICONDUCTOR”, assigned to the same assignee, and disclosure of which is incorporated herein by reference in its entirety.
    • BACKGROUND
  • 1. Technical Field
  • The present invention relates to semiconductor with low dislocation, and a light emitting diode with the semiconductor.
  • 2. Description of Related Art
  • Currently, common solid state semiconductor devices include light emitting diodes (LED), laser diodes, and semiconductor RF (radio frequency) devices. Generally, the light emitting diode, the laser diode, or the semiconductor RF device includes a semiconductor device such as an RF device and a light emitting device with a p-n junction formed on the epitaxial substrate.
  • The structure of a blue or red light emitting diode comprises a sapphire substrate, a buffer layer formed on the sapphire substrate, an N-type GaN semiconductor layer, an active layer partly covering the N-type GaN semiconductor layer, a P-type GaN semiconductor layer formed on the active layer, and two contact electrodes respectively formed on the aforesaid two semiconductor layers.
  • The luminous efficiency of LEDs is affected by some factors such as internal quantum efficiency and external quantum efficiency. The major factor affecting the internal quantum efficiency is the amount of dislocation existing in the active layer. However, lattice mismatch always occurs in the materials of a sapphire substrate and a GaN layer. Therefore, the threading dislocation also occurs during the epitaxial process.
  • FIG. 1A is a schematic diagram of a prior art disclosed by Taiwanese patent publication No. TW561632. The device comprises a sapphire substrate 10, an N-type semiconductor layer 11 formed on the sapphire substrate 10, an active layer 12 capable of generating light with default wavelengths formed on the N-type semiconductor layer 11, and a P-type semiconductor layer 13 formed on the active layer 12.
  • A plurality of recesses 14 are periodically arranged and formed on the sapphire substrate 10 using photolithography equipment and a reactive ion etching process. Therefore, the N-type semiconductor layer 11 on the sapphire substrate 10 without crystal defects is filled in each of the recesses 14. The depth and width of each of the recesses 14 are respectively 1 μm and 10 μm. The pitch, defined as the distance between the centers of two adjacent recesses, is 10 μm.
  • A Bell, R. Liu, F. A. Ponce, H. Amano, I. Akasaki, D. Cherns, et al. propose a GaAlN doped with Mg grown on a patterned sapphire substrate in Applied Physics Letters, vol. 82, No. 3, pp. 349-351 and discuss its luminous characteristics and microstructure. This paper puts forth that a sapphire substrate patterned with a plurality of grooves is formed by performing photolithography and reactive ion etching processes, and an epitaxial layer of GaAlN doped with Mg is formed on the patterned sapphire substrate. A great deal of threading dislocation exists in the epitaxial layer, and the epitaxial lateral overgrowth (ELOG) regions of the epitaxial layer above each of the stripe-shaped grooves have no defects.
  • In addition, Shulij Nakamura, Masayuki Senoh, Shinichi Nagahama, Naruhito Iwasa, Takao Tamada, et al., researchers of Nichia Chemical Co., propose a laser diode of modulation-doped strained-layer superlattices formed on an epitaxial lateral overgrowth GaN substrate in Appl. Phys. Lett. 72(2), 211-213. Referring to FIG. 1B, a buffer layer 91 and a GaN layer with a thickness of 2 μm are sequentially formed on a sapphire substrate 90. A silica layer 93 with a thickness of 0.1 μm is further formed on the GaN layer 92, and the silica layer 93 has stripe-shaped windows 94 with a width of 4 μm by a photolithography process. The windows 94 of the silica layer 93 act as a mask (silica mask) on the GaN layer 92. Finally, an N-type GaN layer 95 is sequentially formed on the mask by a two jet-flow MOCVD method so that a sequential device can be formed thereon.
  • The researchers of Nichia utilize an amorphous mask to direct epitaxial vertical overgrowth layers in the windows 94 to be laterally merged with each other so as to form epitaxial lateral overgrowth layers on the mask. Accordingly, the dislocation density of the epitaxial layer is reduced.
  • Although the aforesaid prior patents and techniques can reduce the threading dislocation occurring in an epitaxial layer during an epitaxial process, all of the aforesaid recesses and windows are regularly arranged, so the dislocation defects cannot be completely eliminated.
  • Finding a means to reduce the dislocation density of an epitaxial layer during an epitaxial process and improving the luminous characteristics of the epitaxial layer are still critical issues for the manufacturers currently investing significant resources on research in the epitaxial field.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be described according to the appended drawings in which:
  • FIGS. 1A and 1B are schematic structure diagrams of a prior art;
  • FIG. 2 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor layer in accordance with the present invention;
  • FIG. 3 is an SEM picture showing recesses on the semiconductor in accordance with the present invention; and
  • FIG. 4 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor in accordance with another embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • The present invention is related to a semiconductor and a method for blocking the dislocation propagation of the semiconductor. For the purpose of understanding the present invention thoroughly, the descriptions below illustrate detailed steps and the compositions thereof. Clearly, the embodiment of the present invention is not limited to the particular method or the system familiar to those skilled in the art of blocking the dislocation propagation of a semiconductor. On the other hand, the ordinary skills in the art are not illustrated to avoid unnecessary limitations on the present invention. The preferred embodiments are illustrated below but the present invention may be utilized in other practices and should not be limited by such illustrated embodiments. The scope of the present invention should be interpreted in light of the claims.
  • Many papers have been proposed attempting to reduce the density of dislocation defects, but none of them can block dislocation defects. For example, U.S. Pat. No. 6,252,261 overlays a silica (SiO2) layer on a group III nitride semiconductor layer to act as masks regularly arranged. However, the dislocation defects cannot be completely blocked.
  • U.S. Pat. No. 6,861,270 interposes a silicon nitride layer between N-type and P-type group III nitride semiconductor layers by depositing so as to enable the spatial fluctuation of band-gap in an active layer. However, the defective density of the internal material cannot be reduced.
  • Furthermore, U.S. Pat. No. 6,462,357 forms island crystals by using group II nitride material ([Be, Mg, Ca, Sr, Ba, Zn, Cd, Hg]N) on a substrate or a group III nitride semiconductor layer. Because the adjustable parameters for epitaxial growth are limited, the optimal result is not easily obtained.
  • U.S. Pat. No. 6,627,974 utilizes an additional CVD process to form a protective film (SiOx, SixNy, TiOx, or ZrOx) which is regularly arranged. However, the dislocation defects cannot be completely blocked.
  • U.S. Pat. No. 6,345,063 utilizes silica or silicon nitride as a patterned mask layer having a regular layout. However, the dislocation defects cannot be completely blocked. In this patent, InGaN is directly grown on the patterned mask layer. Therefore, an epitaxial layer of high quality is not easily formed thereon.
  • TW patent No. 1242898 puts forth a method blocking the propagation of line dislocation occurring only in hexagon vias. As to line dislocation around the hexagon vias, a TEM (Transmission Electron Microscopy) picture cannot show any redirection effects on the dislocation because of lateral growth.
  • In contrast, the present invention provides a method for blocking the dislocation propagation of a semiconductor. Before dislocation defects go to an active layer, an epitaxial blocking layer with orientation is used to block the extension, in contrast to the epitaxial blocking layers without orientation as seen in the prior arts. Furthermore, the line dislocation is likely to be blocked because of lateral growth mechanism. First, a semiconductor layer is formed by epitaxial process on a substrate. Recesses are formed on the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. The aforesaid plurality of recesses can be formed by etching the semiconductor layer. When the semiconductor layer is etched, the fragile locations of the semiconductor layer resulted from the dislocation defects are etched to be recesses by etchant.
  • Thereafter, a blocking layer is formed on each of the recesses. The steps of forming the blocking layer on a plurality of recesses comprise: depositing a blocking layer on the semiconductor layer; coating photoresist on the blocking layer to fill in the plurality of recesses; removing the photoresist outside the plurality of recesses; removing the blocking layer outside the plurality of recesses by etching and leaving the blocking layer existing in the plurality of recesses; and removing the photoresist remaining on the plural areas of the blocking layer to expose the blocking layer existing in the recesses.
  • The same semiconductor layer undergoes epitaxial process again on the aforesaid semiconductor layer, and laterally grows to redirect the dislocation defects. The present invention further provides a method for blocking the dislocation propagation of a semiconductor. First, the aforesaid steps are performed at least one time. Thereafter, a compound semiconductor multilayer is formed by epitaxial process on the latter semiconductor layer to form an LED. The compound semiconductor multilayer comprises an N-type semiconductor conductive layer, a P-type semiconductor conductive layer, and an active layer, wherein the active layer is between the N-type semiconductor conductive layer and the P-type semiconductor conductive layer.
  • The material of the aforesaid substrate is sapphire (Al2O3), silicon carbide (SiC), AlLiO2, LiGaO2, silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), zinc selenide (ZnSe), or other metal. The present invention further comprises a buffer layer interposed between the aforesaid substrate and the compound semiconductor multilayer. The present invention also comprises a P-type semiconductor electron barrier layer interposed between the active layer and the P-type semiconductor conductive layer.
  • The aforesaid embodiments are particularized by diagrams and flow charts to show the structures and formation steps of the present invention.
  • FIG. 2 is a flow chart of manufacturing processes for blocking dislocation propagating in a semiconductor layer. First, as shown in Step 1, a substrate 100 is provided. A semiconductor layer 102 is formed on the substrate 100. The material of the substrate 100 is sapphire (Al2O3), silicon carbide (SiC), AlLiO2, LiGaO2, silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), or zinc selenide (ZnSe). The choice of material of the substrate is dependent on the sequential epitaxial material deposited on it. For example, II-VI semiconductor compound is commonly and preferably formed on a zinc selenide substrate or a zinc oxide substrate as an epitaxial base. Group III arsenide or Group III phosphide is commonly formed on a gallium arsenide substrate, a gallium phosphide substrate, an indium phosphide substrate, or an indium arsenide substrate. In the current LED market, Group III nitride is commonly formed on a sapphire substrate, or a silicon carbide substrate, and an AlLiO2 substrate, a LiGaO2 substrate, a silicon substrate, or an aluminum zinc oxide substrate is also used in an experimental stage. Furthermore, the structure and coefficient of crystal lattice are another consideration for selecting the epitaxial substrate. When the coefficients of crystal lattice of two layers are significantly different from each other, a buffer layer needs to be first formed on the lower layer to obtain a good quality upper epitaxial layer. In this embodiment, when the epitaxial material is Group III nitride, particularly gallium nitride, the common epitaxial substrate is a sapphire substrate or a silicon carbide substrate which is used in the current LED market. However, a person skilled in the art can understand the epitaxial material is not limited to the Group III nitride or even the gallium nitride. Any III-VI semiconductor compound or II-V semiconductor compound can be applied to the present invention.
  • When sapphire or silicon carbide is used to as the substrate, a buffer layer 101 is formed on the substrate prior to the formation of Group III nitride because the mismatch of the crystal lattice between the sapphire substrate and gallium nitride is as high as 14%. The mismatch of the crystal lattice between the silicon carbide substrate and gallium nitride is also as high as 3.5%. Generally, the material of the buffer layer 101 can be gallium nitride, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a superlattice structure of InGaN/InGaN. As to the superlattice structure of InGaN/InGaN, TW Patent Application No. 096104378 filed by Advanced Optoelectronic Technology Inc. introduces the detailed technology. The buffer layer 101 is deposited in epitaxial equipment such as MOCVD (metal organic chemical vapor deposition) equipment or MBE (molecular beam epitaxy) equipment under a temperature lower than the temperatures of forming sequential epitaxial layers. For example, AlGaInN undergoes epitaxial process between 800-1,400, and the buffer layer undergoes epitaxial process between 250-700. When the MOCVD equipment is used, the precursor of nitrogen can be NH3 or N2, the precursor of gallium can be trimethylgallium or Triethylgallium, the precursor of aluminum can be trimethylaluminum or Triethylaluminum, and the reaction chamber can be set to low pressure or normal pressure.
  • Thereafter, as shown in Step 2, a plurality of recesses 110 is formed by etching the fragile locations of the semiconductor layer 102 where dislocation occurs. A blocking layer 103 is formed on the semiconductor layer 102, as shown in Step 3. A photoresist is coated on the blocking layer 103 to form a photoresist layer 109 filling in the plurality of recesses 110, as shown in Step 4. As shown in Step 5, the photoresist layer 109 outside the plurality of recesses 110 is removed and the photoresist layer 109 inside the plurality of recesses 110 is left in place. As shown in Step 6, the blocking layer 103 outside the plurality of recesses 110 is removed and the blocking layer 103 existing in the plurality of recesses 110 is also left in place. The photoresist layer 109 remaining in the plurality of recesses 110 is removed by a photolithography process, as shown in Step 7. The material of the blocking layer 103 can be dielectric comprising magnesium nitride (MgxNy), silicon nitride (SixNy), silicon oxide (SixOy), titanium oxide (TWO, zirconium oxide (ZrxOy), hafnium oxide (HfxOy), tantalum oxide (TaxOy), silicon nitride (SiN), and silicon oxide (SiO).
  • Referring to Step 8, a re-epitaxial semiconductor layer 104 is formed by epitaxial process on the semiconductor layer 102. The aforesaid blocking layer 103 can block the growth of the semiconductor layer 104, and hence, the semiconductor layer 104 laterally overgrows toward the plurality of recesses 110. Accordingly, the dislocation is redirected so the defects of the dislocation are stopped in the re-epitaxial semiconductor layer 104, as shown in Steps 9, 10, and 11.
  • FIG. 3 is an SEM (scanning electron microscope) picture showing recesses on the semiconductor layer in accordance with the present invention.
  • The present invention applies the aforesaid method for blocking the dislocation propagation of a semiconductor to the LED fabrication so as to have a method for restraining dislocation defects inside LEDs. Referring to FIG. 4, this method performs at least one cycle of the aforesaid method for blocking the dislocation propagation of a semiconductor, and a re-epitaxial semiconductor layer 404. Thereafter, a compound semiconductor multilayer 420 is formed on the re-epitaxial semiconductor layer 404 to obtain an LED. Therefore, the density of dislocation defects inside the LED can be dramatically reduced by implementing the aforesaid method. The defects of the material are effectively restrained to improve the lighting characteristics and the electrical characteristics of light emitting devices.
  • First, by implementing the aforesaid steps, the dislocation defects of the re-epitaxial semiconductor layer 404 can be restrained. As shown in Step 20, a buffer layer 401 is formed on a substrate 400, and a semiconductor layer 402 is formed on the buffer layer 401. As shown in Step 21, a plurality of recesses 410 is formed on the semiconductor layer 402 by etching the semiconductor layer 402 where dislocation occurs. Thereafter, as shown in Step 22, a blocking layer 403 is formed on the semiconductor layer 402. As shown in Step 23, photoresist is coated on the blocking layer 403 as a photoresist layer 409 to fill in the plurality of recesses 410. Thereafter, as shown in Step 24, the photoresist layer 409 outside the plurality of recesses 410 is removed. As shown in Step 25, the photoresist layer 409 outside the plurality of recesses 410 is etched, and the photoresist layer 409 is left as a plurality of areas in the recesses 410. As shown in Step 26, the remaining photoresist layer 409 is removed by a photolithography process. As shown in Step 27, the same semiconductor layer 402 undergoes epitaxial process again on the aforesaid semiconductor layer 402, and laterally grows to form as a re-epitaxial semiconductor layer 404 for redirecting the dislocation defects.
  • As shown in Step 27, the dislocation defects cannot be completely restrained in the re-epitaxial semiconductor layer 404. Therefore, the aforesaid steps are performed again to further block the other dislocation, whereby the density of dislocation defects inside the device can be dramatically reduced.
  • Finally, as shown in Step 28, a compound semiconductor multilayer 420 is formed by epitaxial process on the re-epitaxial semiconductor layer 404 to form an LED. The compound semiconductor multilayer 420 comprises an N-type semiconductor conductive layer 405, an active layer 406, and a P-type semiconductor conductive layer 408. Furthermore, the aforesaid LED further comprises a P-type semiconductor electron barrier 407 between the active layer 406 and the P-type semiconductor conductive layer 408 so as to improve the light extraction efficiency of the LED. In a preferred embodiment of the present invention, the N-type semiconductor conductive layer 405, the active layer 406, the P-type semiconductor electron barrier layer 407, and the P-type semiconductor conductive layer 408 can all be group III nitride.
  • The N-type semiconductor conductive layer 405 can be a layer of gallium nitride or aluminum gallium nitride acting as a cladding layer of the N-type conduction of the LED. The N-type conduction of gallium nitride or aluminum gallium nitride is formed in MOCVD equipment or MBE equipment. During the formation of the nitride layer, group IV atoms are simultaneously doped. In this embodiment, the group IV atoms are silicon atoms. The precursor of silicon is silane or disilane suitable for the MOCVD equipment. Under the cladding layer, a gallium nitride layer (not shown) without dopant and a contact layer (not shown) of the N-type conduction can be previously and sequentially formed on the buffer layer, and the formation steps of the two layers are optional for this embodiment. The gallium nitride layer without dopant can improve the epitaxial quality of the cladding layer of the N-type conduction. The material of the contact layer of the N-type conduction can be highly-doped gallium nitride or highly-doped aluminum gallium nitride to have a superior conductive effect with the N-type electrodes.
  • The aforesaid active layer 406 can be a single heterostructure structure, a double heterostructure structure, a single quantum well structure, or a structure of multi quantum well layers/barrier layers. The material of the quantum well layer can be indium gallium nitride, and the material of the barrier can be a ternary component structure such as aluminum gallium nitride. Furthermore, a quaternary component structure can also be selected. That is, AlxInyGa1-x-yN can be used as the quantum well layer and the barrier layer, wherein the proportion of aluminum and indium can be adjusted to obtain the barrier layer with high energy band gap and the quantum well layer with lower energy band gap. The formation of the active layer is similar that of the aforesaid cladding layer of N-type conduction. The precursor of indium can be trimethyl indium or triethyl indium. The active layer can be doped with N-type or P-type dopants, and can be doped with both or neither. Furthermore, the quantum layer can be without dopants, and the barrier layer can be with dopants; the quantum layer and the barrier layer can be both with dopants or both without dopants. The partial regions of the quantum well layer can be with delta dopants.
  • The steps of forming the P-type semiconductor electron barrier layer 407 on the active layer 406 are optional. The P-type semiconductor electron barrier layer 407 comprises a first III-V semiconductor layer and a second III-V semiconductor layer. These two III-V semiconductor layers with different energy band gaps are periodically and repeatedly disposed on the aforesaid active layers to act as an electron barrier with an energy band gap higher than the energy band gap of the active layer. Excessive electrons (e−) can prevented from overflowing to the active layer 406. The details and formation of the electron barrier layer of P-type conduction can be found by referring to TW application No. 097128065 filed by the present applicant.
  • Furthermore, the P-type semiconductor conductive layer 408 can be a layer of gallium nitride or aluminum gallium nitride acting as a cladding layer of the P-type conduction of the LED. The P-type conductive of gallium nitride or aluminum gallium nitride is formed in MOCVD equipment or MBE equipment. During the formation of the nitride layer, group II atoms are simultaneously doped. In this embodiment, the group II atoms are magnesium atoms. The precursor of magnesium is Cp2Mg suitable for the MOCVD equipment. Above the cladding layer, a contact layer (not shown) of P-type conduction can be formed thereon. The material of the contact layer of P-type conduction can be highly-doped gallium nitride or highly-doped aluminum gallium nitride to have a superior conductive effect with the P-type electrodes.
  • The above-described embodiments of the present invention are intended to be illustrative only. Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.

Claims (14)

1. A semiconductor, comprising:
a semiconductor layer;
a plurality of recesses formed on a surface of the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs;
a blocking layer filled in each recess; and
a re-epitaxial semiconductor layer grown from a surface of the semiconductor layer without the covering of blocking layer and laterally overgrown toward areas of the recesses for overlaying the blocking layer.
2. The semiconductor of claim 1, wherein the material of the blocking layer is dielectric, and is selected from the group consisting of magnesium nitride (MgxNy), silicon nitride (SixNy), silicon oxide (SixOy), titanium oxide (TixOy), zirconium oxide (ZrxOy), hafnium oxide (HfxOy), tantalum oxide (TaxOy), silicon nitride (SiN), and silicon oxide (SiO).
3. The semiconductor of claim 1, further comprising a substrate for growth of the semiconductor layer.
4. The semiconductor of claim 3, wherein the material of the substrate is sapphire (Al2O3), silicon carbide (SiC), AlLiO2, LiGaO2, silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), or zinc selenide (ZnSe).
5. The semiconductor of claim 3, further comprising a buffer layer formed between the substrate and the semiconductor layer.
6. The semiconductor of claim 5, wherein the buffer layer is deposited in an epitaxial equipment selected from one of MOCVD equipment and MBE equipment.
7. A light emitting diode, comprising:
a semiconductor layer
a plurality of recesses formed on a surface of the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs;
a blocking layer filled in each recess;
a re-epitaxial semiconductor layer grown from a surface of the semiconductor layer without the covering of blocking layer and laterally overgrown toward areas of the recesses for overlaying the blocking layer; and
a lighting structure formed on a surface of the re-epitaxial semiconductor layer.
8. The light emitting diode of claim 7, wherein the lighting structure comprises an N-type semiconductor conductive layer, an active layer, and a P-type semiconductor conductive layer, and the active layer is between the N-type semiconductor conductive layer and the P-type semiconductor conductive layer.
9. The light emitting diode of claim 8, wherein the lighting structure further comprises a P-type semiconductor electron barrier layer formed between the active layer and the P-type semiconductor conductive layer.
10. The light emitting diode of claim 7, wherein the material of the blocking layer is dielectric, and is selected from the group consisting of magnesium nitride (MgxNy), silicon nitride (SixNy), silicon oxide (SixOy), titanium oxide (TixOy), zirconium oxide (ZrxOy), hafnium oxide (HfxOy), tantalum oxide (TaxOy), silicon nitride (SiN), and silicon oxide (SiO).
11. The light emitting diode of claim 7, further comprising a substrate for growth of the semiconductor layer.
12. The light emitting diode of claim 11, wherein the material of the substrate is sapphire (Al2O3), silicon carbide (SiC), AlLiO2, LiGaO2, silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), or zinc selenide (ZnSe).
13. The light emitting diode of claim 11, further comprising a buffer layer formed between the substrate and the semiconductor layer.
14. The light emitting diode of claim 13, wherein the buffer layer is deposited in an epitaxial equipment selected from one of MOCVD equipment and MBE equipment.
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