CN214176022U - Wafer level package structure - Google Patents
Wafer level package structure Download PDFInfo
- Publication number
- CN214176022U CN214176022U CN202120075382.XU CN202120075382U CN214176022U CN 214176022 U CN214176022 U CN 214176022U CN 202120075382 U CN202120075382 U CN 202120075382U CN 214176022 U CN214176022 U CN 214176022U
- Authority
- CN
- China
- Prior art keywords
- chip
- package structure
- level package
- metal
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a wafer level packaging structure, including the chip body, the chip body has first surface and the second surface that is parallel to each other, and the first surface is formed with chip source electrode and chip grid, and the second surface is formed with the chip drain electrode, and the chip drain electrode is connected to the first surface through the conductive metal who runs through the chip body, and the first surface is provided with the metal pad that forms through rewiring, and chip source electrode, chip grid and chip drain electrode electricity respectively connect in the metal pad. Through set up the conductive metal that runs through the chip body setting on the chip drain electrode to make the chip drain electrode derive on the first surface, so that three electrode can be located the coplanar, need not adopt the lead frame again to carry out the electrode derivation, it can the direct mount on the PCB board, makes the installation more convenient, simultaneously, has also saved whole manufacturing cost effectively.
Description
Technical Field
The utility model belongs to the technical field of the chip architecture, more specifically say, it relates to a wafer level packaging structure.
Background
The power chip generally has three electrodes, namely a chip source electrode, a chip gate electrode and a chip drain electrode, which are respectively distributed on two surfaces of the power chip, so that when the power chip is mounted on a PCB, the three electrodes must be led out on the same plane by using a lead frame and a metal wire, and the power chip can be mounted on the PCB, which is not convenient enough in mounting and has higher production cost.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an aim at: a wafer level package structure is provided, which can solve the above problems in the prior art.
The above technical purpose of the present invention can be achieved by the following technical solutions:
the wafer level packaging structure comprises a chip body, wherein the chip body is provided with a first surface and a second surface which are parallel to each other, a chip source electrode and a chip grid electrode are formed on the first surface, a chip drain electrode is formed on the second surface and is connected to the first surface through conductive metal penetrating through the chip body, a metal bonding pad formed by rewiring is arranged on the first surface, and the chip source electrode, the chip grid electrode and the chip drain electrode are respectively and electrically connected to the metal bonding pad.
As a preferred technical solution of the wafer level package structure, the chip body is provided with a through hole penetrating through the first surface and the second surface, and the conductive metal penetrates through the through hole to electrically connect the first surface and the second surface.
As a preferable technical solution of the wafer level package structure, the chip body is provided with a plurality of through holes, and the conductive metal is provided with a plurality of through holes corresponding to the through holes.
As a preferable technical solution of the wafer level package structure, the wafer level package structure further includes a first insulating layer, the first insulating layer is disposed on the first surface of the chip body and covers the chip source, the chip gate and the periphery of the conductive metal for insulating the chip source, the chip gate and the conductive metal from each other.
As a preferable aspect of the wafer level package structure, the first insulating layer further covers an inner gap and a peripheral portion of the metal pad.
As a preferable technical solution of the wafer level package structure, the metal pad penetrates through the first insulating layer, so that an outer surface of the metal pad is exposed to an outer surface of the first insulating layer.
As a preferred technical solution of the wafer level package structure, a source solder ball, a gate solder ball and a drain solder ball are disposed on an outer surface of the metal pad.
As a preferable technical solution of the wafer level package structure, the package structure further includes a second insulating layer, and the second insulating layer covers an outer surface of the chip drain.
As a preferable technical solution of the wafer level package structure, the package structure further includes a heat dissipation layer, and the heat dissipation layer covers an outer surface of the second insulating layer.
As a preferred technical solution of the wafer level package structure, the heat dissipation layer is a metal layer or a graphene layer.
To sum up, the utility model discloses following beneficial effect has:
the utility model provides a wafer level packaging structure, the first surface on its chip body is formed with chip source electrode, chip grid, and its second surface is formed with the chip drain electrode, through set up the conductive metal that runs through the chip body setting on the chip drain electrode to make the chip drain electrode derive on the first surface. Meanwhile, a metal bonding pad formed by rewiring is arranged on the first surface, and the chip source electrode, the chip grid electrode and the chip drain electrode are electrically connected to the metal bonding pad respectively, so that the three electrodes can be located on the same plane, redistribution of electrode positions is carried out through the metal bonding pad, electrode leading-out is not needed to be carried out through a lead frame, the three electrodes can be directly installed on a PCB, installation is more convenient and quicker, and meanwhile, the whole production cost is effectively saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a wafer level package structure according to the present invention.
In the figure:
100. a chip body; 200. chip source electrode 300, chip grid electrode; 400. a chip drain electrode; 410. a conductive metal; 500. a metal pad; 510. a source solder ball; 520. a grid solder ball; 530. a drain solder ball; 600. a first insulating layer; 700. a second insulating layer; 800. and a heat dissipation layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a wafer level packaging structure to when solving present power chip and installing on the PCB board, not convenient enough technical problem.
Hereinafter, referring to fig. 1, the wafer level package structure is described in detail, and the wafer level package structure includes a chip body 100, where the chip body 100 has a first surface and a second surface parallel to each other, the first surface is formed with a chip source 200 and a chip gate 300, the second surface is formed with a chip drain 400, the chip drain 400 is connected to the first surface through a conductive metal 410 penetrating through the chip body 100, the first surface is provided with a metal pad 500 formed by a redistribution, and the chip source 200, the chip gate 300, and the chip drain 400 are electrically connected to the metal pad 500, respectively.
Specifically, the chip body 100 is circular, and the chip is specifically a power chip, and the wafer level package structure is suitable for MOSFET power devices. In this embodiment, the conductive metal 410 disposed through the chip body 100 is disposed on the chip drain 400, so that the chip drain 400 penetrates the chip body 100 from the second surface and is led out on the first surface, and further, the chip drain 400 is led out to the metal pad 500 disposed on the first surface.
In this way, the die source 200, the die gate 300 and the die drain 400 are all electrically connected to the metal pad 500, and the metal pad 500 is formed by re-wiring, so that the die source 200, the die gate 300 and the die drain 400 electrically connected to the metal pad 500 can be redistributed in position to be flexibly arranged according to actual requirements.
Through exporting chip drain 400 to with chip source 200 and chip grid 300 the same metal pad 500 on, also on the coplanar, make chip body 100 need not adopt the lead frame again to export each electrode at the coplanar, adopt the packaging structure in this scheme, it can the direct mount on the PCB board, it is more convenient, swift in the scheme that needs to adopt the lead frame in the past, simultaneously, the cost of lead frame has also been saved effectively, in order to save overall structure's manufacturing cost.
The utility model provides a wafer level packaging structure, the first surface on its chip body 100 is formed with chip source electrode 200, chip grid 300, and its second surface is formed with chip drain electrode 400, through the electrically conductive metal 410 that runs through chip body 100 setting on chip drain electrode 400 to make chip drain electrode 400 derive on the first surface. Meanwhile, a metal bonding pad 500 formed by rewiring is arranged on the first surface, and the chip source electrode 200, the chip grid electrode 300 and the chip drain electrode 400 are electrically connected to the metal bonding pad 500 respectively, so that the three electrodes can be located on the same plane, redistribution of the electrode positions is carried out through the metal bonding pad 500, electrode lead-out by adopting a lead frame is not needed, the three electrodes can be directly installed on a PCB, installation is more convenient and faster, and meanwhile, the whole production cost is effectively saved.
In order to realize the above package structure, the chip body 100 is provided with a through hole penetrating through the first surface and the second surface, and the conductive metal 410 is disposed through the through hole to electrically connect the first surface and the second surface.
Specifically, a through hole region is reserved in the chip body 100, and the through hole is formed in the through hole region, so that the conductive metal 410 penetrates through the chip body 100 through the through hole, and meanwhile, the conductive metal 410 is accommodated in the through hole, thereby effectively ensuring the structural stability of the conductive metal 410, and ensuring the conductive performance and the use stability of stably guiding the chip drain 400 out to the first surface of the chip body 100.
As a preferred technical solution of the wafer level package structure, in order to ensure that the chip body 100 can bear a large current, a plurality of through holes are formed in the chip body 100, a plurality of conductive metals 410 are provided corresponding to the through holes, and each conductive metal 410 penetrates through each through hole.
Through set up a plurality of through-holes on chip body 100 to make conductive metal 410 set up to a plurality ofly corresponding to the quantity of through-hole, through increasing the quantity of conductive metal 410, in order to increase the area of contact of conductive metal 410 with metal pad 500, in order to improve the electric current volume through conductive metal 410 effectively, make chip body 100 can bear bigger electric current.
The number of the conductive metals 410 can be flexibly set according to actual requirements, and is not limited herein.
As a preferable technical solution of the wafer level package structure, the wafer level package structure further includes a first insulating layer 600, wherein the first insulating layer 600 is disposed on the first surface of the chip body 100 and covers the chip source 200, the chip gate 300 and the periphery of the conductive metal 410 for mutual insulation therebetween.
Specifically, the first insulating layer 600 covers the periphery of the chip source 200, the chip gate 300 and the conductive metal 410, so that the gap between the chip source 200 and the chip gate 300 is covered with the first insulating layer 600, and the chip source 200, the chip gate 300 and the conductive metal 410 are covered inside the first insulating layer 600, so that the chip source 200, the chip gate 300 and the conductive metal 410 are not exposed outside, and the structural stability and the use stability of the chip source 200, the chip gate 300 and the conductive metal 410 are effectively ensured.
As a preferable aspect of the wafer level package structure, the first insulating layer 600 further covers an inner gap and a peripheral portion of the metal pad 500.
Also, the first insulating layer 600 covers the inner gap and the peripheral portion of the metal pad 500, and the first insulating layer 600 fills the inner gap of the metal pad 500, so that the structural strength of the inner structure and the structural strength of the peripheral portion of the metal pad 500 are effectively enhanced, and the structural stability and the use stability of the metal pad are ensured.
As a preferred technical solution of the wafer level package structure, the metal pad 500 penetrates through the first insulating layer 600, so that an outer surface of the metal pad 500 is exposed at an outer surface of the first insulating layer 600.
Therefore, the outer surface of the metal pad 500 is exposed to the outside through the first insulating layer 600, and the external PCB board is used through the outer surface of the metal pad 500, so that the metal pad can be packaged in the first insulating layer 600 while ensuring that the metal pad has a sufficient use area, thereby minimizing the exposed area of the metal pad 500 and ensuring that the metal pad has a greater structural stability.
In order to facilitate the solder mounting of the metal pad 500 and the PCB, a source solder ball 510, a gate solder ball 520, and a drain solder ball 530 are disposed on the outer surface of the metal pad 500.
Specifically, the source solder ball 510, the gate solder ball 520, and the drain solder ball 530 are respectively disposed on the corresponding electrode position formed by the redistribution of the metal pad 500, and when the metal pad 500 is soldered to the PCB, the source solder ball 510, the gate solder ball 520, and the drain solder ball 530 can be directly soldered, so that the mounting process is more convenient.
As a preferable technical solution of the wafer level package structure, the wafer level package structure further includes a second insulating layer 700, and the second insulating layer 700 covers an outer surface of the chip drain 400.
The chip drain 400 is insulated from the outside by the second insulating layer 700, so that the chip drain 400 cannot be communicated with an external electrode, the chip drain 400 is protected, and meanwhile, the chip drain 400 is covered by the second insulating layer, so that the chip drain 400 is effectively packaged, and the chip drain 400 has better protection and protection effects.
In order to improve the heat dissipation performance of the wafer level package structure in the present embodiment, the wafer level package structure further includes a heat dissipation layer 800, and the heat dissipation layer 800 covers the outer surface of the second insulation layer 700.
Specifically, the heat dissipation layer 800 is a metal layer or a graphene layer, and in other embodiments, the heat dissipation layer may also be a material layer with higher heat dissipation performance, which is not limited herein.
It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A wafer level packaging structure is characterized by comprising a chip body, wherein the chip body is provided with a first surface and a second surface which are parallel to each other, a chip source electrode and a chip grid electrode are formed on the first surface, a chip drain electrode is formed on the second surface and is connected to the first surface through conductive metal penetrating through the chip body, a metal bonding pad formed by rewiring is arranged on the first surface, and the chip source electrode, the chip grid electrode and the chip drain electrode are respectively and electrically connected to the metal bonding pad.
2. The wafer-level package structure of claim 1, wherein the chip body defines a through hole penetrating the first surface and the second surface, and the conductive metal is disposed through the through hole to electrically connect the first surface and the second surface.
3. The wafer-level package structure of claim 2, wherein the chip body is formed with a plurality of the through holes, and the conductive metal is formed in a plurality corresponding to the through holes.
4. The wafer-level package structure of claim 1, further comprising a first insulating layer disposed on the first surface of the chip body and covering the chip source, the chip gate and the periphery of the conductive metal for insulating the chip source, the chip gate and the conductive metal from each other.
5. The wafer-level package structure of claim 4, wherein the first insulating layer further covers an inner gap and a periphery of the metal pad.
6. The wafer-level package structure of claim 5, wherein the metal pad penetrates the first insulating layer such that an outer surface of the metal pad is exposed at an outer surface of the first insulating layer.
7. The wafer level package structure of claim 6, wherein the metal pads have source solder balls, gate solder balls, and drain solder balls on the outer surface.
8. The wafer-level package structure of claim 1, further comprising a second insulating layer, wherein the second insulating layer covers an outer surface of the chip drain.
9. The wafer-level package structure of claim 8, further comprising a heat dissipation layer, wherein the heat dissipation layer covers an outer surface of the second insulating layer.
10. The wafer level package structure of claim 9, wherein the heat spreading layer is a metal layer or a graphene layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120075382.XU CN214176022U (en) | 2021-01-12 | 2021-01-12 | Wafer level package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120075382.XU CN214176022U (en) | 2021-01-12 | 2021-01-12 | Wafer level package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214176022U true CN214176022U (en) | 2021-09-10 |
Family
ID=77593214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120075382.XU Active CN214176022U (en) | 2021-01-12 | 2021-01-12 | Wafer level package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214176022U (en) |
-
2021
- 2021-01-12 CN CN202120075382.XU patent/CN214176022U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104641459B (en) | Semiconductor device | |
| CN109616452B (en) | Heat radiation assembly, corresponding heat radiation device and corresponding circuit board | |
| CN208111434U (en) | Power module | |
| CN201946588U (en) | Packaging structure for power semiconductors | |
| CN108496249A (en) | Semiconductor device | |
| CN214176022U (en) | Wafer level package structure | |
| US8031484B2 (en) | IC packages with internal heat dissipation structures | |
| CN219435850U (en) | MOSFET chip packaging structure | |
| CN206595249U (en) | Carry the SOP device encapsulation structures of high current | |
| JP4026188B2 (en) | Printed wiring board | |
| CN206931585U (en) | A kind of power IC device and supply unit | |
| JP2000188359A (en) | Semiconductor package | |
| CN107275295A (en) | A kind of power IC device, method for packing and supply unit | |
| JP2845488B2 (en) | Semiconductor integrated circuit device | |
| CN206532770U (en) | The new SOP structures of chip package | |
| CN218299797U (en) | Multi-chip sealed semiconductor packaging structure | |
| CN218585975U (en) | Semiconductor packaging structure | |
| CN207800587U (en) | A kind of chip electrode bonding wire interconnection compact package structure | |
| CN213026106U (en) | Tube core packaging structure with good heat dissipation | |
| CN216435895U (en) | Integrated MOS module used for BMS | |
| CN219999689U (en) | Circuit board assembly | |
| CN204558445U (en) | Semiconductor packaging structure | |
| KR20190085587A (en) | High thermal conductivity semiconductor package | |
| CN213340380U (en) | Semiconductor device packaging structure | |
| CN218585980U (en) | Novel semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |