JP2845488B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2845488B2 JP2845488B2 JP10060989A JP10060989A JP2845488B2 JP 2845488 B2 JP2845488 B2 JP 2845488B2 JP 10060989 A JP10060989 A JP 10060989A JP 10060989 A JP10060989 A JP 10060989A JP 2845488 B2 JP2845488 B2 JP 2845488B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit chip
- radiator
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に放熱効果を
高めた大消費電力の半導体集積回路装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device with high power consumption and improved heat dissipation.
従来、大消費電力の半導体集積回路装置は、半導体集
積回路チップをパッケージに封入後、このパッケージの
一部に金属体等からなる放熱板を接触させて放熱効果を
得る構成となっていた。2. Description of the Related Art Conventionally, a semiconductor integrated circuit device with large power consumption has a configuration in which a semiconductor integrated circuit chip is sealed in a package, and a heat radiating plate made of a metal body or the like is brought into contact with a part of the package to obtain a heat radiation effect.
例えば、第３図はその一例であり、パッケージ基板11
に設けた凹部11a内に接着材12を用いて半導体集積回路
チップ13を搭載している。この半導体集積回路チップ13
は、その電極パッド13aをパッケージ基板11に設けた配
線15にボンディングワイヤ16を用いて接続し、外部リー
ド18によって外部に導出している。また、この半導体集
積回路チップ13は、パッケージ基板11に取着したキャッ
プ17により封止される。For example, FIG. 3 shows an example of such a case.
The semiconductor integrated circuit chip 13 is mounted in the concave portion 11a provided by using the adhesive 12. This semiconductor integrated circuit chip 13
The electrode pad 13a is connected to a wiring 15 provided on the package substrate 11 by using a bonding wire 16 and is led out by an external lead 18. The semiconductor integrated circuit chip 13 is sealed by a cap 17 attached to the package substrate 11.
そして、前記パッケージ基板11の上面側には前記凹部
11aに至る穴をあけ、この穴内に金属体19を挿入して半
導体集積回路チップ13の裏面に接触させる。更に、この
金属体19の上面に金属等の熱伝導性の高い放熱体20を接
着材21により接続している。The concave portion is provided on the upper surface side of the package substrate 11.
A hole reaching 11a is made, and a metal body 19 is inserted into this hole to make contact with the back surface of the semiconductor integrated circuit chip 13. Further, a radiator 20 having high thermal conductivity such as metal is connected to the upper surface of the metal body 19 by an adhesive 21.
この構成によれば、半導体集積回路チップ13に発生し
た熱は、金属体19を介して放熱体20に伝達され、この放
熱体20から放熱される。According to this configuration, the heat generated in the semiconductor integrated circuit chip 13 is transmitted to the radiator 20 via the metal body 19, and is radiated from the radiator 20.
上述した従来の放熱構造では、半導体集積回路チップ
13と放熱体20との間に両者を熱的に接続するための金属
体19を介在させる必要があるため、分部品点数が増大し
かつ構成が複雑になる。また、半導体集積回路チップ13
に発生した熱を金属体21を介して放熱体20に伝達させる
ため、その分熱伝導効果が低下され、放熱効果が低減さ
れるという問題がある。In the conventional heat dissipation structure described above, the semiconductor integrated circuit chip
Since it is necessary to interpose a metal body 19 for thermally connecting the two to each other between the heat radiator 13 and the heat radiator 20, the number of components increases and the configuration becomes complicated. In addition, the semiconductor integrated circuit chip 13
Is transferred to the heat radiator 20 via the metal body 21, so that the heat conduction effect is reduced and the heat radiation effect is reduced.
本発明は構成を簡単にする一方で放熱効果を高めるこ
とができる半導体集積回路装置を提供することを目的と
する。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device capable of simplifying the structure and improving the heat radiation effect.
本発明の半導体集積回路装置は、中央部に開孔部を有
し内部配線が施され前記内部配線に接続される外部リー
ドが埋め込まれた配線基板と、前記配線基板に取着され
前記開孔部に対応する位置に凹部を設けた高熱伝導体で
構成された放熱体と、前記放熱体の前記凹部内に高熱伝
導度を有する接着材により接着固定され前記凹部の深さ
よりも厚みの薄い半導体集積回路チップと、前記凹部を
充填し前記内部配線に電気接続された前記半導体集積回
路チップを埋設する樹脂とを備え、前記配線基板と前記
放熱体とが同じ幅であることを特徴とする。A semiconductor integrated circuit device according to the present invention includes a wiring board having an opening in the center, an internal wiring being provided, and an external lead connected to the internal wiring embedded therein, and the opening being attached to the wiring board. A radiator formed of a high thermal conductor having a concave portion at a position corresponding to a portion, and a semiconductor having a thickness smaller than the depth of the concave portion which is adhered and fixed in the concave portion of the radiator by an adhesive having high thermal conductivity. An integrated circuit chip and a resin filling the concave portion and burying the semiconductor integrated circuit chip electrically connected to the internal wiring are provided, and the wiring board and the radiator have the same width.
この構成では、半導体集積回路チップの熱を直接的に
放熱体に伝達させるため、熱の伝導効率を高めて放熱効
果を向上させる。また、半導体集積回路チップと放熱体
との間に金属体を介在させる必要がなく、構成の簡易化
を実現する。In this configuration, since the heat of the semiconductor integrated circuit chip is directly transmitted to the heat radiator, the heat conduction efficiency is increased and the heat radiation effect is improved. In addition, there is no need to interpose a metal body between the semiconductor integrated circuit chip and the heat radiator, so that the configuration can be simplified.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１実施例の断面図である。放熱体
１は高熱伝導性を有する比較的厚い金属板で構成し、そ
の下面中央に凹部1aを形成している。そして、この凹部
1a内には高熱伝導度を有する絶縁性または導電性の接着
材２を介して半導体集積回路チップ３を搭載している。
また、前記放熱体１の凹部1aの周囲には配熱基板４を取
着しており、前記半導体集積回路チップ３の電極パッド
3aをボンディングワイヤ６によって前記配線基板４に設
けた配線５に接続している。FIG. 1 is a sectional view of a first embodiment of the present invention. The heat radiator 1 is made of a relatively thick metal plate having high thermal conductivity, and has a concave portion 1a formed in the center of the lower surface thereof. And this recess
A semiconductor integrated circuit chip 3 is mounted in 1a via an insulating or conductive adhesive 2 having high thermal conductivity.
Further, a heat distribution substrate 4 is attached around the concave portion 1a of the heat radiator 1, and an electrode pad of the semiconductor integrated circuit chip 3 is provided.
3a is connected to a wiring 5 provided on the wiring board 4 by a bonding wire 6.
そして、前記半導体集積回路チップ3,ボンディングワ
イヤ５等を樹脂７を用いて封止している。この樹脂７は
集積回路の外部との電気的絶縁性及び耐湿性を実現する
ために充填されたものである。また、この樹脂７を通し
て前記配線５に外部リード８を接続し、この外部リード
８をピングリッドアレイタイプのパッケージ端子として
外部に取り出している。Then, the semiconductor integrated circuit chip 3, the bonding wires 5 and the like are sealed with a resin 7. This resin 7 is filled in order to realize electrical insulation and moisture resistance from the outside of the integrated circuit. An external lead 8 is connected to the wiring 5 through the resin 7, and the external lead 8 is taken out as a pin grid array type package terminal.
この構成によれば、半導体集積回路チップ３に発生し
た熱を放熱体１に直接伝達させてここから放熱を行うの
で、半導体集積回路チップ３の熱を高い効率で放熱する
ことが可能となり、その放熱効果を高めることができ
る。また、半導体集積回路チップ３と放熱体１との間に
は他の部品を介在させる必要がないため、構成を簡単な
ものにできる。According to this configuration, since the heat generated in the semiconductor integrated circuit chip 3 is directly transmitted to the radiator 1 and heat is radiated therefrom, the heat of the semiconductor integrated circuit chip 3 can be radiated with high efficiency. The heat radiation effect can be enhanced. Further, since there is no need to interpose other components between the semiconductor integrated circuit chip 3 and the heat radiator 1, the configuration can be simplified.
また、放熱体１に配線基板４を一体的に設け、この配
線基板４に形成した配線５を介して半導体集積回路チッ
プ３と外部リード８とを電気接続しているので、従来の
パッケージ基板と同様の取扱いで半導体集積回路チップ
を搭載し、かつ半導体集積回路装置の組立てを行うこと
ができる。Further, since the wiring board 4 is integrally provided on the heat radiator 1 and the semiconductor integrated circuit chip 3 and the external leads 8 are electrically connected through the wiring 5 formed on the wiring board 4, the conventional package board and the conventional package board are electrically connected. The semiconductor integrated circuit chip can be mounted and the semiconductor integrated circuit device can be assembled in the same manner.
第２図は本発明の第２実施例の断面図であり、第１実
施例と同一部分には同一符号を付して詳細な説明は省略
する。FIG. 2 is a sectional view of a second embodiment of the present invention, in which the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.
この実施例では、配線基板４に設けた配線５の外端部
をそのまま外部リード8Aとして突出させており、フラッ
トパッケージ型の半導体集積回路装置として構成してい
る。In this embodiment, the outer end of the wiring 5 provided on the wiring board 4 is protruded as the external lead 8A as it is, and is configured as a flat package type semiconductor integrated circuit device.
以上説明したように本発明は、高熱伝導体で形成した
放熱体の一面に、高熱伝導性の接着材を用いて半導体集
積回路チップを接着支持しているので、半導体集積回路
チップの熱を直接的に放熱体に伝達させて熱の伝導効率
を高め、放熱効果を向上させることができる。また、半
導体集積回路チップと放熱体との間に金属体を介在させ
る必要がなく、構成を簡略化できる。As described above, according to the present invention, since the semiconductor integrated circuit chip is bonded and supported on one surface of the heat radiator formed of the high thermal conductor using a high thermal conductive adhesive, the heat of the semiconductor integrated circuit chip is directly transferred. The heat is efficiently transmitted to the radiator to increase the heat conduction efficiency, and the heat radiation effect can be improved. Further, there is no need to interpose a metal body between the semiconductor integrated circuit chip and the heat radiator, and the configuration can be simplified.
また、放熱体に配線基板を一体的に設け、この配線基
板に形成した配線を介して半導体集積回路チップと外部
リードとを電気接続しているので、従来のパッケージ基
板と同様の取扱いで半導体集積回路チップの搭載及び組
立てを行うことができる。In addition, since the wiring board is integrally provided on the radiator and the semiconductor integrated circuit chip and the external leads are electrically connected via the wiring formed on the wiring board, the semiconductor integrated circuit is handled in the same manner as the conventional package board. Circuit chips can be mounted and assembled.
また、本発明では、半導体集積回路チップは、放熱体
の凹部の深さよりも薄く形成されているので、半導体集
積回路チップから放射される熱の殆どを凹部の内面に輻
射し、放熱体に対して伝達することができるため、前記
した放熱効果を更に高めることが可能となる。Further, in the present invention, since the semiconductor integrated circuit chip is formed to be thinner than the depth of the concave portion of the heat radiator, most of the heat radiated from the semiconductor integrated circuit chip radiates to the inner surface of the concave portion, and , The heat radiation effect described above can be further enhanced.
第１図は本発明の第１実施例の断面図、第２図は本発明
の第２実施例の断面図、第３図は従来の半導体集積回路
装置の断面図である。 １……放熱体、２……接着材、３……半導体集積回路チ
ップ、４……配線基板、５……配線、６……ボンディン
グワイヤ、７……樹脂、8,8A……外部リード、11……放
熱体、12……接着材、13……半導体集積回路チップ、15
……配線、16……ボンディングワイヤ、17……キャッ
プ、18……外部リード、19……金属体、20……放熱体、
21……接着材。FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIG. 3 is a sectional view of a conventional semiconductor integrated circuit device. DESCRIPTION OF SYMBOLS 1 ... Heat dissipator, 2 ... Adhesive material, 3 ... Semiconductor integrated circuit chip, 4 ... Wiring board, 5 ... Wiring, 6 ... Bonding wire, 7 ... Resin, 8, 8A ... External lead, 11 ... heat radiator, 12 ... adhesive, 13 ... semiconductor integrated circuit chip, 15
... wiring, 16 ... bonding wire, 17 ... cap, 18 ... external lead, 19 ... metal body, 20 ... radiator,
21 ... Adhesive.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/36,23/40 H01L 21/60──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23 / 36,23 / 40 H01L 21/60
Claims (1)
記内部配線に接続される外部リードが埋め込まれた配線
基板と、前記配線基板に取着され前記開孔部に対応する
位置に凹部を設けた高熱伝導体で構成された放熱体と、
前記放熱体の前記凹部内に高熱伝導度を有する接着材に
より接着固定され前記凹部の深さよりも厚みの薄い半導
体集積回路チップと、前記凹部を充填し前記内部配線に
電気接続された前記半導体集積回路チップを埋設する樹
脂とを備え、前記配線基板と前記放熱体とが同じ幅であ
ることを特徴とする半導体集積回路装置。1. A wiring board having an opening at a central portion and provided with internal wiring and embedded with external leads connected to the internal wiring, and a wiring board attached to the wiring board and corresponding to the opening. A radiator made of a high thermal conductor having a concave portion at a position,
A semiconductor integrated circuit chip adhesively fixed in the concave portion of the radiator with an adhesive having a high thermal conductivity and having a thickness smaller than the depth of the concave portion; and the semiconductor integrated circuit filling the concave portion and electrically connected to the internal wiring. A semiconductor integrated circuit device, comprising: a resin for embedding a circuit chip, wherein the wiring board and the radiator have the same width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10060989A JP2845488B2 (en) | 1989-04-20 | 1989-04-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10060989A JP2845488B2 (en) | 1989-04-20 | 1989-04-20 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02278856A JPH02278856A (en) | 1990-11-15 |
| JP2845488B2 true JP2845488B2 (en) | 1999-01-13 |
Family
ID=14278590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10060989A Expired - Lifetime JP2845488B2 (en) | 1989-04-20 | 1989-04-20 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2845488B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06204285A (en) * | 1992-12-28 | 1994-07-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US8706049B2 (en) * | 2008-12-31 | 2014-04-22 | Intel Corporation | Platform integrated phased array transmit/receive module |
| JP5110099B2 (en) * | 2010-02-09 | 2012-12-26 | 株式会社デンソー | Fuel supply device |
| US8869775B2 (en) | 2010-02-09 | 2014-10-28 | Denso Corporation | Fuel supply apparatus |
| CN108581168B (en) * | 2018-05-09 | 2020-06-26 | 西安君信电子科技有限责任公司 | Solid welding process of heat dissipation chip |
| CN112951774B (en) * | 2021-01-26 | 2024-02-09 | 徐州市创泽优电子科技有限公司 | Substrate for packaging electronic device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6194359U (en) * | 1984-11-27 | 1986-06-18 | ||
| JPS6370155U (en) * | 1986-10-24 | 1988-05-11 |
-
1989
- 1989-04-20 JP JP10060989A patent/JP2845488B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02278856A (en) | 1990-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6566164B1 (en) | Exposed copper strap in a semiconductor package | |
| US6657296B2 (en) | Semicondctor package | |
| JPH0923076A (en) | Multiple heat conduction path for intensifying heat/dissipation and integrated circuit package consisting of cap surroundingedge for improving package integrity and reliability | |
| KR970030723A (en) | Solder Ball Array Package with Heat Sink Attached to Bottom | |
| US7508060B2 (en) | Multi-chip semiconductor connector assemblies | |
| JPH0810744B2 (en) | Semiconductor device | |
| JPH0629459A (en) | Semiconductor device and manufacture thereof | |
| JP2000294723A (en) | Stacked semiconductor device and its manufacture | |
| CA2075593A1 (en) | Semiconductor chip module and method for manufacturing the same | |
| JP2845488B2 (en) | Semiconductor integrated circuit device | |
| JP3922809B2 (en) | Semiconductor device | |
| KR880002260A (en) | Thermally Enhanced Large Scale Integrated Circuit Packages and Mounting Integrated Circuit Dies | |
| JP3169578B2 (en) | Substrate for electronic components | |
| JPH09199629A (en) | Semiconductor device | |
| JP3764214B2 (en) | Printed circuit board and electronic apparatus equipped with the same | |
| US20040075166A1 (en) | Semiconductor device with heat-dissipating capability | |
| JP2612455B2 (en) | Substrate for mounting semiconductor elements | |
| JPH07176664A (en) | Semiconductor device and fabrication thereof | |
| JP2501950B2 (en) | Semiconductor device | |
| JP2564645Y2 (en) | Hybrid integrated circuit device having heat-generating components | |
| JP2772986B2 (en) | Semiconductor device | |
| JP3502511B2 (en) | Semiconductor device | |
| JPH06326236A (en) | Resin sealed semiconductor device | |
| JP2626631B2 (en) | Semiconductor device | |
| JP2504262Y2 (en) | Semiconductor module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081030 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091030 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091030 Year of fee payment: 11 |