CN213635955U

CN213635955U - Anti-static chip packaging structure

Info

Publication number: CN213635955U
Application number: CN202022664632.1U
Authority: CN
Inventors: 顾大元; 乔畅君; 韩玲玲; 胡祖敏
Original assignee: Shenzhen Horb Tech Development Co ltd
Current assignee: Shenzhen Horb Tech Development Co ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2021-07-06
Anticipated expiration: 2030-11-18

Abstract

The utility model belongs to the technical field of the chip package, concretely relates to prevent chip package structure of static, including silicon base, shrouding, the upper end fixedly connected with encapsulation platform of silicon base, the inboard bottom of encapsulation platform is provided with the lug, the inside packing of encapsulation platform has bonding glue, the outside cladding of lug has bonding glue, bonding glue's upper end bonds and has the chip, the chip card connects in the inside of encapsulation platform. The utility model discloses an inside at the encapsulation platform sets up the lug, then glue filling bonding for bonding glue and encapsulation platform are laminated more, then connect the chip card on the encapsulation platform, and the lower extreme and the bonding of chip glue the contact, make the more firm of chip mounting, then set up the elasticity strip on the pin, the pin alternates after the through-hole with the bonding wire contact on the chip, the elasticity strip struts the inboard contact with the silicon base this moment, prevent that the pin from droing, also made things convenient for the change when easy to assemble.

Description

Anti-static chip packaging structure

Technical Field

The utility model relates to a chip package technical field specifically is a prevent chip package structure of static.

Background

The chip package is a package for mounting a semiconductor integrated circuit chip, plays a role in placing, fixing, sealing and protecting the chip, and is also a bridge for communicating the internal world of the chip with an external circuit, i.e., contacts on the chip are connected to pins of the package through wires, and the pins are connected with other devices through wires on a printed board. Therefore, the package plays an important role for both the CPU and other LSI integrated circuits.

At present, the existing packaging structure usually adopts siliceous materials, is high-efficient and antistatic, but has the defects of complex structure, difficult installation and poor heat dissipation effect. Therefore, improvements are needed.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a prevent chip packaging structure of static has solved the complicated difficult installation of structure to the not good problem of radiating effect.

In order to achieve the above object, the utility model provides a following technical scheme: an anti-static chip packaging structure comprises a silicon base and a sealing plate, wherein the upper end of the silicon base is fixedly connected with a packaging platform, the bottom of the inner side of the packaging table is provided with a convex block, the interior of the packaging table is filled with adhesive glue, the outside of the lug is coated with bonding glue, the upper end of the bonding glue is bonded with a chip, the chip card is connected with the inside of the packaging table, a bonding wire is welded on the chip, a through hole is arranged on the silicon base, a sealing plug is sleeved inside the through hole, pins are sleeved in the sealing plug in a sliding manner and are in contact with the bonding wires, a clamping groove is formed in the silicon base and above the through hole, the sealing plate is fixedly connected with an elastic sheet, a clamping block is fixedly connected on the elastic sheet, the clamping block is clamped in the clamping groove, the lower extreme fixedly connected with heat conduction piece of shrouding, the lower extreme and the chip contact of heat conduction piece.

Preferably, the pin is fixedly connected with an elastic strip, and the elastic strip is in contact with the inner side of the silicon base.

Preferably, the upper end of the heat conduction block is provided with a heat conduction rod, and the heat conduction rod penetrates through the sealing plate and extends to the outside of the sealing plate.

Preferably, the number of the elastic pieces is two, and the two elastic pieces are symmetrically distributed on the sealing plate.

Preferably, the number of the bumps is five, and the five bumps are uniformly distributed on the packaging table.

Preferably, the number of the through holes is two, and the two through holes are symmetrically distributed on the silicon base.

Compared with the prior art, the beneficial effects of the utility model are as follows:

1. the utility model discloses an inside at the encapsulation platform sets up the lug, then glue filling bonding for bonding glue and encapsulation platform are laminated more, then connect the chip card on the encapsulation platform, and the lower extreme and the bonding of chip glue the contact, make the more firm of chip mounting, then set up the elasticity strip on the pin, the pin alternates after the through-hole with the bonding wire contact on the chip, the elasticity strip struts the inboard contact with the silicon base this moment, prevent that the pin from droing, also made things convenient for the change when easy to assemble.

2. The utility model discloses an add a set of heat radiation structure in the upper end of chip, wherein the heat conduction piece is fixed at the shrouding, is provided with the heat conduction stick on the heat conduction piece in addition, and the heat-conducting plate runs through the shrouding and extends to the outside of shrouding, and the lower extreme of heat conduction piece is direct and the chip contacts, and the heat on the chip can be conducted to the heat conduction stick through the heat conduction piece on, is conducted to the outside by the heat conduction stick again, carries out effectual heat dissipation to the chip, prevents that the heat from concentrating on the.

Drawings

Fig. 1 is a schematic structural view of the present invention;

fig. 2 is an enlarged view of the structure of part a of fig. 1 according to the present invention;

fig. 3 is a front view of the present invention.

In the figure: 1. a silicon base; 2. a packaging stage; 3. a bump; 4. bonding glue; 5. a chip; 6. welding wires; 7. a through hole; 8. a sealing plug; 9. a pin; 10. an elastic strip; 11. a card slot; 12. closing the plate; 13. a spring plate; 14. a clamping block; 15. a heat conducting block; 16. a heat conducting rod.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Examples

Referring to fig. 1-3, an anti-static chip package structure includes a silicon substrate 1 and a sealing plate 12, the silicon substrate 1 is made of silicon material and has an anti-static effect, a package platform 2 is fixedly connected to an upper end of the silicon substrate 1, a bump 3 is disposed at a bottom of an inner side of the package platform 2, an adhesive 4 is filled inside the package platform 2, the bump 3 is covered with the adhesive 4, a chip 5 is adhered to an upper end of the adhesive 4, the chip 5 is clamped inside the package platform 2, a bonding wire 6 is welded to the chip 5, a through hole 7 is disposed on the silicon substrate 1, a sealing plug 8 is sleeved inside the through hole 7, a pin 9 is slidably sleeved inside the sealing plug 8, the pin 9 contacts the bonding wire 6, a clamping groove 11 is disposed on the silicon substrate 1 and above the through hole 7, a spring plate 13 is fixedly connected to the sealing plate 12, a clamping block 14 is fixedly connected to the spring plate 13, and a clamping, the lower end of the sealing plate 12 is fixedly connected with a heat conducting block 15, and the lower end of the heat conducting block 15 is in contact with the chip 5.

Referring to fig. 1, the leads 9 are fixedly connected with elastic strips 10, and the elastic strips 10 are in contact with the inner side of the silicon substrate 1. Through the design of the elastic strip 10, the pins 9 are prevented from falling off accidentally.

Referring to fig. 1 and 3, the upper end of the heat conducting block 15 is provided with a heat conducting rod 16, and the heat conducting rod 16 penetrates through the sealing plate 12 and extends to the outside of the sealing plate 12. The heat on the heat conducting block 15 is removed by the design of the heat conducting rod 16.

Referring to fig. 1 and 3, the number of the elastic sheets 13 is two, and the two elastic sheets 13 are symmetrically distributed on the sealing plate 12. The sealing plate 12 is convenient to mount through the design of the elastic sheets 13.

Referring to fig. 1, the number of the bumps 3 is five, and the five bumps 3 are uniformly distributed on the package stage 2. Through the design of lug 3 for bonding glue 4 and encapsulation platform 2 are laminated more.

Referring to fig. 1, the number of the through holes 7 is two, and the two through holes 7 are symmetrically distributed on the silicon substrate 1. Through the design of through-hole 7, pin 9 is conveniently installed.

The utility model discloses the concrete implementation process as follows: when the packaging platform is used, the packaging platform 2 is filled with the bonding glue 4, the bump 3 on the packaging platform 2 is coated by the bonding glue 4, the bonding glue 4 is attached to the packaging platform 2, the chip 5 is clamped on the packaging platform 2, the lower end of the chip 5 is contacted with the bonding glue 4, the chip 5 is installed more firmly, then the pin 9 is provided with the elastic strip 10, the pin 9 is inserted through the through hole 7 and then is contacted with the bonding wire 6 on the chip 5, the elastic strip 10 is propped open to be contacted with the inner side of the silicon base 1, then the sealing plug 8 is sleeved in the through hole 7 to prevent the pin 9 from falling off, the installation is convenient, the replacement is also convenient, then the sealing plate 12 is covered, the clamping block 14 of the elastic sheet 13 on the sealing plate 12 is clamped in the clamping groove 11 on the silicon base 1, the heat conducting block 15 on the sealing plate 12 is directly contacted with the chip 5, when the chip 5 works normally, the heat on the chip 5 is conducted to, and then is conducted to the outside by the heat conduction rod 16, so that the chip 5 is effectively radiated, and the damage of the chip 5 caused by the concentration of heat on the chip 5 is prevented.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides an prevent chip package structure of static, includes silicon base (1), shrouding (12), its characterized in that: the upper end of the silicon base (1) is fixedly connected with a packaging table (2), a convex block (3) is arranged at the bottom of the inner side of the packaging table (2), bonding glue (4) is filled in the packaging table (2), the bonding glue (4) is coated outside the convex block (3), a chip (5) is bonded at the upper end of the bonding glue (4), the chip (5) is connected in the packaging table (2) in a clamping manner, a welding wire (6) is welded on the chip (5), a through hole (7) is formed in the silicon base (1), a sealing plug (8) is sleeved in the through hole (7), a pin (9) is sleeved in the sealing plug (8) in a sliding manner, the pin (9) is in contact with the welding wire (6), a clamping groove (11) is formed in the silicon base (1) and above the through hole (7), and an elastic sheet (13) is fixedly connected to the sealing plate (12), the elastic sheet (13) is fixedly connected with a clamping block (14), the clamping block (14) is clamped in the clamping groove (11), the lower end of the sealing plate (12) is fixedly connected with a heat conducting block (15), and the lower end of the heat conducting block (15) is in contact with the chip (5).

2. The anti-static chip packaging structure according to claim 1, wherein: and the pins (9) are fixedly connected with elastic strips (10), and the elastic strips (10) are in contact with the inner sides of the silicon bases (1).

3. The anti-static chip packaging structure according to claim 1, wherein: the upper end of the heat conducting block (15) is provided with a heat conducting rod (16), and the heat conducting rod (16) penetrates through the sealing plate (12) and extends to the outside of the sealing plate (12).

4. The anti-static chip packaging structure according to claim 1, wherein: the number of the elastic sheets (13) is two, and the two elastic sheets (13) are symmetrically distributed on the sealing plate (12).

5. The anti-static chip packaging structure according to claim 1, wherein: the number of the bumps (3) is five, and the five bumps (3) are uniformly distributed on the packaging table (2).

6. The anti-static chip packaging structure according to claim 1, wherein: the number of the through holes (7) is two, and the two through holes (7) are symmetrically distributed on the silicon base (1).