CN213401177U - Multi-pin semiconductor device with internal connection structure - Google Patents
Multi-pin semiconductor device with internal connection structure Download PDFInfo
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- CN213401177U CN213401177U CN202022694862.2U CN202022694862U CN213401177U CN 213401177 U CN213401177 U CN 213401177U CN 202022694862 U CN202022694862 U CN 202022694862U CN 213401177 U CN213401177 U CN 213401177U
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- pin
- pad
- chip
- bonding pad
- internal connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a multi-pin semiconductor device with an internal connection structure, which comprises an encapsulation colloid, wherein n circuit units are arranged in the encapsulation colloid; the circuit unit comprises a first inner connecting pad and a second inner connecting pad which are strip-shaped, a first front pin and a first rear pin are fixed at two ends of the bottom of the first inner connecting pad respectively, a second front pin and a second rear pin are fixed at two ends of the bottom of the second inner connecting pad respectively, a first chip located right above the first front pin is fixed on the first inner connecting pad, the first chip is connected with the second inner connecting pad through a first lead, a second chip located right above the second rear pin is fixed on the second inner connecting pad, and the second chip is connected with the first inner connecting pad through a second lead. The utility model discloses the shaping has integrative internal connection pad between the adjacent pin, processing convenient operation, and production efficiency is high, and internal connection pad can effectively strengthen heat dispersion, and can effectively reduce impedance and cut-off voltage.
Description
Technical Field
The utility model relates to a semiconductor device specifically discloses a many pins semiconductor device with inscription structure.
Background
Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, which can be used to generate, control, receive, convert, amplify signals, and perform energy conversion.
The semiconductor processing usually includes welding chips on a frame, connecting each welding point through a wire to form a specific circuit structure, placing the specific circuit structure in a mold for injection molding and packaging to obtain a packaging colloid, and then cutting the colloid to obtain an independent semiconductor device. In the prior art, a plurality of chips are integrated in part of semiconductor devices, as shown in fig. 1, pins are uniformly distributed on two sides of a packaging colloid, the chips are welded on the pins and connected with other pins through wires, in order to realize corresponding circuit functions, a wire structure is also connected between part of adjacent pins, the wires between the adjacent pins need to be welded during processing, the operation is complex, and the electrical performance of the structures is poor and the overall structure is unstable.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a multi-pin semiconductor device with an internal connection structure, which can effectively reduce the number of bonding wires, and has high production efficiency, good heat dissipation performance and low impedance.
In order to solve the prior art problem, the utility model discloses a multi-pin semiconductor device with an internal connection structure, which comprises an encapsulation colloid, wherein n circuit units are arranged in the encapsulation colloid, and n is a positive integer;
the circuit unit comprises a first internal bonding pad and a second internal bonding pad which are strip-shaped, the first internal bonding pad and the second internal bonding pad are mutually parallel and spaced, a first front pin and a first rear pin are respectively fixed at two ends of the bottom of the first internal bonding pad, a second front pin and a second rear pin are respectively fixed at two ends of the bottom of the second internal bonding pad, the first front pin and the second front pin are respectively protruded out of the bottom surface of the same side of the packaging colloid, the first rear pin and the second rear pin are respectively protruded out of the bottom surface of the other side of the packaging colloid, a first chip which is positioned right above the first front pin is fixed on the first internal bonding pad, the first chip is connected with the second internal bonding pad through a first lead, one end of the first lead, which is far away from the first chip, is positioned right above the second front pin, a second chip which is positioned right above the second rear pin is fixed on the second internal bonding pad, and the second chip is connected with the first internal bonding pad through a second lead, one end of the second lead, which is far away from the second chip, is positioned right above the first rear pin.
Furthermore, a first strengthening wing plate is fixed on one side of the first internal connection bonding pad and is positioned on one side, close to the second internal connection bonding pad, of the first chip; and a second strengthening wing plate is fixed on one side of the second internal connection bonding pad, is positioned on one side of the second chip close to the first internal connection bonding pad, and forms a gap between the first strengthening wing plate and the second strengthening wing plate.
Further, a gap is formed between the first reinforcing wing plate and the end portion of the first internal connection pad, and a gap is formed between the second reinforcing wing plate and the end portion of the second internal connection pad.
Further, the first front pin, the first rear pin, the second front pin and the second rear pin are all silver pins.
Furthermore, two third strengthening wing plates are arranged between the first inner bonding pad and the second inner bonding pad which are adjacent in different circuit units, one third strengthening wing plate is fixedly connected with the second inner bonding pad which is positioned below the second chip, and the other third strengthening wing plate is fixedly connected with the first inner bonding pad which is positioned below the first chip.
Further, n is 2 line units.
The utility model has the advantages that: the utility model discloses a many pins semiconductor device with inscription structure, the shaping has integrative inscription pad between the adjacent pin, need not to go on between the pin through the wire welding link to each other, can effectively reduce the bonding wire quantity, processing convenient operation, production efficiency is high, the inscription pad of big face integration can effectively strengthen the heat dispersion of overall structure, and can effectively reduce impedance and cutoff voltage, rated power is high, the electrical property is good; in addition, all parts in the circuit unit are reasonably distributed, the space of the colloid can be effectively packaged, and meanwhile, short circuit can be effectively avoided.
Drawings
Fig. 1 is a schematic view of an internal structure of a semiconductor device in a top view according to the prior art.
Fig. 2 is a schematic perspective view of the present invention.
Fig. 3 is a schematic view of the internal structure of the present invention at a top view angle.
Fig. 4 is a schematic perspective view of the circuit unit of the present invention.
The reference signs are: the package body 10, the circuit unit 20, the first inner bonding pad 30, the first front lead 311, the first rear lead 312, the first chip 32, the first wire 33, the first reinforced wing plate 34, the second inner bonding pad 40, the second front lead 411, the second rear lead 412, the second chip 42, the second wire 43, the second reinforced wing plate 44, and the third reinforced wing plate 50.
Detailed Description
For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Refer to fig. 2 to 4.
The embodiment of the utility model discloses a multi-pin semiconductor device with an internal connection structure, which comprises an encapsulation colloid 10, wherein n circuit units 20 which are arranged side by side and are not in direct contact are arranged in the encapsulation colloid 10, and n is a positive integer;
each line unit 20 satisfies the following condition: the circuit unit 20 includes a first inner bonding pad 30 and a second inner bonding pad 40 which are both strip-shaped, that is, the first inner bonding pad 30 and the second inner bonding pad 40 are both rectangular structures, the first inner bonding pad 30 and the second inner bonding pad 40 are arranged in parallel and at an interval, that is, the first inner bonding pad 30 and the second inner bonding pad 40 are parallel and not contacted with each other, a first front pin 311 and a first rear pin 312 are respectively fixed at the front and rear ends of the bottom of the first inner bonding pad 30, the first front pin 311 and the first rear pin 312 are an integrally formed structure, a second front pin 411 and a second rear pin 412 are respectively fixed at the front and rear ends of the bottom of the second inner bonding pad 40, the second front pin 411 and the second rear pin 412 are integrally formed structures, the first front pin 311 and the second front pin 411 protrude from the bottom surface of the same side of the package body 10, the first rear pin 312 and the second rear pin 412 protrude from the other side of the package body 10, the PCB is convenient to weld and use on the PCB, a first chip 32 positioned right above a first front pin 311 is welded and fixed on a first inner bonding pad 30, one electrode of the first chip 32 is electrically connected with the first inner bonding pad 30, the other electrode of the first chip 32 is connected with a second inner bonding pad 40 through a first lead 33, one end of the first lead 33 far away from the first chip 32 is positioned right above a second front pin 411, a second chip 42 positioned right above a second rear pin 412 is welded and fixed on the second inner bonding pad 40, one electrode of the second chip 42 is electrically connected with the second inner bonding pad 40, the other electrode of the second chip 42 is connected with the first inner bonding pad 30 through a second lead 43, one end of the second lead 43 far away from the second chip 42 is positioned right above the first rear pin 312, the first inner bonding pad 30, the second inner bonding pad 40, the first chip 32, the second chip 32, The first wires 33, the second chip 42 and the second wires 43 are all located in the package of the encapsulant 10.
The utility model discloses a first internal connection pad 30 and second internal connection pad 40 are rectangular shape's big face pad structure, have good heat dispersion and electrical property, and rated power is higher, and the impedance is low, the cut-off voltage is low, and application scope is wide, uses the utility model discloses the structure need not to increase between two front and back pins and weld extra lead wire, can effectively save the processing step, convenient to use, and the internal connection pad structure of integration is more stable firm; the first chip 32 and the second chip 42 are staggered in different spaces, and the first wire 33 and the second wire 43 are also staggered in different spaces, so that the internal space of the encapsulant 10 can be effectively utilized, meanwhile, the first wire 33 and the second wire 43 can be effectively prevented from being in contact with each other and short circuit can be avoided, and the circuit structure of the circuit unit 20 is reliable. The utility model discloses inside is provided with reasonable circuit structure with two or more chips of integration, and the many pins semiconductor device overall structure of formation is reliable and stable, and production efficiency is high.
In the embodiment, the first reinforcing wing plate 34 is fixed on one side of the first internal connection pad 30, the first reinforcing wing plate 34 and the first internal connection pad 30 are in an integrally formed structure, so that the stability of the connection structure between the first internal connection pad 30 and the encapsulant 10 can be effectively improved, and the area of the first internal connection pad 30 can be further increased, so that the electrical performance of the first internal connection pad is improved, the first reinforcing wing plate 34 is located on one side of the first chip 32 close to the second internal connection pad 40, the area of the first internal connection pad 30 can be increased by the first reinforcing wing plate 34, and the welding and installation of the first chip 32 can be facilitated; a second reinforcing wing plate 44 is fixed to one side of the second internal connection pad 40, the second reinforcing wing plate 44 and the second internal connection pad 40 are integrally formed, the stability of the connection structure between the second internal connection pad 40 and the package colloid 10 can be effectively improved, the area of the second internal connection pad 40 can be further increased, thereby improving the electrical performance thereof, and the second reinforcing wing 44 is positioned at a side of the second chip 42 adjacent to the first inner contact pad 30, the second reinforcing wing 44 can increase the area of the second inner contact pad 40 at that region, the solder mounting of the second chip 42 is facilitated, the first reinforcing wing plate 34 and the second reinforcing wing plate 44 are spaced apart from each other, that is, the first reinforcing wing plate 34 and the second reinforcing wing plate 44 are respectively located at the front end and the rear end of the gap formed by the first inner land 30 and the second inner land 40, so that the space can be effectively saved while the structural stability is enhanced and the electrical performance is improved.
Based on the above embodiment, a distance is formed between the first reinforced wing plate 34 and the end of the first internal connection pad 30, and a distance is formed between the second reinforced wing plate 44 and the end of the second internal connection pad 40, so that after the lead frame is subjected to injection molding and packaging, when the lead frame is cut, the cutter is not obstructed by the retracted reinforced wing plate, the resistance received by the cutter during cutting can be effectively reduced, the cutting action stability is improved, and meanwhile, the stress formed inside the semiconductor device during cutting can be effectively reduced, so that the probability of crack occurrence is reduced.
In this embodiment, the first front lead 311, the first rear lead 312, the second front lead 411 and the second rear lead 412 are all sheet-shaped silver leads, and the silver leads have good electrical welding performance, and meanwhile, the impedance can be further reduced, and the electrical performance of the whole structure can be improved.
In this embodiment, two third strengthening wing plates 50 that are not in contact with each other are disposed between the adjacent first inner bonding pad 30 and the second inner bonding pad 40 in different circuit units 20, one of the third strengthening wing plates 50 is fixedly connected to the second inner bonding pad 40 located below the second chip 42, and the other third strengthening wing plate 50 is fixedly connected to the first inner bonding pad 30 located below the first chip 32, so that the structural firmness between the circuit units 20 and the encapsulant 10 can be further improved, and meanwhile, a certain space can be saved.
Based on the above embodiment, the line units 20 are provided with n equal to 2, the respective inner pads in the two line units 20 are parallel to each other, and preferably, the chips are diode chips, and by this structure, two sets of internal line structures each integrating two diode chips can be formed, and the semiconductor device of DFN2010-8L can be supported.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (6)
1. The multi-pin semiconductor device with the internal connection structure is characterized by comprising an encapsulation colloid (10), wherein n circuit units (20) are arranged in the encapsulation colloid (10), and n is a positive integer;
the circuit unit (20) comprises a first inner bonding pad (30) and a second inner bonding pad (40) which are both strip-shaped, the first inner bonding pad (30) and the second inner bonding pad (40) are spaced in parallel, a first front pin (311) and a first rear pin (312) are fixed at two ends of the bottom of the first inner bonding pad (30) respectively, a second front pin (411) and a second rear pin (412) are fixed at two ends of the bottom of the second inner bonding pad (40) respectively, the first front pin (311) and the second front pin (411) protrude from the bottom surface of the same side of the packaging colloid (10), the first rear pin (312) and the second rear pin (412) protrude from the bottom surface of the other side of the packaging colloid (10), and a first chip (32) located right above the first front pin (311) is fixed on the first inner bonding pad (30), go up through first wire (33) on first chip (32) with second internal bond pad (40) are connected, first wire (33) are kept away from the one end of first chip (32) is located directly over pin (411) before the second, be fixed with on second internal bond pad (40) and be located second chip (42) directly over pin (412) behind the second, on second chip (42) through second wire (43) with first internal bond pad (30) are connected, second wire (43) are kept away from one end of second chip (42) is located directly over pin (312) behind the first.
2. A multi-pin semiconductor device with an interconnection structure according to claim 1, wherein a first reinforcing wing plate (34) is fixed to one side of the first interconnection pad (30), and the first reinforcing wing plate (34) is located on one side of the first chip (32) close to the second interconnection pad (40); a second strengthening wing plate (44) is fixed on one side of the second internal connecting pad (40), the second strengthening wing plate (44) is positioned on one side, close to the first internal connecting pad (30), of the second chip (42), and a gap is formed between the first strengthening wing plate (34) and the second strengthening wing plate (44).
3. A multi-pin semiconductor device having an internal connection structure according to claim 2, wherein the first reinforcement wing (34) is spaced from an end of the first internal connection pad (30), and the second reinforcement wing (44) is spaced from an end of the second internal connection pad (40).
4. The multi-pin semiconductor device with an interconnection structure according to claim 1, wherein the first front pin (311), the first rear pin (312), the second front pin (411), and the second rear pin (412) are all silver pins.
5. A multi-pin semiconductor device with an interconnection structure according to claim 1, wherein two third reinforcement wings (50) are provided between the adjacent first interconnection pad (30) and the second interconnection pad (40) in different ones of the line units (20), wherein one of the third reinforcement wings (50) is fixedly connected to the second interconnection pad (40) under the second chip (42), and the other third reinforcement wing (50) is fixedly connected to the first interconnection pad (30) under the first chip (32).
6. The multi-pin semiconductor device with an interconnection structure according to claim 5, wherein the number of the line units (20) is 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022694862.2U CN213401177U (en) | 2020-11-18 | 2020-11-18 | Multi-pin semiconductor device with internal connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022694862.2U CN213401177U (en) | 2020-11-18 | 2020-11-18 | Multi-pin semiconductor device with internal connection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213401177U true CN213401177U (en) | 2021-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022694862.2U Active CN213401177U (en) | 2020-11-18 | 2020-11-18 | Multi-pin semiconductor device with internal connection structure |
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| CN (1) | CN213401177U (en) |
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- 2020-11-18 CN CN202022694862.2U patent/CN213401177U/en active Active
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