CN212990690U

CN212990690U - Double-serial-port bus Nand type memory

Info

Publication number: CN212990690U
Application number: CN202021809673.9U
Authority: CN
Inventors: 郑伟; 黄欢; 施冠良; 朱纯莹
Original assignee: Heyangtek Cooperation Ltd
Current assignee: Jiangsu Yangheyang Microelectronics Technology Co ltd
Priority date: 2020-08-26
Filing date: 2020-08-26
Publication date: 2021-04-16
Anticipated expiration: 2030-08-26

Abstract

The utility model discloses a dual serial port bus Nand type memory, which comprises a data memory, a clock source, an input register and an output register; the input register and the output register are both electrically connected with the data memory, the input register and the output register are both electrically connected with the clock source, and the output register is controlled by the data line switching signal CS to output signals on an external SI signal line or an external SO signal line; the input end of the input register is electrically connected with an external SI signal line; when CS is 0, outputting a signal on an external SO signal line, and inputting a signal on an external SI signal line to realize an SPI bus serial port; when CS is 1, the output signal and the input signal are both on the external SI signal line, and the I2C bus serial port is realized.

Description

Double-serial-port bus Nand type memory

Technical Field

The utility model belongs to the technical field of nonvolatile memory, concretely relates to two serial ports bus Nand type memory.

Background

The large-capacity Nand type memory usually adopts a parallel port or an SPI bus serial port to receive or send information, the small-capacity E2PROM adopts an I2C bus to receive or send information, the SPI bus is a three-wire system, the I2C bus is a two-wire system, both the SPI bus and the SPI bus have independent clock signal lines, two data lines of the SPI are input and output respectively, and a data line of the I2C can be input and output. The I2C bus currently does not have a large capacity of memory.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: for filling the blank that the I2C bus does not have mass storage, the utility model provides a two serial ports bus Nand type memory can use SPI bus or I2C bus to communicate wantonly, makes things convenient for the customer to use.

The technical scheme is as follows: a dual serial port bus Nand type memory comprises a data memory, a clock source, an input register and an output register; the input register and the output register are both electrically connected with the data memory, the input register and the output register are both electrically connected with the clock source, and the output register is controlled by the data line switching signal CS to output signals on an external SI signal line or an external SO signal line; the input end of the input register is electrically connected with an external SI signal line;

when CS is 0, outputting a signal on an external SO signal line, and inputting a signal on an external SI signal line to realize an SPI bus serial port;

when CS is 1, the output signal and the input signal are both on the external SI signal line, and the I2C bus serial port is realized.

Further, the input register is an input shift register.

Further, the output register is an output shift register.

Further, the output register receives a data line switching signal CS through the flip-flop 1 and the flip-flop 2, and outputs a signal on an external SI signal line or an external SO signal line according to the received data line switching signal CS.

Further, the output trigger signals of the flip-flop 1 and the flip-flop 2 are opposite.

Further, the data line switching signal CS is used as an output trigger signal of the flip-flop 1, and the data line switching signal CS is used as an output trigger signal of the flip-flop 2 after passing through the not gate.

Has the advantages that: compared with the prior art, the utility model, have following advantage:

(1) the utility model can automatically switch two usable buses through different states of the CS signal, and the client can use the bus without hindrance only by setting the corresponding level of the required bus;

(2) the utility model automatically switches the data lines corresponding to the output signals by the two triggers with the same input signals and opposite enable signals, thereby realizing the compatibility of the SPI and the I2C bus;

(3) the utility model discloses realize a core double bus, the customer can the bus that the arbitrary selection is suitable for, does not need two kinds of chips.

Drawings

Fig. 1 is a schematic diagram of the Nand memory architecture of the present invention.

Detailed Description

The technical solution of the present invention will be further explained with reference to the accompanying drawings and embodiments.

The NAND-type memory with dual serial buses as shown in fig. 1 includes a data memory 2, a clock source 1, an input shift register 3 and an output shift register 4; the input shift register 3 and the output shift register 4 are both electrically connected with the data memory 2, the input shift register 3 and the output shift register 4 are both electrically connected with the clock source 1, and the output register 4 is controlled by the data line switching signal CS to output signals on an external SI signal line or an external SO signal line; the input end of the input register 3 is electrically connected with an external SI signal line; namely, the SPI corresponding signal line is CLK, SI and SO; I2C corresponds to signal lines CLK, SI.

In this embodiment, the data lines corresponding to the output signals are automatically switched by the flip-flops, in which the two input signals are the same and the enabling signals are opposite, through different states of the data line switching signal CS, so that the compatibility between the SPI and the I2C bus is realized. The customer only needs to set up the corresponding level that needs the bus, can unimpededly use, specifically is: when CS is 0 (low level), the data line switching signal CS is used as an output trigger signal of the flip-flop 26 after passing through the not gate 7, and meets the condition of being output by the flip-flop 2, and the output signal is on an external SO signal line, and the input signal is on an external SI signal line, SO as to implement an SPI bus serial port; when CS is 1 (high level), the condition of output of the flip-flop 1 is met, and both the output signal and the input signal are on the external SI signal line, so that the I2C bus serial port is realized.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents of the embodiments of the invention may be made without departing from the spirit and scope of the invention, which should be construed as falling within the scope of the claims of the invention.

Claims

1. A dual serial port bus Nand type memory is characterized in that: the device comprises a data memory, a clock source, an input register and an output register; the input register and the output register are both electrically connected with the data memory, the input register and the output register are both electrically connected with the clock source, and the output register is controlled by the data line switching signal CS to output signals on an external SI signal line or an external SO signal line; the input end of the input register is electrically connected with an external SI signal line;

2. The dual serial bus Nand type memory of claim 1, wherein: the input register is an input shift register.

3. The dual serial bus Nand type memory of claim 1, wherein: the output register is an output shift register.

4. The dual serial bus Nand type memory of claim 1, wherein: the output register receives a data line switching signal CS through the flip-flop 1 and the flip-flop 2, and outputs a signal on an external SI signal line or an external SO signal line according to the received data line switching signal CS.

5. The dual serial bus Nand type memory of claim 4, wherein: the output trigger signals of the flip-flop 1 and the flip-flop 2 are opposite.

6. The dual serial bus Nand type memory of claim 5, wherein: the data line switching signal CS is used as an output trigger signal of the flip-flop 1, and the data line switching signal CS is used as an output trigger signal of the flip-flop 2 after passing through the not gate.