CN212572075U

CN212572075U - Single-wafer battery protection circuit, battery charging and discharging circuit and portable electronic equipment

Info

Publication number: CN212572075U
Application number: CN201921874738.5U
Authority: CN
Inventors: 谭健; 蒋锦茂
Original assignee: Suzhou Saixin Electronic Technology Co ltd
Current assignee: Suzhou Saixin Electronic Technology Co ltd
Priority date: 2018-11-06
Filing date: 2019-11-01
Publication date: 2021-02-19
Anticipated expiration: 2029-11-01
Also published as: CN209250230U; CN110854832A; CN212572076U; CN212543359U; CN110854831A; CN109449891A

Abstract

The utility model provides a single wafer battery protection circuit, charge-discharge circuit and portable electronic equipment. The single-wafer battery protection circuit includes: the device comprises a basic protection circuit, a clamp circuit, a grid substrate control circuit, an over-temperature protection circuit and a charge and discharge control MOS (metal oxide semiconductor) tube; one end of a source electrode and one end of a drain electrode of the charge and discharge control MOS tube are connected to the cathode of the battery, and the other end of the charge and discharge control MOS tube is connected to the cathode of the charger or the load; the grid and the substrate are respectively connected to a grid substrate control circuit; the over-temperature protection circuit is respectively coupled with the basic protection circuit and the grid substrate control circuit and is used for detecting the temperature of a chip integrated by the single-wafer battery protection circuit and controlling and conducting the grid substrate control circuit together with the basic protection circuit; the clamping circuit is connected with the grid substrate control circuit and used for clamping the power supply voltage of the grid substrate control circuit. The utility model discloses can make battery protection circuit avoid the destruction of peak voltage and direct current high voltage, prolong charge-discharge circuit's life.

Description

Single-wafer battery protection circuit, battery charging and discharging circuit and portable electronic equipment

Technical Field

The utility model relates to a battery charge-discharge technical field indicates a single crystal circle battery protection circuit, battery charge-discharge circuit and portable electronic equipment especially.

Background

With the increasing functions of mobile terminals in recent years, the performance of mobile terminals is also rapidly increasing, which also puts greater demands on the battery of the terminal. Some application batteries need to be made very small, some application batteries need to be made very low in cost, and the traditional battery protection scheme usually occupies a large area and is very high in cost, so that the traditional battery protection scheme is not suitable for new market requirements.

Conventional battery protection schemes are achieved by discrete devices. A control circuit chip and a chip including two N-type power MOS transistors are required. The control circuit chip controls the grid voltage of the two power MOS tubes to realize the charge and discharge control of the battery. The control circuit chip is made by CMOS process, and the power MOS chip is usually made by a vertical DMOS or UMOS tube. Since CMOS and DMOS/UMOS are two completely different processes, the control circuit chip and the two power MOS chips are usually from two different vendors, being two separate chips. In addition, the charge and discharge peripheral circuit of this separate device scheme requires two resistors and one capacitor.

In order to reduce the area of the above-mentioned solution for protecting the separated device battery and reduce the cost of the solution, in chinese patent CN103474967A, my self proposed a single-wafer battery protection circuit and a charging and discharging circuit. The single-wafer battery protection circuit integrates a control circuit chip, two power MOS chips and a peripheral resistor on a semiconductor substrate in the traditional scheme, and a peripheral charging and discharging circuit only needs one resistor and one capacitor. According to the single-wafer battery protection scheme, a control circuit chip and two power MOS (metal oxide semiconductor) chips are integrated on one semiconductor substrate, and further, two power MOS structures in the traditional scheme are combined into one power MOS so as to further reduce the scheme area and reduce the scheme cost.

Currently, in order to minimize the circuit area and the cost, a 5v cmos process is usually adopted for implementation. And the breakdown voltage of the MOS tube in the 5V CMOS process is between 8V and 12V. Since the battery protection circuit may generate a peak voltage of up to 16V and a dc high voltage during charging and discharging and production testing, the single-wafer battery protection circuit manufactured by the 5V CMOS process may be broken down by the peak voltage or the dc high voltage to cause damage to the single-wafer battery protection circuit.

An intuitive solution is to increase the withstand voltage of the protection circuit of the single-wafer battery by using a semiconductor process with higher breakdown voltage, so that the protection circuit can bear 16V peak voltage and dc high voltage, but this increases the number of process layers and greatly increases the occupied area of the semiconductor device on a chip, thereby greatly increasing the cost of the protection circuit.

In view of the above, the present invention provides a single-wafer battery protection circuit, a battery charging/discharging circuit and a portable electronic device, so as to solve the problem that the single-wafer battery protection circuit is damaged by a dc high voltage and a peak voltage.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a single crystal circle battery protection circuit, battery charge and discharge circuit and portable electronic equipment, when battery production test process and charge and discharge used, can make single crystal circle battery protection circuit avoid the damage of direct current high voltage and peak voltage, the life of extension charge and discharge circuit and battery.

The utility model provides a technical scheme as follows:

the utility model provides a single wafer battery protection circuit, include: the device comprises a basic protection circuit, a clamp circuit, a grid substrate control circuit, an over-temperature protection circuit and a charge and discharge control MOS (metal oxide semiconductor) tube;

one end of a source electrode and one end of a drain electrode of the charge and discharge control MOS tube are connected to the negative electrode of the battery, and the other end of the source electrode and the other end of the drain electrode of the charge and discharge control MOS tube are connected to the negative electrode or the load of the charger; the grid and the substrate of the charge and discharge control MOS tube are respectively connected to the grid substrate control circuit;

the over-temperature protection circuit is respectively coupled with the basic protection circuit and the grid substrate control circuit and is used for detecting the temperature of a chip integrated by the single-wafer battery protection circuit and controlling and conducting the grid substrate control circuit together with the basic protection circuit;

the clamping circuit is connected with the grid substrate control circuit and is used for clamping the power supply voltage of the grid substrate control circuit.

The battery protection circuit in the scheme relates to a great number of semiconductor devices, and can be damaged by peak voltage or direct current high voltage in the battery production test process and charging and discharging use. For example, the breakdown voltage of a 5VCMOS process MOS transistor is between 8V and 12V, and if the peak voltage generated during the production test process and the charging and discharging use exceeds the breakdown voltage, the MOS transistor is damaged. The general intuitive solution is to increase the withstand voltage of the MOS transistor, which increases the number of process layers, increases the area of the MOS transistor on the chip, and increases the cost of the chip. This scheme has added the clamp circuit in order to protect the device not damaged by peak voltage or direct current high voltage under the prerequisite of assurance cost and chip area, with voltage clamp system in certain within range, even if in production test process and when charge-discharge uses peak voltage or direct current high voltage, also can be by clamp circuit with voltage clamp system in safe voltage range, guarantee that protection circuit is not damaged.

In the production test process of the battery protection circuit, the battery protection chip and the resistor and the capacitor are made into a battery protection board, and then the battery protection board and the battery core are connected together to form the battery with the protection function. Test equipment such as a protection board tester, a comprehensive tester, a capacity grading cabinet and the like can be frequently used in the production test process of the battery. The protection shield tester is used for detecting whether the protection shield is qualified, the comprehensive tester is used for detecting whether the battery with the protection function is qualified, and the capacity grading cabinet is used for detecting the capacity of the battery with the protection function. These testing devices often generate a peak voltage or a dc high voltage of up to 16V during the testing process, and therefore, the conventional battery protection scheme needs to make the breakdown voltage of the charging control MOS transistor Mc and the discharging control MOS transistor Md be more than 16V to prevent the battery with the protection function from being broken down by the peak voltage or the dc high voltage of 16V during the production testing process.

Theoretically, the single-wafer battery protection circuit needs to simultaneously make the breakdown voltage of the source and the drain of the charge-discharge control MOS transistor more than 16V, so as to ensure that the battery with the protection function is not broken down by the peak voltage or the direct-current high voltage of 16V generated by the test equipment in the production test process. However, the charge and discharge control MOS transistor has a breakdown voltage of 16V or more, which results in high cost.

Adopt the utility model discloses a clamp circuit, the withstand voltage of charge-discharge control MOS pipe only needs 12V, also is the breakdown voltage of traditional 5V CMOS technology exactly, can prevent to take protect function's battery not by 16V's peak voltage or direct current high voltage breakdown in the production test process and when charge-discharge uses.

The utility model also provides a battery charging circuit, including foretell single wafer battery protection circuit, charger, battery and RC filter circuit, wherein:

one end of the first resistor is connected with a power supply voltage end of the basic protection circuit, and the other end of the first resistor is connected with the anode of the battery;

one end of the first capacitor is connected with a power supply voltage end of the basic protection circuit, and the other end of the first capacitor is connected with the negative electrode of the battery;

and the positive electrode of the charger is connected with the positive electrode of the battery to provide charging voltage for the battery.

The utility model also provides a battery discharge circuit, including foretell single wafer battery protection circuit, RC filter circuit, battery and load, wherein:

the positive pole of battery with the positive pole of load is connected, for the load provides the power, the negative pole of load through charge-discharge control MOS pipe with the negative pole of battery is connected.

The application also provides a portable electronic device which comprises the single wafer and the single wafer battery protection circuit. The portable electronic device may be a device having a lithium battery, such as a mobile phone, a toy, a mobile power supply, an electronic cigarette, a bluetooth headset (TWS), and the like.

Through the utility model provides a pair of single crystal circle battery protection circuit, battery charge and discharge circuit and portable electronic equipment can bring following at least one beneficial effect:

the utility model discloses in, utilize the clamp circuit, with the voltage clamp system between grid substrate control circuit's supply voltage GVDD and VSS end at predetermineeing the within range. The voltage resistance of the battery protection circuit chip in the production test process and in the charging and discharging use process is improved, and the damage of devices in the battery protection circuit is prevented. The over-temperature protection circuit is used for detecting the temperature of a chip integrated by the single-wafer battery protection circuit and controlling the conducting grid substrate control circuit together with the basic protection circuit.

Drawings

The above features, technical features, advantages and implementations of a protection circuit for a single-wafer battery and a charging/discharging circuit for improving a spike-resistant capability will be described in detail in the following description of preferred embodiments with reference to the accompanying drawings.

Fig. 1 is a structural view of a charging and discharging circuit of a conventional discrete device battery protection circuit;

FIG. 2 is a schematic diagram of a conventional charge and discharge circuit for protecting a single-wafer battery;

fig. 3 is a circuit diagram of a gate substrate control circuit in a prior art single wafer battery protection scheme;

fig. 4 is a diagram of an embodiment of a single-wafer battery protection circuit and a charging/discharging circuit structure for improving the anti-peak voltage capability of the present invention;

FIG. 5 is a block diagram of the primary protection circuit of FIG. 4;

FIG. 6 is a circuit diagram of the over-temperature protection circuit of FIG. 4;

FIG. 7 is a circuit diagram of the gate substrate control circuit of FIG. 4;

FIG. 8 is another circuit diagram of the gate substrate control circuit of FIG. 4;

fig. 9 is a circuit diagram of a clamping circuit according to an embodiment of the present invention;

fig. 10 is another circuit diagram of a clamping circuit in an embodiment of the invention;

fig. 11 is another circuit diagram of a clamping circuit in an embodiment of the invention;

fig. 12 is another circuit diagram of a clamp circuit according to an embodiment of the invention.

Detailed Description

In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.

For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".

Fig. 1 is a charge and discharge circuit of a conventional discrete device battery protection scheme. The control circuit A controls the grid voltage of the two power MOS tubes (Mc and Md) to realize the charge and discharge control of the battery. The control circuit a is made by CMOS process, and the power MOS transistors (Mc and Md) are usually made by DMOS or UMOS transistors with a vertical structure. Since CMOS and DMOS/UMOS are two completely different processes, the control circuit a and the two power MOS transistors (Mc and Md) are usually from two different suppliers, being two separate chips, the peripheral circuit requires two resistors R0 and Rvm and one capacitor C0.

Fig. 2 is an internal block diagram and a charging/discharging circuit of a battery protection circuit in the single-wafer battery protection scheme. When the battery protection circuit enters the overcharge voltage protection, the charge overcurrent protection or the charge overtemperature protection, the charging path of the battery protection circuit is closed, and the voltage of the charger is completely provided by the external charging circuit. The basic protection circuit, the over-temperature protection circuit, the logic control unit I12 and the logic control unit I13 in the battery protection circuit are powered by a battery, no high voltage exists, and the circuit cannot be broken by the high voltage. However, the supply voltage of the gate substrate control circuit during the charging protection is the charger voltage, and during the production test and the charger connection process, the voltage may reach a high voltage of 16V, which may damage the gate substrate control circuit and the charge and discharge control MOS transistor M0.

Fig. 3 is a circuit diagram of a gate substrate control circuit in a prior art single wafer battery protection scheme.

Referring to fig. 3, the substrate control circuit including the gate control circuit outputting VGATE and the substrate control circuit outputting VSUB has a low level of the VOD voltage, the VOC voltage, and the VCHOC1 voltage inputted from the gate control circuit, which are the VGND voltage and need to be converted to the VSS voltage, because the low level of the VSS voltage and the VGND voltage of the gate control circuit are not identical potentials. The VOD voltage, the VOC voltage, and the VCHOC1 voltage all require a level shift circuit, and the level shift circuit of the VOD voltage is described as an example.

The MOS tubes M7, M8, M9 and M10 and the logic control unit I6 complete low level conversion of the VOD voltage. When the VOD voltage is at a high level VDD, the transistor M7 is turned off, the transistor M8 is turned on, and the VODP voltage is at a high level VDD; when the VOD voltage is at the low level VGND, the transistor M7 is turned on, the transistor M8 is turned off, and the VODP voltage is at the low level VSS, completing the conversion from the VGND level to the VSS level. Similarly, the VOC voltage is converted into the VOCP voltage, the VCHOC1 voltage is converted into the VCHOC1P voltage, and the VCHOC1N voltage. When both the VODP voltage and the VOCP voltage are at a high level, the output of the VGATE end is at a high level VDD, and when one of the VODP voltage and the VOCP voltage is at a low level VSS, the output of the VGATE end is at a low level VSS. When the VOCP is at a high level, VGOC is at a low level, VGOCB is at a high level, MOS transistor M1 is turned on, MOS transistor M2 is turned off, and the output VSUB voltage is equal to the VGND voltage; when the voltage of the VOCP is low, VGOC is high, VGOCB is low, the MOS transistor M1 is turned off, the MOS transistor M2 is turned on, and the output voltage VSUB is equal to the voltage VM. When the voltage of VCHOC1 is high, the voltage of VCHOC1P is high, the voltage of VCHOC1N is low, MOS tube M19 is turned on, MOS tube M20 is turned off, and the voltage of VSS is equal to the voltage of VGND; when the voltage of VCHOC1 is low, the voltage of VCHOC1P is low, the voltage of VCHOC1N is high, MOS transistor M19 is turned off, MOS transistor M20 is turned on, and VSS voltage is equal to VM voltage.

In the above description, when the voltage of VCHOC1P is low, VSS voltage is equal to VM voltage, and the voltage difference between VDD voltage and VSS voltage is the voltage difference between VDD voltage and VM voltage, the voltage between VDD and VM may generate a peak voltage or a dc voltage as high as 16V during the production test process and charging/discharging operation, and the breakdown voltage of the MOS transistor in the 5V CMOS process is between 8V and 12V, which is lower than the generated peak voltage or dc voltage, and the conventional gate substrate control circuit may be damaged or broken down.

Based on above-mentioned analysis conclusion, the utility model provides a new battery protection circuit. Fig. 4 is a structural diagram of a single-wafer battery protection circuit and a charging/discharging circuit according to an embodiment of the present invention. Fig. 5 is a block diagram of the basic protection circuit in fig. 4. Fig. 6 is a circuit diagram of the over-temperature protection circuit in fig. 4. Fig. 7 is a circuit diagram of a gate substrate control circuit in fig. 4, and fig. 8 is another circuit diagram of the gate substrate control circuit in fig. 4. As shown in fig. 7 and 8, the gate substrate control circuit includes a gate control portion and a substrate control portion, and the gate control portion and the substrate control portion have a common circuit. Referring to fig. 4 to 7, the clamping circuit is added and the gate substrate control circuit is improved relative to the battery protection circuit of fig. 2 and the gate substrate control circuit of fig. 3. In fig. 4, when the battery protection circuit enters the overcharge voltage protection, the charge overcurrent protection or the charge overtemperature protection, the charge path of the battery protection circuit is closed, and the voltage of the charger is completely provided by the external charge circuit. Referring to fig. 7, the positive power supply terminal of the improved gate substrate control circuit is the output voltage GVDD of the clamp circuit, and when the battery protection circuit enters the overcharge voltage protection, the charge overcurrent protection, or the charge overtemperature protection, the voltage of the negative power supply terminal VSS is VM, and in addition, the voltage of the negative power supply terminal VSS is VGND. The power supply voltage of the grid substrate control circuit is the voltage between GVDD and VM or the voltage between GVDD and VGND, the power supply voltage is clamped and is lower than the breakdown voltage of all MOS tubes in the grid substrate control circuit, and the grid substrate control circuit cannot be damaged.

Referring to fig. 4, the battery charging and discharging circuit 2 includes a battery, an RC filter circuit 3, a single-wafer battery protection circuit 1, a charger, and a load, and the battery is connected in parallel with the RC filter circuit 3, the charger, and the load; the single-wafer battery protection circuit 1, the charger, the battery and the RC filter circuit 3 form a battery charging circuit; the single-wafer battery protection circuit 1, the RC filter circuit 3, the battery and the load form a battery discharge circuit.

The battery charging circuit comprises a single-wafer battery protection circuit 1, a charger, a battery and an RC filter circuit 3, wherein: one end of a first resistor R0 in the RC filter circuit 3 is connected with the supply voltage VDD end of the basic protection circuit 10, and the other end of the first resistor R0 is connected with the anode of the battery; one end of a first capacitor C0 in the RC filter circuit 3 is connected with the supply voltage VDD end of the basic protection circuit 10, and the other end of the first capacitor C0 is connected with the negative electrode of the battery; the positive pole of the charger is connected with the positive pole of the battery when charging, and provides charging voltage for the battery, and the negative pole of the charger is connected with the negative pole of the battery through a charging and discharging control MOS tube M0.

The battery discharge circuit comprises a single-wafer battery protection circuit 1, an RC filter circuit 3, a battery and a load, wherein: one end of a first resistor R0 in the RC filter circuit 3 is connected with the supply voltage VDD end of the basic protection circuit 10, and the other end of the first resistor R0 is connected with the anode of the battery; one end of a first capacitor C0 in the RC filter circuit 3 is connected with the supply voltage VDD end of the basic protection circuit 10, and the other end of the first capacitor C0 is connected with the negative electrode of the battery; the positive pole of the battery is connected with one end of the load to provide power for the load, and the negative pole of the battery is connected with the other end of the load through a charge-discharge control MOS transistor M0.

The single-wafer battery protection circuit 1 includes: the protection circuit comprises a basic protection circuit 10, a clamp voltage circuit 11, a grid substrate control circuit 12, an over-temperature protection circuit 13, a first logic control unit I12, a second logic control unit I13 and a charge-discharge control MOS tube M0; the supply voltage VDD input terminal of the basic protection circuit 10 is connected between the first resistor R0 and the first capacitor C0; the output terminal of the basic protection circuit 10 is coupled to the gate substrate control circuit 12. The input end of the over-temperature protection circuit 13 is connected with the basic protection circuit 10; the output end of the basic protection circuit 10 and the output end of the over-temperature protection circuit 13 are respectively coupled to the gate substrate control circuit 12 through a first logic control unit I12 and a second logic control unit I13; the clamp circuit 11 is coupled to a supply voltage VDD, and the clamp circuit 11 is coupled to the gate substrate control circuit 12. One end of a source electrode and one end of a drain electrode of the charge and discharge control MOS tube M0 are connected to the negative electrode of the battery, the other end of the source electrode and the other end of the drain electrode of the charge and discharge control MOS tube M0 are connected to the negative electrode of the charger or the load, for example, the source electrode of the charge and discharge control MOS tube M0 is connected to the negative electrode of the charger, and the drain electrode of the charge and discharge control MOS tube M0 is connected; the grid and the substrate of the charging and discharging control MOS tube M0 are respectively connected to the grid substrate control circuit 12; the source of the charge and discharge control MOS transistor M0 is connected to the basic protection circuit 10 and the gate substrate control circuit 12, and the drain of the charge and discharge control MOS transistor M0 is connected to the basic protection circuit 10 and the gate substrate control circuit 12.

In the single-wafer battery protection circuit 1 of the present embodiment, the basic protection circuit 10 detects the charging/discharging of the battery, and transmits a control signal to the gate substrate control circuit 12, so that the gate substrate control circuit 12 controls the conduction of the charging/discharging control MOS transistor M0 according to the control signal, thereby controlling the charging/discharging of the battery. The single-wafer battery protection circuit 1 detects the temperature of a chip integrated by the battery protection circuit through the over-temperature protection circuit 13, and the over-temperature protection circuit 13 and the basic protection circuit 10 jointly control the conduction of the grid substrate control circuit 12. The single-wafer battery protection circuit 1 clamps the power supply voltage of the grid substrate control circuit 12 through the clamping circuit 11, and the single-wafer battery protection circuit 1 is guaranteed not to be damaged.

Fig. 9 is a circuit diagram of the clamp circuit 11 according to the embodiment of the present application. The clamp circuit 11 comprises a divider resistor R5 and N Zener tubes (zener) which are connected in series in a unidirectional manner, wherein N is more than or equal to 1; one end of the voltage dividing resistor R5 receives the supply voltage VDD, the other end of the voltage dividing resistor R5 connects the cathodes of the N unidirectional series connected zener diodes (zener) and the input terminal GVDD of the gate substrate control circuit 12, and the anodes of the N unidirectional series connected zener diodes (zener) are coupled to the input terminal VSS of the gate substrate control circuit 12.

The principle that the clamp circuit 11 of the present embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within a predetermined range is that: the PN junction of the Zener tube (Zener) has extremely low resistance in a reverse breakdown state, so that when the Zener tube (Zener) is conducted, the voltage between the input voltage GVDD and VSS is equal to the breakdown voltage of the Zener tube (Zener); when the zener (zener) is non-conductive, the input voltage GVDD is almost equal to the supply voltage VDD.

When the voltage between VDD and VSS is lower than the turn-on voltage of Zener, the input voltage GVDD is equal to the supply voltage VDD; when the voltage between VDD and VSS is higher than the turn-on voltage of the zener, the highest output voltage between input voltages GVDD and VSS is the zener voltage. The on-state voltage of a Zener tube (Zener) in a general integrated circuit is between 5.5V and 6.5V, if the voltage between VDD and VSS is continuously increased, one or more Zener tubes (Zener) are connected in series for clamping, the voltage of the Zener tube (Zener) is stabilized at the on-state voltage of the Zener tube (Zener), the rest voltage is reduced on a divider resistor R5, the resistance value of the divider resistor R5 is more than or equal to 0, and tens of volts are reduced on the divider resistor R5 without problems; the withstand voltage between the supply voltages VDD and VSS is therefore not compromised by the clamp circuit 11 up to a few tens of volts. VSS is connected to the low potential of the gate substrate circuit 12. The voltage between VDD and VSS is clamped at one or more zener (zener) voltage values. The power supply voltage of the gate substrate control circuit 12 is a voltage between GVDD and VSS, and the maximum value is the turn-on voltage of the zener (zener). Is lower than the breakdown voltage of the MOS transistor M0 by between 8V and 12V, so that the gate substrate control circuit 12 is not damaged.

As shown in fig. 10, another circuit diagram of the clamp circuit 11 in the embodiment of the present application is different from that in fig. 9 in that: the clamp circuit 11 comprises a divider resistor R5 and N diodes which are connected in series in a one-way mode, wherein N is more than or equal to 1; one end of the voltage dividing resistor R5 receives the supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to the anodes of the N unidirectional series diodes and the input terminal GVDD of the gate substrate control circuit 12, and the cathodes of the N unidirectional series diodes are coupled to the input terminal VSS of the gate substrate control circuit 12.

The principle that the clamping circuit 11 of the present embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within the preset range by serially connecting a plurality of diodes is that: by utilizing the gradual change characteristic of the forward conduction voltage of the diode, when the diode is conducted, the voltage between the input voltage GVDD and VSS is equal to the sum of the conduction voltages of the plurality of diodes; when the diode is non-conductive, the input voltage GVDD is almost equal to the supply voltage VDD.

As shown in fig. 11, another circuit diagram of the clamp circuit 11 in the embodiment of the present application is different from that in fig. 9 in that: the clamp circuit 11 comprises a divider resistor R5 and N NMOS tubes connected in series, wherein N is more than or equal to 1; one end of the voltage dividing resistor R5 receives the supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to one end of N series-connected NMOS transistors and the input terminal GVDD of the gate substrate control circuit 12, and the other end of the N series-connected NMOS transistors is coupled to the input terminal VSS of the gate substrate control circuit 12.

The principle that the clamping circuit 11 of the present embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within the preset range by serially connecting a plurality of NMOS is that: the source and the gate of the NMOS are shorted together, the NMOS is equivalent to a diode, and the forward conduction voltage is the threshold voltage Vthn of the NMOS. Therefore, when the NMOS is turned on, the input voltage GVDD is equal to the sum of the threshold voltages of the plurality of NMOS; when the NMOS is not conducting, the input voltage GVDD is almost equal to the supply voltage VDD.

As shown in fig. 12, another circuit diagram of the clamp circuit 11 in the embodiment of the present application is different from that in fig. 9 in that: the clamp circuit 11 comprises a divider resistor R5 and N PMOS tubes connected in series, wherein N is more than or equal to 1; one end of the voltage dividing resistor R5 receives the supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to one end of N series-connected PMOS transistors and the input terminal GVDD of the gate substrate control circuit 12, and the other end of the N series-connected PMOS transistors is coupled to the input terminal VSS of the gate substrate circuit 12.

The clamp circuit 11 of the present embodiment can clamp the voltage between the input voltages GVDD and VSS of the gate substrate control circuit 12 within a predetermined range by connecting a plurality of PMOS transistors in series, and can clamp the voltage between GVDD and VSS within a predetermined range by connecting a plurality of NMOS transistors in series.

As shown in fig. 5, a circuit diagram of the basic protection circuit 10 in the single-wafer battery protection circuit 1 in fig. 4 includes: the circuit comprises a reference circuit, a discharging overcurrent comparator, a discharging short-circuit comparator, a charging overcurrent comparator, an overdischarging voltage comparator, an overcharging voltage comparator, a time delay circuit, a charging and discharging detection circuit, a second resistor R1, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a sixth logic control unit I0, a seventh logic control unit I1, an eighth logic control unit I2, a ninth logic control unit I3 and a tenth logic control unit I4.

The output end of the reference circuit is respectively connected with a first input end (positive input end) of the discharging overcurrent comparator, a first input end (positive input end) of the discharging short-circuit comparator, a second input end (negative input end) of the charging overcurrent comparator, a second input end (negative input end) of the over-discharge voltage comparator and a first input end (positive input end) of the over-charge voltage comparator; a second input end (negative input end) of the discharging overcurrent comparator, a second input end (negative input end) of the discharging short-circuit comparator, a first input end (positive input end) of the charging overcurrent comparator and a second input end (negative input end) of the charging and discharging detection circuit are respectively connected with a source electrode or a drain electrode of the charging and discharging control MOS tube M0 through a fifth resistor R4; one end of the second resistor R1 is connected with the supply voltage VDD, and the other end of the second resistor R1 is connected with a first input end (positive input end) of the over-discharge voltage comparator and one end of the third resistor R2; the other end of the third resistor R2 is connected with a second input end (negative input end) of the overcharge voltage comparator and one end of the fourth resistor R3, and the other end of the fourth resistor R3 is connected with a first input end (positive input end) of the charge-discharge detection circuit and the ground; the output end of the discharging overcurrent comparator, the output end of the discharging short-circuit comparator, the output end of the charging overcurrent comparator, the output end of the over-discharging voltage comparator and the output end of the over-charging voltage comparator are respectively connected with the delay circuit; the output end of the charging overcurrent comparator is respectively connected with the delay circuit and the grid substrate control circuit 12; the output end of the charge-discharge detection circuit is connected with the input end of the over-temperature comparison circuit 13.

The output end of the delay circuit is connected with the first input end of the eighth logic control unit I2 through the VDOC1, VDSHORT and the VDODV sixth logic control unit I0; the output end of the charge-discharge detection circuit is connected with the second input end of the eighth logic control unit I2; the output end of the eighth logic control unit I2 is coupled with the gate substrate control circuit 12; the output ends VDCHOC and VDOCV of the delay circuit are connected with the first input end of the ninth logic control unit I3 through the seventh logic control unit I1; the output end of the charge-discharge detection circuit is connected with the input end of the tenth logic control unit I4; the output end of the tenth logic control unit I4 is connected with the second input end of the ninth logic control unit I3; the output terminal of the ninth logic control unit I3 is coupled to the gate substrate control circuit 12.

The reference circuit is used for generating a positive input signal VOC1 of the discharging overcurrent comparator, a positive input signal VSHORT of the discharging short-circuit comparator, a negative input signal VCHOC of the charging overcurrent comparator, reference output voltages VPN and VOTP, a positive input signal VOCV of the overcharging voltage comparator and a negative input signal VODV of the over-discharging voltage comparator.

The discharging overcurrent comparator outputs a high level VDD when VOC1 is greater than VM1 and outputs a low level VGND when VOC1 is lower than VM1 based on the comparison result of the magnitude of the positive input signal VOC1 and the negative input signal virtual ground voltage VM 1.

The discharge short comparator outputs a high level VDD when VSHORT is greater than VM1 and outputs a low level VGND when VSHORT is lower than VM1 based on the comparison result of the magnitude of the positive input signal VSHORT and the negative input signal virtual ground voltage VM 1.

The charging overcurrent comparator outputs a high level VDD when VM1 is greater than VCHOC and outputs a low level VGND when VM1 is lower than VCHOC, based on the comparison result of the magnitude of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC.

The overcharge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result between the positive input signal VOCV and a negative input signal VROCV of the power supply voltage VDD after being subjected to resistance voltage division.

The over-discharge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result of the positive input signal VRODV and the negative input signal VODV after the power supply voltage VDD is subjected to resistance voltage division.

The charge/discharge detection circuit outputs a high level VDD or a low level VGND based on the comparison result between the positive input signal VGND and the negative input signal virtual ground voltage VM 1. When the positive input signal VGND is greater than the negative input signal virtual ground voltage VM1, a high level VDD is output, and when the positive input signal VGND is lower than the negative input signal virtual ground voltage VM1, a low level VGND is output.

The delay circuit is used for delaying an output signal VOC1P of the discharging overcurrent comparator, an output signal VSHORTP of the discharging short-circuit comparator, an output signal VCHOC1 of the charging overcurrent comparator, an output signal VODVP of the over-discharging voltage comparator and an output signal VOCVP of the over-charging voltage comparator, and correspondingly outputting VDOC1, VDSHRT, VDCHOC, VDODV and VDOCV after delay. VDOC1 is a VOC1P delayed signal, VDSHORT is a VSHORTP delayed signal, VDCHOC is a VCHOC1 delayed signal, VDODV is a VODVP delayed signal, and VDOCV is a VOCVP delayed signal.

When all of VDOC1, VDSHORT, VDODV are high, the sixth logic control unit I0 outputs a signal VOD3 of high level VDD, and when at least one of VDOC1, VDSHORT, VDODV is low, the sixth logic control unit I0 outputs a signal VOD3 of low level VGND.

When VDCHOC, VDOCV are both high, the seventh logic control unit I1 outputs a signal VOC3 output as high level VDD. When at least one of VDCHOC, VDOCV is low, the seventh logic control unit I1 outputs a signal VOC3 output as a low level VGND.

When at least one of the sixth logic control unit I0 output signal VOD3 and the charge and discharge detection circuit output signal VCHP is high, the eighth logic control unit I2 output signal VOD2 is output as the high level VDD. When both VOD3, VCHP are low, VOD2 output is low VGND.

When at least one of the output signal VOC3 of the seventh logic control unit I1 and the output signal VCHN of the tenth logic control unit I4 is high, the output signal VOC2 of the ninth logic control unit I3 is output as the high level VDD. When the output signals VOC3 and VCHN of the seventh logic control unit I1 and the tenth logic control unit I4 are both low, the output signal VOC2 of the ninth logic control unit I3 is output as low VGND.

The basic protection circuit 10 of the present embodiment detects the charge/discharge of the battery, transmits a control signal to the gate substrate control circuit 12, and controls the charge/discharge of the battery by causing the gate substrate control circuit 12 to control the conduction of the charge/discharge control MOS transistor M0 in accordance with the control signal.

As shown in fig. 6, the circuit of the over-temperature protection circuit 13 in the single-wafer battery protection circuit 1 in fig. 4 is shown.

The over-temperature protection circuit 13 includes an over-temperature comparator, a third logic control I14, a fourth logic control unit I15, and a fifth logic control unit I16.

The input end of the over-temperature comparator is connected with the basic protection circuit 10, the output end of the over-temperature comparison circuit 13 is respectively connected with the first input end of the fourth logic control unit I15 and the second input end of the fifth logic control unit I16, the second input end of the fourth logic control unit I15 is connected with the output end of the third logic control unit I14, the first input end of the fifth logic control unit I16 and the input end of the third logic control unit I14 are connected with the basic protection circuit 10, and the output end of the fourth logic control unit I15 and the output end of the fifth logic control unit I16 are coupled with the gate substrate control circuit 12. Specifically, the output terminal vchot of the fourth logic control unit I15 is coupled to the gate substrate control circuit 12 through the second logic control unit I13, and the output terminal vdisptp of the fifth logic control unit I16 is coupled to the gate substrate control circuit 12 through the first logic control unit.

The over-temperature comparator outputs a high level when the positive input end voltage VPN is larger than the negative input end voltage VOTP and outputs a low level when the positive input end voltage VPN is smaller than the negative input end voltage VOTP based on the comparison result of the positive input end voltage VPN and the negative input end voltage VOTP.

When at least one of the over-temperature comparator output voltage VOTPP and the third logic control unit I14 output voltage VCHN1 is high, the fourth logic control unit I15 output voltage VCHOTP is output as a high level VDD. When the over-temperature comparator output voltage VOTPP and the third logic control unit I14 output voltage VCHN1 are both low, the fourth logic control unit I15 output voltage vchot is output low.

When at least one of the over-temperature comparator output voltage VOTPP and the third logic control unit I14 input voltage VCHP is high, the fifth logic control unit I16 output voltage VDISOTP is outputted as the high level VDD. When the over-temperature comparator output voltage VOTPP and the third logic control unit I14 input voltage VCHP are both low, the fifth logic control unit I16 output voltage VDISOTP output is low.

The over-temperature protection circuit 13 of the present embodiment is used for detecting the temperature of the chip integrated with the single-wafer battery protection circuit 1, and controls the conducting gate substrate control circuit 12 together with the basic protection circuit 10.

Fig. 7 is a schematic circuit diagram of the gate substrate control circuit 12 in the single-wafer cell protection circuit 1 shown in fig. 4.

The difference from the gate substrate control circuit of fig. 3 is that the gate substrate control circuit 12 further includes resistors R11, R12, R13, R14, R15, and R16, and MOS transistors M21, M22, M23, M24, M25, and M26.

The gate substrate control circuit 12 includes a gate control portion and a substrate control portion, the gate control portion and the substrate control portion having a common circuit;

the gate control part comprises resistors R11, R12, R13, R14, R15, R16, MOS tubes M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26 and logic control units I6, I7, I8 and I9;

one end of the resistor R11 is connected to the output voltage VOD of the first logic control unit I12; the other end of the resistor R11 is connected with the grid of the MOS tube M7, the input end of the logic control unit I6 and the drain of the MOS tube M21; the source of the MOS transistor M21 is connected to the gate of the MOS transistor M21, the substrate of the MOS transistor M21, the output terminal GVDD of the clamp circuit 11, the substrate of the MOS transistor M7, the source of the MOS transistor M7, the substrate of the MOS transistor M8, the source of the MOS transistor M8, the gate of the MOS transistor M22, the substrate of the MOS transistor M22, and the source of the MOS transistor M22; one end of the resistor R12 is connected with the drain electrode of the MOS tube M22 and the gate electrode of the MOS tube M8; the other end of the resistor R12 is connected with the output end of the logic control unit I6; the drain electrode of the MOS transistor M7 is connected with the drain electrode of the MOS transistor M9 and the gate electrode of the MOS transistor M10; the drain electrode of the MOS transistor M8 is connected with the gate electrode of the MOS transistor M9, the drain electrode of the MOS transistor M10 and the first input end of the logic control unit I9; the output end of the logic control unit I9 is connected with the grid of a charge-discharge control MOS tube M0; a source electrode of a MOS tube M9, a substrate of a MOS tube M9, a source electrode of a MOS tube M10, a substrate of a MOS tube M10, a source electrode of a MOS tube M13, a substrate of a MOS tube M13, a source electrode of a MOS tube M14, a substrate of a MOS tube M14, a source electrode of a MOS tube M17, a substrate of a MOS tube M17, a source electrode of a MOS tube M18 and a substrate of a MOS tube M18 are connected together and connected with a source electrode of a MOS tube M19, a substrate of a MOS tube M19, a source electrode of a MOS tube M20 and a substrate of a MOS tube M20; the drain electrode of the MOS tube M19 is connected with one end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the cathode of the battery; the drain electrode of the MOS tube M20 is connected with the other end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the negative electrode of the charger;

one end of the resistor R13 is connected to the output voltage VOC of the second logic control unit I13; the other end of the resistor R13 is connected with the grid of the MOS tube M11, the input end of the logic control unit I7 and the drain of the MOS tube M23; the source electrode of the MOS transistor M23 is connected with the gate electrode of the MOS transistor M23, the substrate of the MOS transistor M23, the source electrode of the MOS transistor M11, the substrate of the MOS transistor M11, the output end GVDD of the clamp circuit 11, the substrate of the MOS transistor M12, the source electrode of the MOS transistor M12, the gate electrode of the MOS transistor M24, the source electrode of the MOS transistor M24 and the substrate of the MOS transistor M24; one end of the resistor R14 is connected with the drain electrode of the MOS tube M24 and the gate electrode of the MOS tube M12; the other end of the resistor R14 is connected with the output end of the logic control unit I7; the drain electrode of the MOS transistor M11 is connected with the drain electrode of the MOS transistor M13 and the gate electrode of the MOS transistor M14; the drain electrode of the MOS transistor M12 is connected with the gate electrode of the MOS transistor M13, the drain electrode of the MOS transistor M14, the second input end of the logic control unit I9 and the input end of the logic control unit I10;

one end of the resistor R15 is connected to the output voltage VCHOC1 of the basic protection circuit 10; the other end of the resistor R15 is connected with the grid of the MOS tube M15, the input end of the logic control unit I8 and the drain of the MOS tube M25; the source electrode of the MOS transistor M25 is connected with the gate electrode of the MOS transistor M25, the substrate of the MOS transistor M25, the source electrode of the MOS transistor M15, the substrate of the MOS transistor M15, the output end GVDD of the clamp circuit 11, the substrate of the MOS transistor M16, the source electrode of the MOS transistor M16, the gate electrode of the MOS transistor M26, the source electrode of the MOS transistor M26 and the substrate of the MOS transistor M26; one end of the resistor R16 is connected with the drain electrode of the MOS tube M26 and the gate electrode of the MOS tube M16; the other end of the resistor R16 is connected with the output end of the logic control unit I8; the drain electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M17, the gate electrode of the MOS tube M18 and the gate electrode of the MOS tube M20; the drain of MOS transistor M16 is connected to the gate of MOS transistor M17, the drain of MOS transistor M18 and the gate of MOS transistor M19.

The substrate control part comprises resistors R13, R14, R15 and R16, MOS transistors M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M23, M24, M25 and M26, and logic control units I7, I8, I10 and I11;

the input end of the logic control unit I10 is connected with the second input end of the logic control unit I9, the drain electrode of the MOS tube M12, the gate electrode of the MOS tube M13 and the drain electrode of the MOS tube M14; the output end of the logic control unit I10 is connected with the input end of the logic control unit I11 and the grid of the MOS transistor M2; the output end of the logic control unit I11 is connected with the grid of the MOS tube M1; the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M19, one end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the cathode of the battery; the source electrode of the MOS transistor M1, the substrate of the MOS transistor M1, the source electrode of the MOS transistor M2 and the substrate of the MOS transistor M2 are connected together and connected with the substrate of the charge-discharge control MOS transistor M0; the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M20, the other end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the negative electrode of the charger.

The effect of adding resistors and MOS tubes is illustrated by R11, R12, M21 and M22: due to the addition of the clamp circuit 11, the positive power voltage of the GATE substrate control circuit 12 is the output potential GVDD of the clamp circuit 11, while the input voltage VOD may be high level VDD or low level VGND, the voltage between the input voltage GVDD and the power supply voltage VDD, and the voltage between the input voltage GVDD and the power supply voltage VGND may exceed the GATE breakdown voltage of the MOS transistors M7 and M8 to damage the MOS transistors M7 and M8, and the maximum voltage from GATE to GVDD of the MOS transistors M7 and M8 after the addition of R11, M21, R12 and M22 is the parasitic diode voltage of the MOS transistors M21 and M22, which will not damage the MOS transistors. The same principle is that: r13, R14, M23, M24 protect M11, M12 from damage; r15, R16, M25, M26 protect M15, M16 from damage.

The gate substrate control circuit 12 of the present embodiment includes a gate control portion and a substrate control portion; the grid control part is connected with the grid of the charging and discharging control MOS tube M0, and the substrate control part is connected with the substrate of the charging and discharging control MOS tube M0; when the battery is charged and discharged, the grid control part outputs a grid control response signal according to the control signal to control the grid voltage of the charging and discharging control MOS tube M0, and the substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charging and discharging control MOS tube M0, so that the conduction condition of the charging and discharging control MOS tube M0 is controlled.

As shown in fig. 8, the difference from the gate substrate control circuit of fig. 3 is that the gate substrate control circuit 12 further includes resistors R11, R12, R13, R14, R15, R16, and diodes D3, D4, D5, D6, D7, and D8, and the same function as in fig. 9 is realized.

the gate control part comprises resistors R11, R12, R13, R14, R15, R16, MOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, diodes D3, D4, D5, D6, D7, D8, logic control units I6, I7, I8 and I9;

one end of the resistor R11 is connected to the output voltage VOD of the first logic control unit I12; the other end of the resistor R11 is connected with the grid of the MOS tube M7, the input end of the logic control unit I6 and the anode of the diode D3; the cathode of the diode D3 is connected to the substrate of the MOS transistor M7, the source of the MOS transistor M7, the output terminal GVDD of the clamp circuit 11, the substrate of the MOS transistor M8, the source of the MOS transistor M8, and the cathode of the diode D4; one end of the resistor R12 is connected with the anode of the diode D4 and the gate of the MOS transistor M8; the other end of the resistor R12 is connected with the output end of the logic control unit I6; the drain electrode of the MOS transistor M7 is connected with the drain electrode of the MOS transistor M9 and the gate electrode of the MOS transistor M10; the drain electrode of the MOS transistor M8 is connected with the gate electrode of the MOS transistor M9, the drain electrode of the MOS transistor M10 and the first input end of the logic control unit I9; the output end of the logic control unit I9 is connected with the grid of a charge-discharge control MOS tube M0; a source electrode of a MOS tube M9, a substrate of a MOS tube M9, a source electrode of a MOS tube M10, a substrate of a MOS tube M10, a source electrode of a MOS tube M13, a substrate of a MOS tube M13, a source electrode of a MOS tube M14, a substrate of a MOS tube M14, a source electrode of a MOS tube M17, a substrate of a MOS tube M17, a source electrode of a MOS tube M18 and a substrate of a MOS tube M18 are connected together and connected with a source electrode of a MOS tube M19, a substrate of a MOS tube M19, a source electrode of a MOS tube M20 and a substrate of a MOS tube M20; the drain electrode of the MOS tube M19 is connected with one end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the cathode of the battery; the drain electrode of the MOS tube M20 is connected with the other end of the source electrode or the drain electrode of the charge-discharge control MOS tube M0 and the negative electrode of the charger;

one end of the resistor R13 is connected to the output voltage VOC of the second logic control unit I13; the other end of the resistor R13 is connected with the grid of the MOS tube M11, the input end of the logic control unit I7 and the anode of the diode D5; the cathode of the diode D5 is connected to the substrate of the MOS transistor M11, the source of the MOS transistor M11, the output terminal GVDD of the clamp circuit 11, the substrate of the MOS transistor M12, the source of the MOS transistor M12, and the cathode of the diode D6; one end of the resistor R14 is connected with the anode of the diode D6 and the gate of the MOS transistor M12; the other end of the resistor R14 is connected with the output end of the logic control unit I7; the drain electrode of the MOS transistor M11 is connected with the drain electrode of the MOS transistor M13 and the gate electrode of the MOS transistor M14; the drain electrode of the MOS transistor M12 is connected with the gate electrode of the MOS transistor M13, the drain electrode of the MOS transistor M14, the second input end of the logic control unit I9 and the input end of the logic control unit I10;

one end of the resistor R15 is connected to the output voltage VCHOC1 of the basic protection circuit 10; the other end of the resistor R15 is connected with the grid of the MOS tube M15, the input end of the logic control unit I8 and the anode of the diode D7; the cathode of the diode D7 is connected to the substrate of the MOS transistor M15, the source of the MOS transistor M15, the output terminal GVDD of the clamp circuit 11, the substrate of the MOS transistor M16, the source of the MOS transistor M16, and the cathode of the diode D8; one end of the resistor R16 is connected with the anode of the diode D8 and the gate of the MOS transistor M16; the other end of the resistor R16 is connected with the output end of the logic control unit I8; the drain electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M17, the gate electrode of the MOS tube M18 and the gate electrode of the MOS tube M20; the drain of MOS transistor M16 is connected to the gate of MOS transistor M17, the drain of MOS transistor M18 and the gate of MOS transistor M19.

The substrate control part comprises resistors R13, R14, R15 and R16, MOS transistors M1, M2, M11, M12, M13, M14, M15, M16, M17, M18, M19 and M20, diodes D5, D6, D7 and D8, and logic control units I7, I8, I10 and I11.

The application also provides a portable electronic device, which comprises a single-wafer and the single-wafer battery protection circuit 1 disclosed in the above embodiments, and the portable electronic device can be a device with a lithium battery, such as a mobile phone, a toy, a mobile power supply, an electronic cigarette, a bluetooth headset (TWS), and the like.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A single wafer battery protection circuit, comprising: the device comprises a basic protection circuit, a clamp circuit, a grid substrate control circuit, an over-temperature protection circuit and a charge and discharge control MOS (metal oxide semiconductor) tube;

2. The single-wafer battery protection circuit according to claim 1, wherein the over-temperature protection circuit includes an over-temperature comparator, a third logic control unit, a fourth logic control unit, and a fifth logic control unit, the input end of the over-temperature comparator is connected with the basic protection circuit, the output end of the over-temperature comparator is respectively connected with the first input end of the fourth logic control unit and the second input end of the fifth logic control unit, a second input terminal of the fourth logic control unit is connected with an output terminal of the third logic control unit, the first input terminal of the fifth logic control unit and the input terminal of the third logic control unit are connected with the basic protection circuit, the output end of the fourth logic control unit and the output end of the fifth logic control unit are coupled with the grid substrate control circuit.

3. The single-wafer battery protection circuit of claim 1, wherein the clamping circuit comprises a voltage-dividing resistor and N NMOS transistors connected in series, wherein N is greater than or equal to 1; one end of the voltage dividing resistor receives a power supply voltage, the other end of the voltage dividing resistor is connected with one end of the N NMOS tubes connected in series and the input end of the grid substrate control circuit, and the other end of the N NMOS tubes connected in series is coupled to the input end of the grid substrate circuit;

or the clamping circuit comprises a divider resistor and N PMOS tubes connected in series, wherein N is more than or equal to 1; one end of the divider resistor receives a power supply voltage, the other end of the divider resistor is connected with one end of the N PMOS tubes connected in series and the input end of the grid substrate control circuit, and the other end of the N PMOS tubes connected in series is coupled to the input end of the grid substrate circuit.

4. The single wafer battery protection circuit of claim 1, wherein the gate substrate control circuit includes a gate control portion and a substrate control portion; the grid control part is connected with the grid of the charging and discharging control MOS tube, and the substrate control part is connected with the substrate of the charging and discharging control MOS tube.

5. The single-wafer battery protection circuit as claimed in claim 1, wherein the battery is connected in parallel with an RC filter circuit, the RC filter circuit comprises a first resistor and a first capacitor, one end of the first resistor is connected to the positive electrode of the battery, and the other end of the first resistor is connected to the negative electrode of the battery through the first capacitor.

6. The single-wafer battery protection circuit according to claim 1,

the basic protection circuit comprises a reference circuit, a discharging overcurrent comparator, a discharging short-circuit comparator, a charging overcurrent comparator, an overdischarging voltage comparator, an overcharge voltage comparator, a time delay circuit, a charging and discharging detection circuit, a second resistor, a third resistor, a fourth resistor and a fifth resistor, wherein the output end of the reference circuit is respectively connected with the first input end of the discharging overcurrent comparator, the first input end of the discharging short-circuit comparator, the second input end of the charging overcurrent comparator, the second input end of the overdischarging voltage comparator and the first input end of the overcharge voltage comparator;

the second input end of the discharging overcurrent comparator, the second input end of the discharging short-circuit comparator, the first input end of the charging overcurrent comparator and the second input end of the charging and discharging detection circuit are connected with the source electrode or the drain electrode of the charging and discharging control MOS tube through the fifth resistor;

one end of the second resistor is connected with the power supply voltage, and the other end of the second resistor is connected with a first input end of the over-discharge voltage comparator and one end of the third resistor;

the other end of the third resistor is connected with the second input end of the overcharge voltage comparator and one end of the fourth resistor, and the other end of the fourth resistor is connected with the first input end of the charge-discharge detection circuit and the ground;

the output end of the discharging overcurrent comparator, the output end of the discharging short-circuit comparator, the output end of the charging overcurrent comparator, the output end of the over-discharge voltage comparator and the output end of the over-charge voltage comparator are respectively connected with the delay circuit;

the output end of the charging overcurrent comparator is respectively connected with the delay circuit and the grid substrate control circuit;

the output end of the charging and discharging detection circuit is connected with the input end of the over-temperature protection circuit.

7. The single-wafer battery protection circuit of claim 6, wherein the basic protection circuit further comprises a sixth logic control unit, a seventh logic control unit, an eighth logic control unit, a ninth logic control unit, and a tenth logic control unit;

the output end of the delay circuit is connected with the first input end of the eighth logic control unit through a sixth logic control unit; the output end of the charge and discharge detection circuit is connected with the second input end of the eighth logic control unit; the output end of the eighth logic control unit is coupled with the grid substrate control circuit;

the output end of the delay circuit is connected with the first input end of the ninth logic control unit through a seventh logic control unit; the output end of the charge and discharge detection circuit is connected with the input end of the tenth logic control unit; the output end of the tenth logic control unit is connected with the second input end of the ninth logic control unit; the output end of the ninth logic control unit is coupled with the grid substrate control circuit.

8. A battery charging circuit comprising the single-wafer battery protection circuit of any one of claims 1 to 7, a charger, a battery, and an RC filter circuit, wherein:

the RC filter circuit comprises a resistor and a capacitor, one end of the resistor is connected with the anode of the battery, and the other end of the resistor is connected with the cathode of the battery through the capacitor;

one end of the resistor is connected with a power supply voltage end of the basic protection circuit, and the other end of the resistor is connected with the anode of the battery;

one end of the capacitor is connected with a power supply voltage end of the basic protection circuit, the other end of the capacitor is connected with the negative electrode of the battery, the positive electrode of the charger is connected with the positive electrode of the battery to provide charging voltage for the battery, and the negative electrode of the charger is connected with the negative electrode of the battery through the charging and discharging control MOS tube.

9. A battery discharge circuit comprising the single-wafer battery protection circuit of any one of claims 1 to 7, an RC filter circuit, a battery, and a load, wherein:

one end of the capacitor is connected with a power supply voltage end of the basic protection circuit, and the other end of the capacitor is connected with the negative electrode of the battery;

the positive pole of the battery is connected with the positive pole of the load to provide power for the load, and the negative pole of the load is connected with the negative pole of the battery through the charge-discharge control MOS tube.

10. A portable electronic device comprising a single wafer and the single wafer battery protection circuit of any one of claims 1-7.