CN110429689A - A kind of Optimal Control System of lithium electric protection chip zero volt battery charger - Google Patents
A kind of Optimal Control System of lithium electric protection chip zero volt battery charger Download PDFInfo
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- CN110429689A CN110429689A CN201910800757.1A CN201910800757A CN110429689A CN 110429689 A CN110429689 A CN 110429689A CN 201910800757 A CN201910800757 A CN 201910800757A CN 110429689 A CN110429689 A CN 110429689A
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- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910052744 lithium Inorganic materials 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000005611 electricity Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 229910052987 metal hydride Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
The invention discloses a kind of Optimal Control Systems of lithium electric protection chip zero volt battery charger; voltage comparator circuit, substrate selection circuit and output control circuit are set; the current detecting port CS of the input terminal connection protection chip IC of voltage comparator circuit; the output of voltage comparator circuit connects substrate selection circuit; the input signal of the output of substrate selection circuit and the logic control signal CT_N inside protection chip IC and its inversion signal CT collectively as output control circuit, the re-charge control port OC of the output connection protection chip IC of output control circuit.
Description
Technical field
The present invention relates to the charge control of lithium electric protection chip, especially a kind of lithium electric protection chip zero volt battery charger
Optimal Control System.
Background technique
In recent years, PDA, DSC, Cellular Phone, Camcorde, Portable, Audio, Advanced Game,
The use lithium of more and more products such as Assist Bicycle, Electric Scooter, Bluetooth Device rapidly
Battery carrys out the main power source as it, and tracing it to its cause, small in size nothing more than its, energy density is high, memory-less effect, cycle life
The advantages such as height, cell voltage are high, self-discharge rate is low.But everything has dual character, just because of lithium battery and ni-Cd, nickel-metal hydride battery are not
Too, lithium battery energy density is high, and under overcharged state, energy will be superfluous after battery temperature rises, then electrolyte
It decomposes and generates gas, lead to the crisis for having ignition or rupture because internal pressure rises, therefore must supervise in real time for such situation
Battery charging situation is surveyed, once detect that exception is shut off charge circuit.The control mode of charge circuit mainly has control pmos
System controls two ways with NMOS tube, and initial stage is mainly controlled using PMOS tube, the maturation with technology and the requirement to cost etc.,
More and more systems use NMOS tube control mode.
Fig. 1 is the prior art binodal lithium battery charging circuit signal enumerated in the application of the applicant 201810671213.5
Figure, its charge circuit use NMOS tube control mode, including lithium battery Battery1, Battery2, resistance R9,
R10, R11, capacitor C1, C2, control of discharge NMOS tube NM1, charge control NMOS tube NM2 and protection chip IC, protect chip IC
Power port VDD and lithium battery Battery2 voltage monitoring port connection capacitor C2 one end and resistance R9 one end,
The other end of capacitor C2 is grounded, the anode of the other end connection lithium battery Battery2 of resistance R9 and the anode of charger, protection
One end of the voltage monitoring port VC connection capacitor C1 of the lithium battery Battery1 of chip IC and one end of resistance R10, capacitor C1
The other end connection protection chip IC chip ground port VSS and lithium battery Battery1 cathode and ground connection, resistance R10's
The other end connects the cathode of lithium battery Battery2 and the anode of lithium battery Battery1, protects the control of discharge port of chip IC
The grid of OD connection NMOS tube NM1, the source electrode ground connection of NMOS tube NM1, the drain electrode of the drain electrode connection NMOS tube NM2 of NMOS tube NM1,
The re-charge control port OC of the grid connection protection chip IC of NMOS tube NM2, the cathode of the source electrode connection charger of NMOS tube NM2
And the current detecting port CS of chip IC is protected by resistance R11 connection.
Fig. 1 circuit is when carrying out charging closing, by taking binodal battery protection system as an example, it is assumed that cell voltage 8.4V fills
Electrical voltage is 24V, and the source electrode that NMOS NM2 is connect with charger at this time is negative voltage, and absolute value is that charger voltage subtracts electricity
Pond group voltage is herein 15.4V, and NM2 grid control signal OC minimum level if not handling is ground, grid, source electrode electricity
Pressure is that 15.4V is greater than NM2 unlatching threshold value, and charge circuit can not close.
Fig. 2 is the zero volt battery charger of the lithium electric protection chip in the application of the applicant 201810671213.5,
The grid of the grid connection NM15 of PM11 and the drain electrode for connecting the logic control signal LOGIC_N, PM11 inside protection chip IC
The one end connecting resistance R12, the grid of PM12 and the grid of NM16, the resistance R12 other end connect NM15 drain electrode, the source electrode of NM15 and
The source level of NM16 is all connected with the port CS of protection chip IC, source electrode and the connection of the source electrode and PM13 of the source electrode connection PM12 of PM11
The drain electrode of one end, the one end resistance R14 and PM13 of the drain electrode connection resistance R13 of VDD, PM12, the other end connection of resistance R13
The inversion signal LOGIC of the logic control signal LOGIC_N inside chip IC is protected in the drain electrode of NM16, the grid connection of PM13,
The port OC of resistance R14 other end connection protection chip IC.LOGIC_N exports VDD level when chip works normally, and LOGIC is
The inversion signal of LOGIC_N exports as VSS level, and OC output is VDD level after logical process, and charging is normally carried out, and works as detection
When to charging abnormality, LOGIC_N output from VDD level becomes VSS level, and OC output is CS electricity after logical process
Flat, NM2 is closed, and can shut charge circuit, but circuit shortcoming is that CS is negative voltage when charging is abnormal, when LOGIC_N is defeated
When being out VSS level, PMOS tube PM11, NMOS tube NM15 are opened simultaneously, in order to which the normal of output signal and limitation chip are static
Power consumption, resistance R12 value must be very big, and this part power consumption stream is related with VDD and cell voltage difference, and can only reduce can not disappear
Remove, thus how effective charge closing circuit, combine system cost, power consumption etc. be badly in need of consider the problems of.
Summary of the invention
To detect exception when solving the charging of lithium electric protection system, system can effective charge closing circuit while, it is simultaneous
The problems such as caring for system cost, power consumption, the present invention provides a kind of optimal control system of lithium electric protection chip zero volt battery charger
System, belong to the subsequent application of the applicant 201810671213.5, be by the zero volt battery charger of Fig. 2 improved and
Voltage comparator circuit is set before this circuit and substrate selection circuit constitutes the optimization of lithium electric protection chip zero volt battery charger
Control system, so that it may meet low cost, the application requirement of low-power consumption while realizing effective charge closing circuit.
In order to achieve the above object, the technical solution adopted by the present invention is that: a kind of lithium electric protection chip zero volt battery charging electricity
The Optimal Control System on road, protection chip IC are equipped with supply port VDD, grounding ports VSS, control of discharge port OD, charging control
Port OC processed, current detecting port CS, it is characterised in that: setting voltage comparator circuit, substrate selection circuit and output control electricity
Road, the current detecting port CS of the input terminal connection protection chip IC of voltage comparator circuit, the output connection of voltage comparator circuit
Substrate selection circuit, the output of substrate selection circuit and logic control signal CT_N and its reverse phase letter inside protection chip IC
The input signal of number CT collectively as output control circuit, the charge control of the output connection protection chip IC of output control circuit
Port OC.
Voltage comparator circuit includes PMOS tube PM1, PM2, PM3 and PM4, NMOS tube NM3, NM4, NM5 and NM6 and resistance
R2, R3 and R4；The source electrode of PMOS tube PM1 and the source electrode of the source electrode of PMOS tube PM2, the source electrode of PMOS tube PM3 and PMOS tube PM4 are mutual
Connect and connect VDD, the grid of PMOS tube PM1 is with the gate interconnection of PMOS tube PM2 and connect the drain electrode and NMOS tube of PMOS tube PM1
The drain electrode of NM3, the grid of NMOS tube NM3 connect bias voltage VBIASN, and the source electrode of NMOS tube NM3 connects one end of resistance R2,
Input terminal of the other end of resistance R2 as voltage comparator circuit, the current detecting port CS of connection protection chip IC, PMOS tube
Drain electrode, the grid of PMOS tube PM3 and the grid of NMOS tube NM5 of the drain electrode connection NMOS tube NM4 of PM2, the grid of NMOS tube NM4
Bias voltage VBIASN, the source electrode of NMOS tube NM4 and the source electrode of NMOS tube NM5 and the source grounding of NMOS tube NM6 are connected,
The drain electrode of PMOS tube PM3 connects the grid of one end of resistance R3 and the grid of PMOS tube PM4 and NMOS tube NM6 and as voltage ratio
Compared with an output end of circuit, SUB_SLN signal, the drain electrode of the other end connection NMOS tube NM5 of resistance R3, PMOS tube are exported
The drain electrode of PM4 connects one end of resistance R4 and the another output as voltage comparator circuit, exports SUB_SL signal, resistance
The drain electrode of the other end connection NMOS tube NM6 of R4.
Substrate selection circuit includes PMOS tube PM5, PM6, NMOS tube NM7, NM8, NM9, NM10, resistance R5 and resistance R6；
The source electrode of PMOS tube PM5 and the source electrode of PMOS tube PM6 are all connected with VDD, and the grid of PMOS tube PM5 connects the defeated of voltage comparator circuit
The output signal SUB_SLN of the grid connection voltage comparator circuit of signal SUB_SL out, PMOS tube PM6, the drain electrode of PMOS tube PM5
The grid of one end of resistance R5 and the grid of NMOS tube NM9 and NMOS tube NM8 is connected, the other end of resistance R5 connects NMOS tube
The drain electrode of NM7, source electrode, the source electrode of NMOS tube NM8 and the source of NMOS tube NM10 of the source electrode connection NMOS tube NM9 of NMOS tube NM7
Pole and output end as substrate selection circuit, output signal SUB, the grounded drain of NMOS tube NM9, the drain electrode of NMOS tube NM10
One end of the drain electrode connection resistance R6 of the current detecting port CS of connection protection chip IC, PMOS tube PM6 and NMOS tube NM7
The grid of grid and NMOS tube NM10, the drain electrode of the other end connection NMOS tube NM8 of resistance R6.
Output control circuit includes PMOS tube PM7, PM8, PM9 and PM10, NMOS tube NM11, NM12, NM13 and NM14, electricity
Hinder R7 and resistance R8；The source of the source electrode of PMOS tube PM7, the source electrode of PMOS tube PM8, the source electrode of PMOS tube PM9 and PMOS tube PM10
Pole is all connected with VDD, the logic control signal CT_N inside the grid connection protection chip IC of PMOS tube PM7, the leakage of PMOS tube PM7
Pole connects one end of resistance R7 and the grid of NMOS tube NM12, the logic inside the grid connection protection chip IC of PMOS tube PM8
Signal CT is controlled, the drain electrode of PMOS tube PM8 connects the grid of one end of resistance R8 and the grid of NMOS tube NM11, PMOS tube PM9
The grid of pole and NMOS tube NM13, the grid of the drain electrode connection NMOS tube NM14 of PMOS tube PM9 and the grid of PMOS tube PM10,
The source electrode of NMOS tube NM11 and source electrode, the source electrode of NMOS tube NM13 and the source electrode of NMOS tube NM14 of NMOS tube NM12 are all connected with
The drain electrode of the output signal SUB of substrate selection circuit, PMOS tube PM10 and the drain interconnection of NMOS tube NM14 are simultaneously controlled as output
The output end of circuit processed is connect with the re-charge control port OC of protection chip IC.
The voltage comparator circuit, substrate selection circuit and output control circuit are integrated in protection chip IC.
The invention has the following advantages and beneficial effects: can independently select to charge according to the case where detecting voltage when charging
NMOS tube NM7, NM8, NM9, NM10 underlayer voltage inside chip IC, so that the grid level of final system control NMOS tube NM2
OC low level after the abnormality processing that charges is negative voltage, and absolute value is that charger voltage subtracts battery voltage, and when high level is
Vdd voltage, when protection, can completely close charge circuit, while meet lithium electric protection low cost, the application requirement of low-power consumption.Circuit
Structure is simple, by adjusting the size of bias voltage VBIASN and resistance R2 come flexible setting NMOS tube NM7, NM8, NM9, NM10
Substrate switches voltage, while thoroughly shutting charge circuit, meets lithium electric protection low cost, the application demand of low-power consumption.
Detailed description of the invention
Fig. 1 is existing lithium electric protection charging schematic diagram；
Fig. 2 is existing zero volt battery charger figure；
Fig. 3 is present system composition figure；
Fig. 4 is voltage comparator circuit figure；
Fig. 5 is substrate selection circuit figure；
Fig. 6 is to the improved output control circuit figure of Fig. 2；
Fig. 7 is substrate selection waveform diagram.
Specific embodiment
Such as Fig. 3, present system includes voltage comparator circuit, substrate selection circuit and output control circuit (output control
The improvement of zero volt battery charger in circuit, that is, Fig. 2 processed), the electric current of the input terminal connection protection chip IC of voltage comparator circuit
Port CS is detected, the output of voltage comparator circuit connects substrate selection circuit, the output of substrate selection circuit and protection chip
Logic control signal CT_N (i.e. LOGIC_N in Fig. 2) and its inversion signal CT (i.e. LOGIC in Fig. 2) inside IC is common
As the input signal of output control circuit, the re-charge control port OC of the output connection protection chip IC of output control circuit.
Such as Fig. 4, voltage comparator circuit includes PMOS tube PM1, PM2, PM3 and PM4, NMOS tube NM3, NM4, NM5 and NM6 with
And resistance R2, R3 and R4.PM1, PM2, PM3, PM4 source electrode meet VDD, and PM1 grid, drain electrode are shorted and PM2 grid, NMOS tube NM3
Drain electrode connection, NM3 grid meet biasing VBIASN, the one end source electrode connecting resistance R2, and another termination of R2 inputs CS, PM2 drain electrode, NMOS
NM4 drain electrode, PMOS PM3 grid, NMOS NM5 grid are connected, and NM4 grid meets biasing VBIASN, and NM4, NM5, NM6 source electrode connect
VSS, PM3 drain electrode, the one end R3, PM4 grid, the connection of NM6 grid, output signal SUB_SLN, the resistance R3 other end and NM5 leak
Extremely it is connected, PM4 drain electrode, the one end resistance R4 connection output SUB_SL signal, the resistance R4 other end and NM6 drain electrode connect.Substrate choosing
Select PMOS PM5 in circuit, PM6 source electrode meets VDD, NMOS NM7, NM8, NM9, NM10 source electrode connect output SUB signal, PM5 drain electrode,
The one end resistance R5, NM9, NM8 grid are connected, and PM5 grid meets input signal SUB_SL, and NM9 drain electrode connects VSS, the resistance R5 other end
NM7 drain electrode is connect, PM6 grid meets input signal SUB_SLN, and PM6 drain electrode, NM7 grid, the one end resistance R6, NM10 grid are connected, electricity
The connection NM8 drain electrode of the R6 other end is hindered, NM10 drain electrode meets CS.
Such as Fig. 5, substrate selection circuit includes PMOS tube PM5, PM6, NMOS tube NM7, NM8, NM9, NM10, resistance R5 and electricity
Hinder R6.The source electrode of PM5 and the source electrode of PM6 are all connected with VDD, the output signal SUB_SL of the grid connection voltage comparator circuit of PM5,
One end of the drain electrode connection resistance R5 of the output signal SUB_SLN, PM5 of the grid connection voltage comparator circuit of PM6 and NM9
The grid of grid and NM8, the drain electrode of the other end connection NM7 of resistance R5, the source electrode of NM7 connect the source electrode of the source electrode of NM9, NM8
With the source electrode of NM10 and as the output end of substrate selection circuit, output signal SUB.The drain electrode of the grounded drain of NM9, NM10 connects
Connect one end of drain electrode connection resistance R6 of current detecting the port CS, PM6 of protection chip IC and the grid of the grid of NM7 and NM10
Pole, the drain electrode of the other end connection NM8 of resistance R6.
Such as Fig. 6, output control circuit includes PMOS tube PM7, PM8, PM9 and PM10, NMOS tube NM11, NM12, NM13 and
NM14, resistance R7 and R8.PM7, PM8, PM9, PM10 source electrode meet VDD, and NM11, NM12, NM13, NM14 source electrode connect SUB, PM7 grid
Pole meets input control signal CT_N, and PM7 drains, one end of R7 is connect with NM12 grid, and the R7 other end and NM11 drain electrode connect,
PM8 grid meets input control signal CT, and PM8 drain electrode, one end of resistance R8, NM11 grid, PM9 grid are connect with NM13 grid,
The resistance R8 other end and NM12 drain electrode connect, and PM9 drain electrode, NM13 drain electrode, PM10 grid are connect with NM14 grid, PM10 drain electrode,
NM14 drain electrode, which is connected, exports OUT control signal connection OC.
Working principle and the course of work of the present invention: as illustrated by the arrows in fig. 1, OD, OC are defeated for current trend when charging normal
It is out VDD level, it is negative voltage that control NM1, NM2, which open charging, and PB- current potential and CS current potential are equal, and order of magnitude is charging
The product of electric current and 2 MOS conduction impedances, i.e. charging current 2A, each MOS conduction impedance be 25m Ω if, CS voltage be-
0.1V.It in voltage comparator circuit, detects that CS voltage is normal, flows through that NM3 electric current is smaller, the PM1 electric current of same branch is also small, mirror
As rear PM2 pull-up current ratio NM4 pull-down current is small, NM4 drain electrode output low level exports substrate choosing after PM3, NM5 are reversed
Selecting signal SUB_SLN is VDD level, and it is VSS level, transmitting that substrate selection signal SUB_SL is exported after PM4, NM6 are reversed
When to substrate selection circuit, PM5 conducting, PM6 cut-off, NM9 grid exports high level, NM9 conducting, and Substrate signal SUB is selected as
VSS level is transmitted to the substrate of output circuit, and the signal CT of output circuit control at this time is VSS level, its reverse signal CT_N
For VDD level, PM7 cut-off, PM8 conducting, PM8, which drains, exports high level (VDD level), exports after PM9, NM13 are reversed low
Level, it is high level that OUT signal is exported after PM10, NM14 are reversed.When system detection is excessively high to cell voltage or charges
When electric current is excessive, CS voltage is constantly reduced, and is flowed through NM3 electric current and is constantly increased, and the PM1 electric current of same branch also constantly increases
Greatly, PM2 electric current constantly increases after mirror image, and when CS voltage is lower than setting protection value, PM2 pull-up current is pulled down greater than NM4
Electric current, NM4 drain electrode output high level, it is VSS level that substrate selection signal SUB_SLN is exported after PM3, NM5 are reversed, is passed through
Reversely output substrate selection signal SUB_SL is VDD level afterwards by PM4, NM6, when being transmitted to substrate selection circuit, PM5 cut-off, and PM6
Conducting, NM10 grid export high level, NM10 conducting, and substrate output signal SUB is selected as CS level, is transmitted to output circuit
Substrate, the signal CT of output circuit control at this time is VDD level, its reverse signal CT_N is VSS level, and PM7 is connected, and PM8 is cut
Only, PM8 drain electrode output low level (CS level), exports high level after PM9, NM13 are reversed, after PM10, NM14 are reversed
Output OUT signal is low level (CS level), completely closes charge circuit, stops charging.Size is biased by setting VBIASN
And adjustment resistance R2 resistance value, CS and GND can be adjusted flexibly and overturn point, to realize the flexible switching of substrate electric potential.Such as Fig. 4 institute
Show, the current mirror of PM1, PM2 composition to flow through that NM3, NM4 electric current are equal, and it is I4=0.5u that NM4, which flows through electric current,ncoxW/L*
(VBIASN-VTH)2, wherein unIt is fixed numbers for electron mobility, the breadth length ratio of W/L NM3, NM4 are in actual design
Fixed value, VTH NM3, NM4 threshold voltage are fixed values in actual design, and NM3 flows through electric current I3=-VCS/R2, wherein VCS
CS terminal voltage when changing for substrate selection signal is negative value, allows I3=I4 that can acquire VCS=-R2*0.5uncoxW/L*
(VBIASN-VTH)2.For example, work as R2=100K, when VBIASN=0.8V, a CS and GND substrate selection overturning point voltage VCS at this time
=-0.2V, namely if NM7, NM8, NM9, NM10 substrate S UB are selected as CS voltage, otherwise select when CS voltage is less than -0.2V
It is selected as VSS voltage.Change the size of VCS, change VBIASN or resistance R2 size is ok, VCS is such as wanted to reduce, it can
It increases resistance R2 or increases VBIASN voltage, it is desirable to VCS is increased, reduces resistance R2 or reduces VBIASN, it is different
Different VCS values can be obtained in VBIASN, R2 value, substrate selection overturning point value are adjusted flexibly, and integrated circuit structure is simple, only
NM3, NM4 branch have electric current to flow through, and consume extremely low electric current.
As shown in fig. 7, CS voltage is low level (VSS level), substrate selection signal when system does not charge, discharges
SUB_SL is low level (VSS level), and SUB_SLN is high level (VDD level), and NMOS NM7, NM8, NM9, NM10 substrate are defeated
Signal SUB is VSS level out, and it is low level (VSS level) that chip logic, which controls signal CT, and CT_N is high level (VDD level),
Output control signal OUT is high level (VDD level).When system discharge, CS voltage is low level (more slightly higher than VSS level),
Substrate selection signal SUB_SL be low level (VSS level), SUB_SLN be high level (VDD level), NMOS NM7, NM8,
NM9, NM10 substrate output signal SUB are VSS level, and it is low level (VSS level) that chip logic, which controls signal CT, and CT_N is height
Level (VDD level), output control signal OUT is high level (VDD level).When system charges exception, CS voltage is low electricity
Flat (negative voltage, lower than VSS current potential), substrate selection signal SUB_SL are high level (VDD level), and SUB_SLN is low level
(VSS level), NMOS NM7, NM8, NM9, NM10 substrate output signal SUB are CS level, and it is height that chip logic, which controls signal CT,
Level (VDD level), CT_N are low level (VSS level), and output control signal OUT is low level (CS level).
Claims (2)
1. a kind of Optimal Control System of lithium electric protection chip zero volt battery charger, protection chip IC is equipped with supply port
VDD, grounding ports VSS, control of discharge port OD, re-charge control port OC, current detecting port CS, it is characterised in that: setting
Voltage comparator circuit, substrate selection circuit and output control circuit, the input terminal connection protection chip IC of voltage comparator circuit
The output of current detecting port CS, voltage comparator circuit connect substrate selection circuit, the output and protection of substrate selection circuit
The input signal of logic control signal CT_N and its inversion signal CT collectively as output control circuit inside chip IC, output
The re-charge control port OC of the output connection protection chip IC of control circuit；
Voltage comparator circuit includes PMOS tube PM1, PM2, PM3 and PM4, NMOS tube NM3, NM4, NM5 and NM6 and resistance R2,
R3 and R4；The source electrode of PMOS tube PM1 and source electrode, the source electrode of PMOS tube PM3 and the source electrode of PMOS tube PM4 of PMOS tube PM2 interconnect
And VDD is connected, the grid of PMOS tube PM1 is with the gate interconnection of PMOS tube PM2 and connect the drain electrode and NMOS tube of PMOS tube PM1
The drain electrode of NM3, the grid of NMOS tube NM3 connect bias voltage VBIASN, and the source electrode of NMOS tube NM3 connects one end of resistance R2,
Input terminal of the other end of resistance R2 as voltage comparator circuit, the current detecting port CS of connection protection chip IC, PMOS tube
Drain electrode, the grid of PMOS tube PM3 and the grid of NMOS tube NM5 of the drain electrode connection NMOS tube NM4 of PM2, the grid of NMOS tube NM4
Bias voltage VBIASN, the source electrode of NMOS tube NM4 and the source electrode of NMOS tube NM5 and the source grounding of NMOS tube NM6 are connected,
The drain electrode of PMOS tube PM3 connects the grid of one end of resistance R3 and the grid of PMOS tube PM4 and NMOS tube NM6 and as voltage ratio
Compared with an output end of circuit, SUB_SLN signal, the drain electrode of the other end connection NMOS tube NM5 of resistance R3, PMOS tube are exported
The drain electrode of PM4 connects one end of resistance R4 and the another output as voltage comparator circuit, exports SUB_SL signal, resistance
The drain electrode of the other end connection NMOS tube NM6 of R4；
Substrate selection circuit includes PMOS tube PM5, PM6, NMOS tube NM7, NM8, NM9, NM10, resistance R5 and resistance R6；PMOS
The source electrode of pipe PM5 and the source electrode of PMOS tube PM6 are all connected with VDD, the output letter of the grid connection voltage comparator circuit of PMOS tube PM5
The output signal SUB_SLN of the grid connection voltage comparator circuit of number SUB_SL, PMOS tube PM6, the drain electrode connection of PMOS tube PM5
The other end of the grid of one end of resistance R5 and the grid of NMOS tube NM9 and NMOS tube NM8, resistance R5 connects NMOS tube NM7
Drain electrode, the source electrode of the source electrode connection source electrode of NMOS tube NM9 of NMOS tube NM7, the source electrode of NMOS tube NM8 and NMOS tube NM10 is simultaneously
As the output end of substrate selection circuit, output signal SUB, the grounded drain of NMOS tube NM9, the drain electrode connection of NMOS tube NM10
Protect the current detecting port CS of chip IC, one end of the drain electrode connection resistance R6 of PMOS tube PM6 and the grid of NMOS tube NM7
With the grid of NMOS tube NM10, the drain electrode of the other end connection NMOS tube NM8 of resistance R6；
Output control circuit includes PMOS tube PM7, PM8, PM9 and PM10, NMOS tube NM11, NM12, NM13 and NM14, resistance R7
With resistance R8；The source electrode of PMOS tube PM7, the source electrode of PMOS tube PM8, the source electrode of the source electrode of PMOS tube PM9 and PMOS tube PM10 are equal
VDD, the logic control signal CT_N inside the grid connection protection chip IC of PMOS tube PM7 are connected, the drain electrode of PMOS tube PM7 connects
The logic control inside chip IC is protected in the grid connection of one end of connecting resistance R7 and the grid of NMOS tube NM12, PMOS tube PM8
One end of the drain electrode connection resistance R8 of signal CT, PMOS tube PM8 and the grid of NMOS tube NM11, PMOS tube PM9 grid and
The grid of NMOS tube NM13, the grid of the drain electrode connection NMOS tube NM14 of PMOS tube PM9 and the grid of PMOS tube PM10, NMOS tube
The source electrode of NM11 and source electrode, the source electrode of NMOS tube NM13 and the source electrode of NMOS tube NM14 of NMOS tube NM12 are all connected with substrate choosing
Select the output signal SUB of circuit, the drain electrode of PMOS tube PM10 and the drain interconnection of NMOS tube NM14 and as output control circuit
Output end with protection chip IC re-charge control port OC connect.
2. the Optimal Control System of lithium electric protection chip zero volt battery charger according to claim 1, feature exist
In: the voltage comparator circuit, substrate selection circuit and output control circuit are integrated in protection chip IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910800757.1A CN110429689A (en) | 2019-08-28 | 2019-08-28 | A kind of Optimal Control System of lithium electric protection chip zero volt battery charger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910800757.1A CN110429689A (en) | 2019-08-28 | 2019-08-28 | A kind of Optimal Control System of lithium electric protection chip zero volt battery charger |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110429689A true CN110429689A (en) | 2019-11-08 |
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| CN201910800757.1A Pending CN110429689A (en) | 2019-08-28 | 2019-08-28 | A kind of Optimal Control System of lithium electric protection chip zero volt battery charger |
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| CN112688394A (en) * | 2020-12-28 | 2021-04-20 | 苏州赛芯电子科技股份有限公司 | Lithium battery charging protection circuit and lithium battery |
| CN113965195A (en) * | 2021-12-22 | 2022-01-21 | 芯昇科技有限公司 | Universal input/output interface anti-creeping circuit, chip and electronic equipment |
| CN114188922A (en) * | 2021-11-08 | 2022-03-15 | 力智电子(深圳)有限公司 | Battery protection integrated circuit |
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