CN111693901A - A broken string detecting system for multisection lithium cell protection chip - Google Patents

A broken string detecting system for multisection lithium cell protection chip Download PDF

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Publication number
CN111693901A
CN111693901A CN202010737795.XA CN202010737795A CN111693901A CN 111693901 A CN111693901 A CN 111693901A CN 202010737795 A CN202010737795 A CN 202010737795A CN 111693901 A CN111693901 A CN 111693901A
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China
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disconnection detection
output
battery
nmos
pmos
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涂再林
张洪俞
施泉
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NANJING MICRO ONE ELECTRONICS Inc
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NANJING MICRO ONE ELECTRONICS Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302—Overcharge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00306—Overdischarge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

A disconnection detection system of a multi-section lithium battery protection chip comprises a logic time sequence circuit, a level shift circuit and a disconnection detection circuit, wherein the logic time sequence circuit generates an initial disconnection detection time sequence signal to the level shift circuit, the final disconnection detection time sequence signal obtained by the level shift circuit is transmitted to the disconnection detection circuit, the disconnection detection circuit is provided with disconnection detection units with the same number as the number of battery sections, output signals of all the disconnection detection units are respectively input to a disconnection detection signal output unit, the output unit output signal is connected with a charging and discharging control terminal of a protection chip IC, when disconnection does not occur in a normal state, a charging and discharging control terminal outputs a high level, a charging and discharging NMOS pipe is started to carry out normal charging and discharging, when disconnection occurs in any section of batteries, the output signal of the disconnection detection signal output unit controls the charging and discharging control terminal to output a low level, and the charge and discharge NMOS tube is closed, so that the charge and discharge protection of the system in the disconnection state is realized.

Description

A broken string detecting system for multisection lithium cell protection chip
Technical Field
The invention relates to a multi-lithium battery protection chip, in particular to a disconnection detection system for the multi-lithium battery protection chip.
Background
In recent years, electric tools, electric vehicles and the like gradually integrate into our lives, and the power supply systems of the electric tools, the electric vehicles and the like are discovered to be mainly using a plurality of lithium batteries as main power sources thereof due to the advantages of small volume, high energy density, no memory effect, long cycle life, high battery voltage, low self-discharge rate and the like. However, the lithium battery itself has a potential safety hazard, and excessive charging can raise the voltage of the battery, the battery expands and explodes, and excessive discharging can damage the characteristics of the battery, which seriously affects the service life of the battery, and this situation is particularly serious in a system powered by multiple lithium batteries. The common lithium battery protection chip has a corresponding protection mechanism for overcharge, overdischarge and the like of the battery, but when the connection between the battery and the protection chip is disconnected, the system cannot detect the state, the whole battery pack is still charged or discharged, and serious potential safety hazards exist.
Disclosure of Invention
In order to solve the problem that the system cannot recognize the state and still continues to charge or discharge when the batteries in the multiple lithium battery protection chips are disconnected with the protection chips, the system particularly provides the disconnection detection system for the multiple lithium battery protection chips, so that when the batteries are disconnected with the protection chips, the system can detect the disconnection state, stop the charging or discharging of the battery pack, prevent potential safety hazards caused by the overcharge or the overdischarge of the batteries, and improve the safety of the system.
In order to realize the purpose, the invention adopts the technical scheme that: the utility model provides a broken string detecting system for multisection lithium cell protection chip, the power supply of protection chip is 4 section lithium cell at least, its characterized in that: the disconnection detection system comprises a logic time sequence circuit, a level shift circuit and a disconnection detection circuit which are connected in sequence, wherein the logic time sequence circuit generates an initial disconnection detection time sequence signal and outputs the initial disconnection detection time sequence signal to the level shift circuit, the final disconnection detection time sequence signal is obtained after the level shift circuit and is transmitted to the disconnection detection circuit, the disconnection detection circuit is provided with a number of disconnection detection units corresponding to the number of battery nodes, each detection unit corresponds to one output signal, the output signals of the disconnection detection units are respectively input to the disconnection detection signal output unit, the disconnection detection signal output unit connects the output control signals with a charge control terminal COUT and a discharge control terminal DOUT of a protection chip IC, when disconnection protection does not occur in a normal state, the charge control terminal COUT and the discharge control terminal DOUT output high levels, a charge-discharge NMOS pipe controlled correspondingly is opened, and normal charge and discharge can be carried out, when any battery is disconnected, the output control signal of the disconnection detection signal output unit controls the charge control terminal COUT and the discharge control terminal DOUT to output low level, and the correspondingly controlled charge and discharge NMOS tube is closed, so that the charge and discharge protection of the system in the disconnection state is realized.
The logic sequential circuit comprises an NMOS tube NM4, comparators COMP1 and COMP2, inverters INV1, INV2, INV3 and INV4, NAND gates 1 and1, a D flip-flop DFF, a capacitor C1 and a current source; the positive end of the current source is connected with VCC, the negative end of the current source is connected with one end of a capacitor C1, the drain of an NMOS tube NM4, the positive end of a comparator COMP1 and the positive end of a comparator COMP2, the other end of the capacitor C1 is connected with the source of an NMOS tube NM4 and is grounded, the negative end of the comparator COMP1 is connected with a reference voltage Vstart, the negative end of the comparator COMP2 is connected with a reference voltage Vend, the output of the comparator COMP1 is connected with the input of an inverter INV1, the input B of a NAND gate 1 and the input A of a NAND gate 2, the output of an inverter INV1 is connected with the clock terminal CLK of a D flip-flop DFF, the output Q of the D flip-flop DFF is connected with the input end D2 and the other input A of the NAND gate 1, the output of the comparator COMP2 is connected with the gate of the NMOS tube NM4, the output of the inverter 46INV 45 is connected with the other input B of the NAND gate 3, the output of the NAND gate INV 573 is, an output signal EVEN of the NAND gate NAND2 is connected with the input of the inverter INV4, and the inverter INV4 outputs a signal EVEN _ N;
the level shift circuit comprises two level shift units with the same structure, wherein each level shift unit comprises two PMOS (P-channel metal oxide semiconductor) tubes and two NMOS (N-channel metal oxide semiconductor) tubes;
the first level shift unit comprises PMOS tubes PM1 and PM2 and NMOS tubes NM5 and NM6, the source of the PMOS tube PM1 is connected with the source of the PMOS tube PM2 and VDD, the gate of the PMOS tube PM1 is connected with the drain of the PMOS tube PM2 and the drain of the NMOS tube NM6 and serves as the output end of the first level shift unit, the output signal is EVEN _ SW, the gate of the PMOS tube PM2 is connected with the drain of the PMOS tube PM1 and the drain of the NMOS tube NM5, the gate of the NMOS tube NM5 is the output signal EVEN of the NAND gate 2 in the logic sequence circuit, the source of the NMOS tube NM5 is connected with the source of the NMOS tube NM6 and grounded, and the gate of the NMOS tube NM6 is the output signal EVEN _ N of the other input end of the first level shift unit after the output signal EVEN passes through the inverter 4;
the second level shift unit comprises PMOS transistors PM100 and PM200 and NMOS transistors NM500 and NM600, the source of the PMOS transistor PM100 and the source of the PMOS transistor PM200 are interconnected and VDD is connected, the gate of the PMOS transistor PM100 is connected to the drain of the PMOS transistor PM200 and the drain of the NMOS transistor NM600 and serves as the output end of the second level shift unit, the output signal is ODD _ SW, the gate of the PMOS transistor PM200 is connected to the drain of the PMOS transistor PM00 and the drain of the NMOS transistor NM500, the gate of the NMOS transistor NM500 is the input end of the second level shift unit and is connected to the output signal ODD of the NAND gate 1 in the logic sequence circuit, the source of the NMOS transistor NM500 and the source of the NMOS transistor NM600 are interconnected and grounded, and the gate of the NMOS transistor NM600 is the output signal ODD _ N obtained by connecting the output signal ODD to the other input end of the second level shift unit through the inverter INV 3.
The disconnection detection circuit is provided with disconnection detection units and a disconnection detection signal output unit, the number of the disconnection detection units corresponds to the number of the battery sections, and each disconnection detection unit comprises three resistors, a comparator, two NMOS (N-channel metal oxide semiconductor) tubes and a PMOS (P-channel metal oxide semiconductor) tube. Starting from a first battery, connecting one end of a first resistor, one end of a second resistor, a power supply end of a comparator and a source electrode of a PMOS (P-channel metal oxide semiconductor) tube with the positive voltage of the battery, connecting the other end of the first resistor with the drain electrode of a first NMOS (N-channel metal oxide semiconductor) tube, connecting the grid electrode of the first NMOS tube with an output signal ODD _ SW of a second level shifting unit, connecting the other end of the second resistor with one end of a third resistor and the negative input end of the comparator, connecting the positive input end of the comparator with reference voltage, connecting the other end of the third resistor with the grounding end of the comparator and the source electrode of the first NMOS tube and with the positive voltage of the next battery, connecting the output of the comparator with the grid electrode of the PMOS tube, connecting the drain electrode of the PMOS tube with the drain electrode of a second NMOS tube and serving as the output end of the battery disconnection detecting unit, connecting the grid electrode of the second NMOS tube; the second battery, the third battery … and so on, but it should be noted that the gate of the first NMOS tube in the ODD battery disconnection detection circuit is connected to the output signal ODD _ SW of the second level shift unit, the gate of the first NMOS tube in the EVEN battery disconnection detection circuit is connected to the output signal EVEN _ SW of the first level shift unit, that is, the gate of the first NMOS tube in the ODD battery disconnection detection circuit shares the ODD _ SW detection signal, the gate of the first NMOS tube in the EVEN battery disconnection detection circuit shares the EVEN _ SW detection signal, and the other end of the third resistor in the last battery disconnection detection circuit is connected to the ground terminal of the comparator and the source of the first NMOS tube and is grounded to VSS;
the disconnection detection signal output unit is internally provided with NMOS tubes and PMOS tubes, the number of the NMOS tubes is the same as that of the battery sections and the number of the disconnection detection circuits, the grid electrodes of the NMOS tubes are respectively and correspondingly connected with the output signals of the battery disconnection detection units in sequence, the source electrodes of the NMOS tubes are connected together and grounded to VSS, the drain electrodes of the NMOS tubes are connected together and connected with the drain electrodes of the PMOS tubes to serve as the disconnection detection signal output end of the disconnection detection circuits, the charge control terminal COUT and the discharge control terminal DOUT of the protection chip IC are connected, the grid electrodes of the PMOS tubes are connected with bias voltage, and the source electrodes of the PMOS tubes are connected with VDD.
The power supply of the protection chip can adopt 5 lithium batteries.
The invention has the following advantages and beneficial effects: in the application of multi-lithium battery protection, when the connection line between the battery and the protection chip is disconnected, the system can detect the state, stop the charging or discharging of the battery pack, prevent potential safety hazards caused by the overcharge or the overdischarge of the battery, and improve the safety and the reliability of the system.
Drawings
FIG. 1 is a simplified application diagram of a multi-cell lithium battery protection system;
FIG. 2 is a block diagram of the disconnection detection system of the present invention;
FIG. 3 is a circuit diagram of the logic sequence in the disconnection detection system of the present invention;
FIG. 4a is a level shifting circuit diagram of the disconnection detection system of the present invention;
FIG. 4b is another level shifting circuit diagram of the disconnection detection system of the present invention;
FIG. 5 is a circuit diagram of the disconnection detection circuit in the disconnection detection system of the present invention;
FIG. 6 is a first timing diagram for detection according to the present invention;
FIG. 7 is a second timing diagram of the detection according to the present invention.
Detailed Description
Fig. 1 is a simplified application diagram of a known 5-cell lithium-ion battery protection system. The battery charging and discharging circuit comprises a lithium battery 1, a lithium battery 2, a lithium battery 3, a lithium battery 4, a lithium battery 5, a Zener diode ZD1 and a resistor RVC1、RVC2、RVC3、RVC4、RVC5、RVDD、RSE、RSENS、RDRAIN、RCO1、RCO2、RVMPCapacitor CVC1、CVC2、CVC3、CVC4、CVC5、CVDDNMOS transistors NM1, NM2, NM3 and a protection chip IC, a capacitor C is connected to a VDD (power supply terminal) port of the protection chip ICVDDOne end of ZD1 positive electrode, resistance RVDDOne terminal of (C), a capacitorVDDThe other end of ZD1 is grounded, and the resistance RVDDThe other end of the protection chip is connected with the anode of the lithium battery 1 and PB + (charger and load anode), and the VC1 (voltage monitoring terminal of the battery 1) port of the protection chip IC is connected with a capacitor CVC1And a resistor RVC1One terminal of (C), a capacitorVC1The other end of the resistor is connected with VC2 (voltage monitoring terminal of battery 2) of the protection chip IC, and a resistor RVC1The other end of the protective chip is connected with the anode of the lithium battery 1, and a VC2 (a voltage monitoring terminal of the battery 2) port of the protective chip IC is connected with a capacitor CVC2And a resistor RVC2One terminal of (C), a capacitorVC2The other end of the resistor is connected with VC3 (voltage monitoring terminal of battery 3) of the protection chip IC, and a resistor RVC2The other end of the battery is connected with the anode of the lithium battery 2 and the cathode of the lithium battery 1, and VC3 of a chip IC is protected (voltage monitoring of the battery 3)Test terminal) port connection capacitor CVC3And a resistor RVC3One terminal of (C), a capacitorVC3The other end of the resistor is connected with VC4 (voltage monitoring terminal of battery 4) of the protection chip IC, and a resistor RVC3The other end of the protection chip is connected with the anode of the lithium battery 3 and the cathode of the lithium battery 2, and the VC4 (voltage monitoring terminal of the battery 4) port of the protection chip IC is connected with a capacitor CVC4And a resistor RVC4One terminal of (C), a capacitorVC4The other end of the resistor is connected with VC5 (voltage monitoring terminal of battery 5) of the protection chip IC, and a resistor RVC4The other end of the protection chip is connected with the anode of the lithium battery 4 and the cathode of the lithium battery 3, and the VC5 (the voltage monitoring terminal of the battery 5) port of the protection chip IC is connected with a capacitor CVC5And a resistor RVC5One terminal of (C), a capacitorVC5The other end of the resistor R is connected with VSS (chip ground) of the protection chip ICVC5The other end of the resistor is connected with the anode of the lithium battery 5 and the cathode of the lithium battery 4, the cathode of the battery 5 is connected with VSS, and the resistor R of the protection chip ICSENSOne end is connected with VSS and the other end is connected with RSEAnd NM1 source stage, RSEThe other end is connected with SENS (current detection terminal) of the protection chip IC, the gate of NM1 is connected with DOUT (discharge control terminal) of the protection chip IC, the drain of NM1 is connected with the drain of NM2 and the resistor RDRAINOne end of (A) RDRAINThe other end of NM3 is connected with a DRAIN of NM3, a source of NM3 is connected with VSS, a grid is connected with DRAIN (over-current protection release terminal) of a protection chip IC, and a grid of NM2 is connected with a resistor RCO1One terminal, resistor RCO2One terminal, resistance RCO1The other end is connected with COUT (charge control terminal) of the protection chip IC, and resistor RCO2The other end is connected with NM2 source stage, RVMPOne end and PB- (charger, load negative), RVMPThe other end is connected to a VMP (charger, load detection terminal) of the protection chip IC.
If the disconnection protection is not provided, when the battery is in a normal state, for example, VSS is 0V, VC5 is 3.5V, VC4 is 7.0V, VC3 is 10.5V, VC2 is 14.0V, VC1 is 17.5V, and VDD is 17.5V, normal charging and discharging can be performed, when the system is charging, if the disconnection occurs, the battery voltage can be charged to a very high potential and is easy to explode because the disconnection detection circuit is not provided, if the disconnection occurs, the battery voltage can not be correctly monitored in real time by the system because the disconnection detection circuit is not provided, the battery voltage can be discharged to a very low potential, damage is caused to the battery, and the service life of the battery is reduced.
As shown in fig. 2, the disconnection detection system of the present invention includes a logic sequence circuit, a level shift circuit and a disconnection detection circuit, which are connected in sequence, the logic sequence circuit generates initial disconnection detection sequence signals ODD, ODD _ N, EVEN and EVEN _ N and outputs them to the level shift circuit, the final disconnection detection sequence signals ODD _ SW and EVEN _ SW obtained by the level shift circuit are transmitted to the disconnection detection circuit, when any battery is disconnected, the disconnection protection control signal OUT output by the disconnection detection circuit controls the output of the charging control terminal COUT and the discharging control terminal DOUT of the protection chip IC, so as to realize the charging and discharging protection of the system in the disconnection state.
As shown in fig. 3, in the logic timing circuit, the upper plate of a capacitor C1 is connected with a current source, a positive input end of a comparator COMP1, a positive input end of a COMP2 and a drain of NM4, the lower plate of the capacitor C1 and a source of NM4 are grounded VSS, a negative input end of COMP1 is connected with a reference voltage Vstart, an output signal of COMP1 is connected with an input of an inverter INV1 and a B input end of a NAND gate NAND1 and an a input end of a NAND gate 2, a negative input end of COMP2 is connected with a reference voltage Vend, an output of COMP2 is connected with a gate of NM4, an output of INV1 is connected with a D flip-flop clock CLK, an output end Q of a D flip-flop is connected with an input end D, and is connected with an input end of an inverter INV2 and an a input end of a NAND gate 1, an output signal of an inverter INV2 is connected with a B input end of a NAND gate 2, an output signal of an inverter 1 outputs an ODD signal and is connected with an input of an inverter 86 3, an output.
The level shift circuit comprises two level shift units with the same structure, wherein each level shift unit comprises two PMOS (P-channel metal oxide semiconductor) tubes and two NMOS (N-channel metal oxide semiconductor) tubes;
FIG. 4a shows a first level shift unit, wherein the sources of PM1 and PM2 are connected to VDD, the drain of PM1 is connected to the gate of PM2 and the drain of NM5, the gate of NM5 is connected to the EVEN signal, the source of NM5 and the source of NM6 are connected to VSS, the gate of PM1, the drain of PM2 and the drain of NM6 are connected together to output signal EVEN _ SW, and the gate of NM6 is connected to the inverted signal EVEN _ N of EVEN, so as to shift the levels of input signals EVEN and EVEN _ N to output signal EVEN _ SW.
FIG. 4b shows a second level shift unit, in which the sources of PM100 and PM200 are connected to VDD, the drain of PM100 is connected to the gate of PM200 and the drain of NM500, the gate of NM500 is connected to the ODD signal, the sources of PM100 and NM600 are connected to VSS, the gates of PM100, PM200 and NM600 are connected to the output signal ODD _ SW, and the gate of NM6 is connected to the inverse signal ODD _ N of ODD, so as to shift the level of the input signal ODD, ODD _ N to the output signal ODD _ SW.
Taking the shift of the ODD _ SW as an example, when the input ODD signal is at a low level, the ODD _ N signal is at a high level (3.7V), and the output ODD _ SW signal is at a low level, and when the ODD signal is at a high level (3.7V), the ODD _ N signal is at a low level, and the output ODD _ SW signal is at a high level (VDD level), so that the level shift is realized, and the shift of the EVEN _ SW is similar to this.
Referring to fig. 5, taking 5 batteries as an example, the disconnection detecting circuit is provided with 5 disconnection detecting units and a disconnection detecting signal output unit, wherein the number of the disconnection detecting units corresponds to the number of the batteries, and each disconnection detecting unit comprises three resistors, a comparator, two NMOS transistors and a PMOS transistor.
The broken line detection unit of the first battery comprises resistors R1, R2 and R3, a comparator COMP3, a PMOS tube PM3 and NMOS tubes NM7 and NM8, one end of a resistor R1 is connected with one end of a resistor R2 and the power supply end of the comparator COMP3 and the source of the PMOS tube PM3 and is connected with the positive electrode voltage VC1 of the first battery, the other end of the resistor R1 is connected with the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 is connected with the output signal ODD _ SW of the second level shift unit, the other end of the resistor R1 is connected with the negative input end of the comparator COMP1 and one end of the resistor R1, the positive input end of the comparator COMP1 is connected with the reference voltage VREF1, the other end of the resistor R1 is connected with the source of the NMOS tube NM1 and the grounding end of the comparator COMP1 and is connected with the positive electrode voltage VBS 1 of the second battery, the output end of the PMOS tube NM1 is connected with the gate of the PMOS tube PM1 and is used as the first broken line offset circuit VBS 1 of the PMOS tube PM1 and is connected, the source electrode of the NMOS tube NM8 is grounded VSS;
the disconnection detecting circuit of the second battery comprises resistors R4, R5 and R6, a comparator COMP4, a PMOS tube PM4 and NMOS tubes NM9 and NM10, one end of a resistor R4 is connected with one end of a resistor R5 and the power supply end of the comparator COMP4 and the source of the PMOS tube PM4 and is connected with the anode voltage VC2 of the second battery, the other end of the resistor R4 is connected with the drain of the NMOS tube NM4, the gate of the NMOS tube NM4 is connected with the output signal EVEN _ SW of the first level shift unit, the other end of the resistor R4 is connected with the negative input end of the comparator COMP4 and one end of the resistor R4, the positive input end of the comparator COMP4 is connected with the reference voltage VREF4, the other end of the resistor R4 is connected with the source of the NMOS tube NM4 and the grounding end of the comparator COMP4 and is connected with the anode voltage VC4 of the third battery, the output end of the PMOS tube NM4 is connected with the drain of the PMOS tube PM4 and is used as the second battery disconnection detecting circuit VBS 4, the drain of the PMOS tube PM4, and the second, the source electrode of the NMOS tube NM10 is grounded VSS;
the disconnection detecting circuit of the third cell comprises resistors R7, R8 and R9, a comparator COMP5, a PMOS tube PM5 and NMOS tubes NM11 and NM12, one end of a resistor R7 is connected with one end of a resistor R8, the power supply end of the comparator COMP5 and the source of the PMOS tube PM5 and is connected with the anode voltage VC3 of the third cell, the other end of the resistor R7 is connected with the drain of the NMOS tube NM11, the gate of the NMOS tube NM11 is connected with the output signal ODD _ SW of the second level shift unit, the other end of the resistor R8 is connected with the negative input end of the comparator COMP 8 and one end of the resistor R8, the positive input end of the comparator COMP 8 is connected with the reference voltage VREF 8, the other end of the resistor R8 is connected with the source of the NMOS tube NM8 and the grounding end of the comparator COMP 8 and is connected with the anode voltage VC 8 of the fourth cell, the output end of the PMOS tube NM8 is connected with the gate of the PMOS tube PM8 as the gate of the NMOS tube PM8, and the third cell VBS 8, the disconnection detecting circuit is, the source electrode of the NMOS tube NM12 is grounded VSS;
the disconnection detecting circuit of the fourth battery comprises resistors R10, R11 and R12, a comparator COMP6, a PMOS tube PM6 and NMOS tubes NM13 and NM14, one end of a resistor R10 is connected with one end of a resistor R11 and the power supply end of the comparator COMP6 and the source of the PMOS tube PM6 and is connected with an anode voltage VC4 of the fourth battery, the other end of the resistor R10 is connected with the drain of the NMOS tube NM10, the gate of the NMOS tube NM10 is connected with the output signal EVEN _ SW of the first level shifting unit, the other end of the resistor R10 is connected with the negative input end of the comparator COMP 10 and one end of the resistor R10, the positive input end of the comparator COMP 10 is connected with a reference voltage VREF 10, the other end of the resistor R10 is connected with the source of the NMOS tube NM10 and the grounding end of the comparator COMP 10 and is connected with the anode voltage VC 10 of the PMOS tube PM10, the output end of the PMOS tube NM10 is connected with the drain of the PMOS tube PM10 as a fourth battery disconnection detecting circuit, and the gate of the PMOS tube PM10 is connected with the drain of the NMOS, the source electrode of the NMOS tube NM14 is grounded VSS;
the disconnection detecting circuit of the fifth battery comprises resistors R13, R14 and R15, a comparator COMP7, a PMOS transistor PM7 and NMOS transistors NM15 and NM16, one end of a resistor R13 is connected with one end of a resistor R14 and the power supply end of a comparator COMP7 and the source of a PMOS transistor PM7 and is connected with the anode voltage VC5 of the fifth battery, the other end of the resistor R13 is connected with the drain of an NMOS transistor NM15, the gate of the NMOS transistor NM15 is connected with the output signal ODD _ SW of the second level shift unit, the other end of the resistor R14 is connected with the negative input end of the comparator COMP 14 and one end of the resistor R14, the positive input end of the comparator COMP 14 is connected with a reference voltage VREF 14, the other end of the resistor R14 is connected with the source of the NMOS transistor NM14 and the ground, the output end of the comparator COMP 14 is connected with the gate of the PMOS transistor NM14 and is used as the disconnection detecting circuit of the PMOS transistor PM 14, and the drain of the PMOS transistor VBIAS 14 is connected with the output terminal of the second battery. The source electrode of the NMOS tube NM16 is grounded VSS;
the disconnection detection signal output unit comprises five NMOS transistors of NM17, NM18, NM19, NM20 and NM21 and a PMOS transistor PM8, the drains of the NMOS transistors NM17, NM18, NM19, NM20 and NM21 are connected with the drain of the PMOS transistor PM8 and are used as a disconnection detection signal output end OUT of the whole disconnection detection circuit to be connected with a charge control terminal COUT and a discharge control terminal DOUT of a protection chip, the gate of the PMOS transistor PM8 is connected with a bias voltage VBIASP, the source of the PMOS transistor PM8 is connected with a VDD, and the sources of the NMOS transistors NM17, NM18, NM19, NM20 and NM21 are connected together and grounded.
If the system of the invention is added to fig. 1, the principle and process of the disconnection protection are as follows: when the battery is in a normal state, for example, VSS is 0V, VC5 is 3.5V, VC4 is 7.0V, VC3 is 10.5V, VC2 is 14.0V, VC1 is 17.5V, and VDD is 17.5V, the internal circuit starts to operate, and can perform normal charging and discharging, an internal low voltage supply voltage VCC is generated, 3.7V is output to supply power to the low voltage module, a reference bias current starts to be established, the logic sequence circuit module current starts to charge the capacitor C1, once the C1 voltage exceeds the COMP1 negative input reference voltage Vstart, the COMP1 output signal changes from 0 to a high level (VCC level), the disconnection detection is started until the C1 voltage exceeds the COMP2 negative reference voltage Vend, the COMP2 output is turned to a high level (VCC level), the NMOS tube NM4 is started to reset the C1 voltage to 0, a new disconnection detection is started, and the effective detection time difference between the C36 1 and the ground detection can be determined. The COMP1 output signal is processed by a D flip-flop and a related logic circuit to obtain disconnection detection timing signals ODD, ODD _ N, EVEN, and EVEN _ N, since the supply voltage here is VCC of low voltage of 3.7V, and the highest voltage of the battery is 17.5V at this time, the signals need to be converted by a level shift circuit, the obtained ODD _ SW and EVEN _ SW are final disconnection detection timing signals, VSS voltage is output at low level, VDD voltage is output at high level, wherein the battery 1, the battery 3, and the battery 5 share an ODD _ SW detection signal, and the battery 2 and the battery 4 share an EVEN _ SW detection signal. As shown in fig. 5, the connection line between the battery and the protection board is not broken in the normal state, EVEN _ SW and ODD _ SW are at low level at the beginning, the low impedance paths NMOS NM7, NM9, NM11, NM13 and NM15 between the battery 1, the battery 2, the battery 3, the battery 4 and the battery 5 are closed, the voltage of each battery is kept unchanged, then EVEN _ SW and ODD _ SW are alternately opened, the corresponding low impedance path MOS is opened, however, the battery and the protection board are connected perfectly, the voltage is not changed, the charging and discharging can be normally carried out, and when the connection line between the battery and the protection board is broken. Taking the fifth battery VC5 as an example of the occurrence of a wire break, waiting for the arrival of a corresponding wire break detection timing sequence after the wire break occurs, when EVEN _ SW is at a high level (VDD potential), NM13 is turned on, and forms a low impedance path with R10, since the battery 4 is connected perfectly, the battery 5 is disconnected, the voltage of VC5 is pulled up to a voltage close to VC4, when the voltage of VC5 exceeds a certain value, the voltage of R14 and R15 is divided to exceed a reference voltage VREF5, the output of a comparator COMP7 is inverted, the level of VC5 jumps to a VSS level, PMOS PM7 is turned on, the output of OUT5 is inverted, the level jumps to a VC5 level from the VSS level, corresponding to NMOS NM21 is turned on, an output signal OUT jumps from a VCC high level to the VSS level, and after related logic processing, COUT and DOUT outputs in the multi-node protection system in fig. 1 are controlled to be at a low level, charging/discharging NM2 and discharging 1 are turned off, thereby closing a corresponding charging/discharging loop and realizing the wire.
The transmission process of the disconnection detection signal is as follows: after each battery voltage is normally electrified, the reference voltage, the bias voltage and the current source start to normally work, the logic sequence starts to work, and output signals ODD, ODD _ N, EVEN and EVEN _ N, wherein ODD and ODD _ N are reverse signals, EVEN and EVEN _ N are reverse signals, the upper 4 signals are transmitted to a level shift circuit (2 same module circuits) to obtain level shift output signals ODD _ SW and EVEN _ SW, the upper 2 signals are transmitted to a disconnection detection circuit to detect whether each battery is in a disconnection state, and an output signal OUT of the disconnection detection circuit controls COUT and DOUT terminals of a protection chip IC to output after logic processing, so that charging and discharging protection of a system in the disconnection state is realized.
The broken line detection process is as follows: in the normal state, the connection between the battery and the protection board is not broken, in the disconnection detection circuit, EVEN _ SW and ODD _ SW are at low level at the beginning, the low impedance paths NMOS NM7, NM9, NM11, NM13 and NM15 between the battery 1, the battery 2, the battery 3, the battery 4 and the battery 5 are closed, the voltage of each battery is kept unchanged, then EVEN _ SW and ODD _ SW are alternately opened, the corresponding low impedance path MOS is opened, however, the battery and the protection board are well connected, the voltage is not changed, the charging and discharging can be normally carried out, when the connection between the battery and the protection board is broken, taking the fifth battery VC5 as an example, the disconnection occurs, the corresponding disconnection detection time sequence is waited to come after the disconnection occurs, when EVEN _ SW is at high level (VDD potential), NM13 is opened, and R10 forms a low impedance path, since the battery 4 is well connected, the connection between the battery 5 is broken, the voltage of 5 is pulled up to a voltage lower than VC4, when the voltage of VC5 exceeds a certain value, the divided voltage of R14 and R15 exceeds VREF5, the output of a comparator COMP7 is inverted, the level of VC5 jumps to the VSS level, PMOS PM7 is started, the output of a drain electrode is inverted, the level of VSS jumps to the level of VC5, NMOS NM21 is started, an output signal OUT jumps to the VSS level from the level of VDD, after logic signal processing, the charging control COUT and the discharging control DOUT of the protection chip IC are finally closed, and charging and discharging of the system are stopped.
As shown in fig. 6, the voltage of the CT1 is periodically increased or decreased, and the disconnection-detection low-voltage timing signals EVEN, EVEN _ SW, ODD, and ODD _ N are obtained through logic processing, and the signals are converted into signals EVEN _ SW and ODD _ SW after level shifting, so as to periodically open or close the disconnection-detection branch.
As shown in fig. 7, when a disconnection occurs at VC5 and a corresponding disconnection detection signal arrives, the low impedance disconnection detection branch is turned on, at this time, VC4 is not disconnected, the voltage remains constant, the VC5 potential is pulled up to VC4 potential, which is detected by the internal VC5 disconnection detection circuit, and finally logic processing makes the output signal OUT in fig. 5 change from high level to low level, which controls COUT and DOUT outputs in the multi-section lithium battery protection system of fig. 1 to change to low level after the signal logic processing, and turns off the charge and discharge mosmm 2 and NM1, thereby turning off the system charge and discharge loop, ensuring the safety of the system and improving the reliability of the system.

Claims (5)

1. The utility model provides a broken string detecting system for multisection lithium cell protection chip, the power supply of protection chip is 4 section lithium cell at least, its characterized in that: the disconnection detection system comprises a logic time sequence circuit, a level shift circuit and a disconnection detection circuit which are connected in sequence, wherein the logic time sequence circuit generates an initial disconnection detection time sequence signal and outputs the initial disconnection detection time sequence signal to the level shift circuit, the final disconnection detection time sequence signal is obtained after the level shift circuit and is transmitted to the disconnection detection circuit, the disconnection detection circuit is provided with a number of disconnection detection units corresponding to the number of battery nodes, each detection unit corresponds to one output signal, the output signals of the disconnection detection units are respectively input to the disconnection detection signal output unit, the disconnection detection signal output unit connects the output control signals with a charge control terminal COUT and a discharge control terminal DOUT of a protection chip IC, when disconnection protection does not occur in a normal state, the charge control terminal COUT and the discharge control terminal DOUT output high levels, a charge-discharge NMOS pipe controlled correspondingly is opened, and normal charge and discharge can be carried out, when any battery is disconnected, the output control signal of the disconnection detection signal output unit controls the charge control terminal COUT and the discharge control terminal DOUT to output low level, and the correspondingly controlled charge and discharge NMOS tube is closed, so that the charge and discharge protection of the system in the disconnection state is realized.
2. The system of claim 1, wherein the system further comprises:
the logic sequential circuit comprises an NMOS tube NM4, comparators COMP1 and COMP2, inverters INV1, INV2, INV3 and INV4, NAND gates 1 and1, a D flip-flop DFF, a capacitor C1 and a current source; the positive end of the current source is connected with VCC, the negative end of the current source is connected with one end of a capacitor C1, the drain of an NMOS tube NM4, the positive end of a comparator COMP1 and the positive end of a comparator COMP2, the other end of the capacitor C1 is connected with the source of an NMOS tube NM4 and is grounded, the negative end of the comparator COMP1 is connected with a reference voltage Vstart, the negative end of the comparator COMP2 is connected with a reference voltage Vend, the output of the comparator COMP1 is connected with the input of an inverter INV1, the input B of a NAND gate 1 and the input A of a NAND gate 2, the output of an inverter INV1 is connected with the clock terminal CLK of a D flip-flop DFF, the output Q of the D flip-flop DFF is connected with the input end D2 and the other input A of the NAND gate 1, the output of the comparator COMP2 is connected with the gate of the NMOS tube NM4, the output of the inverter 46INV 45 is connected with the other input B of the NAND gate 3, the output of the NAND gate INV 573 is, an output signal EVEN of the NAND gate NAND2 is connected to an input of the inverter INV4, and the inverter INV4 outputs a signal EVEN _ N.
3. The system of claim 1, wherein the system further comprises:
the level shift circuit comprises two level shift units with the same structure, wherein each level shift unit comprises two PMOS (P-channel metal oxide semiconductor) tubes and two NMOS (N-channel metal oxide semiconductor) tubes;
the first level shift unit comprises PMOS tubes PM1 and PM2 and NMOS tubes NM5 and NM6, the source of the PMOS tube PM1 is connected with the source of the PMOS tube PM2 and VDD, the gate of the PMOS tube PM1 is connected with the drain of the PMOS tube PM2 and the drain of the NMOS tube NM6 and serves as the output end of the first level shift unit, the output signal is EVEN _ SW, the gate of the PMOS tube PM2 is connected with the drain of the PMOS tube PM1 and the drain of the NMOS tube NM5, the gate of the NMOS tube NM5 is the output signal EVEN of the NAND gate 2 in the logic sequence circuit, the source of the NMOS tube NM5 is connected with the source of the NMOS tube NM6 and grounded, and the gate of the NMOS tube NM6 is the output signal EVEN _ N of the other input end of the first level shift unit after the output signal EVEN passes through the inverter 4;
the second level shift unit comprises PMOS transistors PM100 and PM200 and NMOS transistors NM500 and NM600, the source of the PMOS transistor PM100 and the source of the PMOS transistor PM200 are interconnected and VDD is connected, the gate of the PMOS transistor PM100 is connected to the drain of the PMOS transistor PM200 and the drain of the NMOS transistor NM600 and serves as the output end of the second level shift unit, the output signal is ODD _ SW, the gate of the PMOS transistor PM200 is connected to the drain of the PMOS transistor PM00 and the drain of the NMOS transistor NM500, the gate of the NMOS transistor NM500 is the input end of the second level shift unit and is connected to the output signal ODD of the NAND gate 1 in the logic sequence circuit, the source of the NMOS transistor NM500 and the source of the NMOS transistor NM600 are interconnected and grounded, and the gate of the NMOS transistor NM600 is the output signal ODD _ N obtained by connecting the output signal ODD to the other input end of the second level shift unit through the inverter INV 3.
4. The system of claim 1, wherein the system further comprises:
the disconnection detection circuit is provided with disconnection detection units and a disconnection detection signal output unit, the number of the disconnection detection units corresponds to the number of the battery sections, each disconnection detection unit comprises three resistors, a comparator, two NMOS tubes and a PMOS tube, from the first battery, one end of a first resistor, one end of a second resistor, a power supply end of the comparator and a source electrode of the PMOS tube are connected with the positive voltage of the battery, the other end of the first resistor is connected with a drain electrode of the first NMOS tube, a grid electrode of the first NMOS tube is connected with an output signal ODD _ SW of a second level shifting unit, the other end of the second resistor is connected with one end of a third resistor and a negative input end of the comparator, a positive input end of the comparator is connected with a reference voltage, the other end of the third resistor is connected with a grounding end of the comparator and a source electrode of the first NMOS tube and is connected with the positive voltage of the next battery, an output of the comparator is connected with the grid electrode of the PMOS tube, the drain electrode of the PMOS tube is connected with the drain electrode of the second NMOS tube and serves as the output end of the battery disconnection detection unit, the grid electrode of the second NMOS tube is connected with the configuration voltage, and the source electrode of the second NMOS tube is grounded VSS; the second battery, the third battery … and so on, but it should be noted that the gate of the first NMOS tube in the ODD battery disconnection detection circuit is connected to the output signal ODD _ SW of the second level shift unit, the gate of the first NMOS tube in the EVEN battery disconnection detection circuit is connected to the output signal EVEN _ SW of the first level shift unit, that is, the gate of the first NMOS tube in the ODD battery disconnection detection circuit shares the ODD _ SW detection signal, the gate of the first NMOS tube in the EVEN battery disconnection detection circuit shares the EVEN _ SW detection signal, and the other end of the third resistor in the last battery disconnection detection circuit is connected to the ground terminal of the comparator and the source of the first NMOS tube and is grounded to VSS;
the disconnection detection signal output unit is internally provided with NMOS tubes and PMOS tubes, the number of the NMOS tubes is the same as that of the battery sections and the number of the disconnection detection circuits, the grid electrodes of the NMOS tubes are respectively and correspondingly connected with the output signals of the battery disconnection detection units in sequence, the source electrodes of the NMOS tubes are connected together and grounded to VSS, the drain electrodes of the NMOS tubes are connected together and connected with the drain electrodes of the PMOS tubes to serve as the disconnection detection signal output end of the disconnection detection circuits, the charge control terminal COUT and the discharge control terminal DOUT of the protection chip IC are connected, the grid electrodes of the PMOS tubes are connected with bias voltage, and the source electrodes of the PMOS tubes are connected with VDD.
5. The system of claim 1, wherein the system further comprises: the power supply of the protection chip IC adopts 5 lithium batteries.
CN202010737795.XA 2020-07-28 2020-07-28 A broken string detecting system for multisection lithium cell protection chip Pending CN111693901A (en)

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CN113848491A (en) * 2021-08-12 2021-12-28 深圳市创芯微微电子有限公司 Multi-battery disconnection detection circuit and battery protection circuit board
CN114217203A (en) * 2021-11-17 2022-03-22 深圳市创芯微微电子有限公司 Battery protection chip and test system
CN114744731A (en) * 2022-05-17 2022-07-12 上海摩芯半导体技术有限公司 Charger detection circuit for battery protection chip for different-port application

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