CN114217203A - Battery protection chip and test system - Google Patents
Battery protection chip and test system Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/385—Arrangements for measuring battery or accumulator variables
- G01R31/386—Arrangements for measuring battery or accumulator variables using test-loads
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application relates to the technical field of battery testing, and provides a battery protection chip and a testing system. The chip includes: the power supply end of the chip is connected with the first end of the first test mode signal generating circuit, the positive sampling end of the battery voltage is connected with the second end of the first test mode signal generating circuit, and the output end of the first test mode signal generating circuit is connected with the first input end of the driving circuit; the positive battery voltage sampling end is connected with the first end of the second test mode signal generating circuit, the negative battery voltage sampling end is connected with the second end of the second test mode signal generating circuit, and the output end of the second test mode signal generating circuit is connected with the second input end of the driving circuit; the output end of the timer is connected with the third input end of the driving circuit, the input end of the timer is connected with the timing signal output end of the driving circuit, and the control mode total signal output end of the driving circuit is used for being connected to the chip test mode signal end.
Description
Technical Field
The application relates to the technical field of battery testing, in particular to a battery protection chip and a testing system.
Background
In a multi-section battery protection chip, functional items are often very many, and mainly include open short circuit, power consumption, overcharge protection, overcharge recovery, overdischarge protection, overdischarge recovery, overcurrent protection, short circuit protection, overcurrent recovery, charging overcurrent protection, charging overcurrent recovery, disconnection protection, temperature recovery and the like, detection and judgment delays of various related functions are very long, and the maximum test duration of a single functional item can reach tens of seconds, so that the time for normally testing the chip is very long, the test efficiency is low, the test cost is very high, the mass production output is very slow, and various links such as product delivery are influenced.
As shown in fig. 1, a general n-cell battery protection chip system, VCC is a chip power supply terminal, VC 1-VCn (n > -2) is a battery voltage sampling terminal, VSS is a chip ground, VM is a charger load detection terminal, RTV and RTS are temperature detection terminals, VIN is a charging/discharging current detection terminal, CO is a charging control terminal, and DO is a discharging control terminal, in order to shorten the test time, the chip design is generally extended by using the original function terminals of the chip, so that the chip enters the test mode, after the chip enters the test mode, the delay of each function is shortened to several milliseconds from tens, hundreds, even thousands of milliseconds originally designed, and the whole test time is greatly shortened. It is therefore of great importance to design a reliable test pattern.
The principle of designing the test mode is to power up without affecting the application of normal functions, so that the chip enters the test mode, in the conventional scheme, the negative pressure of the VM detection terminal is used for judgment, and a test mode control signal is generated, as shown in fig. 2. The design method is simple, but the inventor researches and discovers that under certain application environments, such as the limit condition of large-current charging, namely the charging overcurrent state, the possibility of misjudgment exists, the VM can detect a large negative voltage, the chip can enter a test mode by misjudgment, and charging overcurrent protection delay is abnormal.
Disclosure of Invention
The application provides a battery protection chip and a test system, which are used for solving the limitation problem that the traditional scheme has misjudgment and enters a test mode.
A battery protection chip comprises a chip power supply end, a battery voltage positive sampling end, a battery voltage negative sampling end, a first test mode signal generating circuit, a second test mode signal generating circuit, a test mode total signal driving circuit and a timer;
the power supply end of the chip is connected with the first end of the first test mode signal generating circuit, the positive battery voltage sampling end is connected with the second end of the first test mode signal generating circuit, and the output end of the first test mode signal generating circuit is connected with the first input end of the test mode total signal driving circuit;
the positive battery voltage sampling end is connected with the first end of the second test mode signal generating circuit, the negative battery voltage sampling end is connected with the second end of the second test mode signal generating circuit, and the output end of the second test mode signal generating circuit is connected with the second input end of the test mode total signal driving circuit;
the output end of the timer is connected with the third input end of the test mode total signal driving circuit, the input end of the timer is connected with the timing signal output end of the test mode total signal driving circuit, and the control mode total signal output end of the test mode total signal driving circuit is used for being connected to the chip test mode signal end.
In one embodiment, the first test mode signal generating circuit includes a first resistor, a second resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a normal phase schmitt trigger;
one end of the first resistor is used as a first end of the first test mode signal generating circuit, the other end of the first resistor is connected to the drain electrode of the first PMOS tube, the grid electrode and the source electrode of the first PMOS tube are connected to the drain electrode of the second PMOS tube after being connected in common, the grid electrode and the drain electrode of the second PMOS tube are connected to the drain electrode of the third PMOS tube after being connected in common, and the grid electrode and the source electrode of the third PMOS tube are connected to the drain electrode of the fourth PMOS tube after being connected in common;
one end of the second resistor is used as a second end of the first test mode signal generating circuit, the other end of the second resistor is connected to a grid electrode of the fourth PMOS tube, a source electrode of the fourth PMOS tube is connected to a drain electrode of the first NMOS tube, a grid electrode of the first NMOS tube is connected to a low-voltage power supply voltage, a source electrode of the first NMOS tube, a drain electrode of the second NMOS tube and an output end of the normal phase Schmitt trigger are connected in common, a grid electrode of the second NMOS tube is connected to a bias voltage, and a source electrode of the second NMOS tube is connected to a chip grounding end;
and the output end of the normal phase Schmitt trigger is used as the output end of the first test mode signal generating circuit.
In one embodiment, the second test mode signal generating circuit includes a third resistor, a fourth resistor, a voltage comparator, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first inverter;
one end of the third resistor and one end of the fourth resistor are connected to the negative input end of the voltage comparator after being connected in common, the positive input end of the voltage comparator is connected to the reference voltage end, and the output end of the voltage comparator is connected to the grid electrode of the fifth PMOS tube; the other end of the third resistor and the drain electrode of the fifth PMOS tube are connected in common to be used as a first end of the second test mode signal generating circuit, and the other end of the fourth resistor is used as a second end of the second test mode signal generating circuit;
the source electrode of the fifth PMOS tube is connected to the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected to low-voltage power supply voltage, the source electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the input end of the first phase inverter are connected in common, the grid electrode of the fourth NMOS tube is connected to bias voltage, the source electrode of the fourth NMOS tube is connected to the ground end of a chip, and the output end of the first phase inverter is used as the output end of the second test mode signal generating circuit.
In one embodiment, the test mode total signal driving circuit comprises a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first nand gate, a second nand gate, an exclusive or gate, a nor gate, a D flip-flop and an oscillator;
the R end of the D flip-flop and the input end of the second inverter are connected in common to be used as a first input end of the test mode total signal driving circuit, and the output end of the second inverter is connected to the first output end of the NOR gate;
the input end of the third inverter and the second input end of the nor gate are connected in common to serve as the second input end of the test mode total signal driving circuit, the output end of the third inverter, the first input end of the first nand gate and the first input end of the exclusive-or gate are connected in common, and the second input end of the first nand gate serves as the third input end of the test mode total signal driving circuit;
the output end of the first NAND gate is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the clock end of the D flip-flop, the positive Q end of the D flip-flop is connected with the second input end of the XOR gate and serves as a chip test mode signal end of the test mode total signal driving circuit, and the D end of the D flip-flop is connected to a power supply end;
the output end of the exclusive-or gate is connected to the first input end of the second nand gate, the output end of the nor gate is connected to the second input end of the second nand gate, the output end of the second nand gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the input end of the oscillator, and the output end of the oscillator is used as the timing signal output end of the test mode total signal driving circuit.
A test system comprises a test battery and the battery protection chip.
In the scheme provided by the application, the chip can be controlled to enter the test mode by electrifying three terminals VCC, VC1 and VC2 of the original terminal of the chip, firstly, the voltage between VCC and VC1 is increased to be more than 5V, so that a first test signal 1 inside the chip is effective, then, the voltage higher than the excessive value is supplied between VC1 and VC2, so that a second test mode signal is generated inside the chip, at the moment, an internal timer is triggered to start timing, but after the timing reaches the designed Ttm delay, a total signal of the test mode is controlled to be effective, and finally, the chip is connected with a test mode end through the total signal of the test mode, so that the chip enters the test mode. Avoid under the extreme condition like heavy current charging through this application, the overcurrent state that charges promptly, can have the possibility of erroneous judgement, can make the effective accurate entering test mode of chip, greatly shorten test time, improve efficiency of software testing, reduce test cost, not only guarantee that the chip is not disturbed completely when normal application, effectively prevent the mistake and trigger the anomaly of getting into test mode, in addition, the negative pressure that can not make chip VM end makes the chip put the nothing recovery value excessively, other circumstances that influence the functional test, can guarantee after chip level survey gets into test mode, all functional items all can all cover the test comprehensively, use safe and reliable more, effectively promote the quality of product.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a conventional scheme of a structure of an n-cell battery protection chip system;
FIG. 2 is a schematic diagram of a control circuit for a chip to enter a test mode in a conventional scheme;
fig. 3 is a schematic diagram illustrating external connection of a battery protection chip provided in the present application;
fig. 4 is a schematic structural diagram of a battery protection chip provided in the present application;
fig. 5 is a schematic structural diagram of a first test mode signal generating circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a second test mode signal generating circuit according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a connection between a test mode total signal driving circuit and a timer according to an embodiment of the present application;
fig. 8 is a schematic timing diagram of a signal when the battery protection chip enters the test mode according to the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In order to explain the technical means of the present application, the following description will be given by way of specific examples.
As shown in fig. 3 and 4, fig. 3 is a schematic diagram of external connection of a battery protection chip provided in the present application, and fig. 4 is a schematic diagram of a structure of a battery protection chip provided in the present application, which includes a chip power supply terminal VCC, a battery voltage sampling terminal (VC 1-VCn (n > -2)), where the battery voltage sampling terminal includes a battery voltage positive sampling terminal and a battery voltage negative sampling terminal, where, for convenience of description, in all embodiments of the present application, a chip highest battery voltage positive sampling terminal VC1 and a chip highest battery voltage negative sampling terminal VC2 are taken as examples, and the first test mode signal generating circuit 101, the second test mode signal generating circuit 102, the test mode total signal driving circuit 103, and the timer 104 are described;
the chip power supply terminal VCC is connected to a first terminal of the first test mode signal generation circuit 101, the battery voltage positive sampling terminal VC1 is connected to a second terminal of the first test mode signal generation circuit 101, and an output terminal of the first test mode signal generation circuit 101 is connected to a first input terminal of the test mode total signal driving circuit 103;
the battery voltage positive sampling end VC1 is connected to the first end of the second test mode signal generating circuit 102, the battery voltage negative sampling end VC2 is connected to the second end of the second test mode signal generating circuit 102, and the output end of the second test mode signal generating circuit 102 is connected to the second input end of the test mode total signal driving circuit 103;
the output end of the timer 104 is connected to the third input end of the test mode total signal driving circuit 103, the input end of the timer 104 is connected to the timing signal output end of the test mode total signal driving circuit 103, and the control mode total signal output end of the test mode total signal driving circuit 103 is used for being connected to the chip test mode signal end.
The first test mode signal generating circuit 101 is controlled by a voltage between a chip power supply terminal VCC and a battery voltage positive sampling terminal VC1 to output a first test mode signal, which is at a high level (1) or a low level (0). Specifically, for example, when the predetermined voltage is 5V, the first test mode signal output by the first test mode signal generating circuit 101 is at a low level 0 when VCC-VC1 is less than 5V, and the first test mode signal output by the first test mode signal generating circuit 101 is at a high level 1 when VCC-VC1 is greater than or equal to 5.
In a specific embodiment, as shown in fig. 5, an embodiment of the present application provides a specific implementation of the first test mode signal generating circuit 101, where the first test mode signal generating circuit 101 includes a first resistor RQ, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, a second NMOS transistor NM2, and a normal phase schmitt;
one end of the first resistor R1 is used as a first end of the first test mode signal generating circuit 101, the other end of the first resistor R1 is connected to the drain of the first PMOS transistor PM1, the gate and the source of the first PMOS transistor PM1 are connected to the drain of the second PMOS transistor PM2 after being connected in common, the gate and the drain of the second PMOS transistor PM2 are connected to the drain of the third PMOS transistor PM3 after being connected in common, and the gate and the source of the third PMOS transistor PM3 are connected to the drain of the fourth PMOS transistor PM4 after being connected in common;
one end of the second resistor R2 is used as a second end of the first test mode signal generating circuit 101, the other end of the second resistor R2 is connected to the gate of the fourth PMOS transistor PM4, the source of the fourth PMOS transistor PM4 is connected to the drain of the first NMOS transistor NM1, the gate of the first NMOS transistor NM1 is connected to a low-voltage power supply voltage V _5V, the source of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2 and the output terminal of the normal phase smitter schmitt are connected in common, the gate of the second NMOS transistor NM2 is connected to a bias voltage VBN, and the source of the second NMOS transistor NM2 is connected to a chip ground terminal VSS; for example, the low voltage supply voltage V _5V may be an internal chip low voltage supply voltage, and the bias voltage VBN may be an internal chip bias voltage.
The output terminal of the normal phase schmitt trigger is used as the output terminal of the first test mode signal generating circuit 101.
In this embodiment, the first resistor R1 and the second resistor R2 are current-limiting protection resistors for preventing the internal devices of the chip from being damaged due to the overhigh voltage between the chip power supply terminal VCC and the battery voltage positive sampling terminal VC1, and the PMO transistors PM1 to PM3 are voltage control MOS for adjusting the judgment voltage between the chip power supply terminal VCC and the battery voltage positive sampling terminal VC 1. It should be noted that, in the example shown in fig. 5, 3 PMOS transistors are used to adjust the magnitude of the determination voltage, and in practical applications, other numbers of settings may be provided, which is not limited specifically.
V _5V is the chip internal low voltage supply voltage, VBN is the chip internal bias voltage, and is used for generating the pull-down bias current. Specifically, in a normal state, when VCC-VC1 is less than 5V, the PM4 of the fourth PMOS transistor remains off, and then the drain terminal of the second NMOS transistor NM2 is pulled down to the chip ground terminal VSS by the bias current controlled by the bias voltage VBN, and after passing through the normal phase schmitt trigger, the first test mode signal 1 is output as a low level 0; on the contrary, when VCC-VC1 is greater than or equal to 5V in the year, the PM4 of the fourth PMOS transistor is turned on, so the drain terminal of the second NMOS transistor NM2 is pulled up to high level and clamped, and after passing through the schmitt normal phase schmitt trigger, the first test mode signal output becomes high level 1.
It should be noted that the embodiment shown in fig. 5 is only an exemplary illustration, and based on the circuit structure, other transformation structures may also be provided, for example, types, numbers, or circuit modes of the switching devices may be changed, and the details are not limited.
The second test mode signal generating circuit 102 outputs a second test mode signal controlled by a voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2, and the first test mode signal is at a high level (1) or a low level (0). Specifically, for example, when the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 is a normal voltage, the second test mode signal output by the second test mode signal generation circuit 102 is at a high level 1, and when the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 is higher than the battery excessive value, the second test mode signal output by the second test mode signal generation circuit 102 is at a low level 0.
As shown in fig. 6, the second test mode signal generating circuit 102 includes a third resistor R3, a fourth resistor R4, a voltage comparator COMP, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a first inverter inv 1;
one end of the third resistor R3 and one end of the fourth resistor R4 are connected to the negative input end of the voltage comparator COMP after being connected together, the positive input end of the voltage comparator COMP is connected to a reference voltage end, the reference voltage end is used for providing a reference voltage Vref, in fig. 6, a reference voltage module is provided, the reference voltage module is connected in parallel between VC1 and VC2, and the output end of the voltage comparator COMP is connected to the gate of the fifth PMOS transistor PM 5; the other end of the third resistor R3 and the drain of the fifth PMOS transistor PM5 are commonly connected as the first end of the second test mode signal generating circuit 102, and the other end of the fourth resistor R4 is used as the second end of the second test mode signal generating circuit 102;
a source of the fifth PMOS transistor PM5 is connected to a drain of the third NMOS transistor NM3, a gate of the third NMOS transistor NM3 is connected to a low voltage supply voltage V _5V, a source of the third NMOS transistor NM3, a drain of the fourth NMOS transistor NM4 and an input terminal of the first inverter inv1 are connected in common, a gate of the fourth NMOS transistor NM4 is connected to a bias voltage VBN, a source of the fourth NMOS transistor NM4 is connected to a chip VSS ground terminal, and an output terminal of the first inverter inv1 serves as an output terminal of the second test mode signal generating circuit 102, wherein, for example, the low voltage supply voltage V _5V may be an on-chip low voltage supply voltage, and the bias voltage VBN may be an on-chip bias voltage.
The third resistor R3 and the fourth resistor R4 are voltage dividing resistors and are used for reducing the voltage between the battery voltage positive sampling end VC1 and the battery voltage negative sampling end VC2, and the reference voltage module is used for generating reference voltage Vref which is referenced to the battery voltage negative sampling end VC 2. When the voltage between VC1 and VC2 is normal voltage, that is, the divided voltage of the third resistor R3 and the fourth resistor R4 is smaller than Vref, at this time, the output of the comparator COMP is 1, and the fifth PMOS transistor PM5 is turned off, so that the drain terminal of the fourth NMOS transistor NM4 is pulled down to the chip ground terminal VSS by the bias current controlled by the programming voltage VBN, and after passing through the first inverter inv1, the second test mode signal is output as high level 1; when the voltages of the battery voltage positive sampling end VC1 and the battery voltage negative sampling end VC2 are higher than the battery excessive value, that is, the divided voltages of the third resistor R3 and the fourth resistor R4 are greater than the reference voltage Vref, the output of the comparator COMP is 0 at this time, so that the fifth PMOS transistor PM5 is turned on, and therefore the drain end of the fourth NMOS transistor NM4 is pulled up to a high level and clamped, and after passing through the first inverter inv1, the output of the second test mode signal is a low level 0.
It should be noted that the embodiment shown in fig. 5 is only an exemplary illustration, and based on the circuit structure, other conversion structures may also be provided, for example, voltage dividing circuits therein, types and numbers of switching devices therein may be changed, or other circuit manners may be replaced, and the details are not limited.
The test mode total signal driving circuit 103 outputs a test mode total signal, which is at a high level (1) or a low level (0), under control of the first test mode signal, the second test mode signal, and the output signal of the timer. In this embodiment, when the first test mode signal 1 is at low level 0, the test mode total signal output is at low level 0, when the first test mode signal 1 is at high level 1, and at this time, when the second test mode signal is at low level 0, the test mode total signal driving circuit 103 outputs a timing signal to drive the timer 104 to operate, and after the timer 104 times and delays for a preset time duration Ttm, the test mode total signal is inverted from low level 0 to high level 1, and the chip is triggered to enter the test mode.
In one embodiment, as shown in fig. 7, the present application provides a test mode total signal driving circuit, which includes a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a first Nand gate Nand2, a second Nand gate Nand2_2, an xor gate xor2, a nor gate nor2, a D flip-flop and an oscillator;
the R terminal of the D flip-flop is connected to the input terminal of the second inverter inv2 as the first input terminal of the test mode total signal driving circuit 103, and the output terminal of the second inverter inv2 is connected to the first output terminal of the nor gate nor 2;
an input terminal of the third inverter inv3 is commonly connected with a second input terminal of the nor gate nor2 as a second input terminal of the test mode total signal driving circuit 103, an output terminal of the third inverter inv3, a first input terminal of the first Nand gate Nand2 and a first input terminal of the xor gate xor2 are commonly connected, and a second input terminal of the first Nand gate Nand2 is commonly connected with a third input terminal of the test mode total signal driving circuit 103;
the output end of the first Nand gate Nand2 is connected to the input end of the fourth inverter inv4, the output end of the fourth inverter inv4 is connected to the clock end CLK of the D flip-flop, the positive Q end of the D flip-flop is connected to the second input end of the xor2 and serves as the chip test mode signal end of the test mode total signal driving circuit 103, the chip test mode signal end is used for outputting a test mode total signal, the D end of the D flip-flop is connected to a power supply terminal VDD, and the power supply terminal VDD can be a voltage provided inside a chip.
An output end of the xor gate xor2 is connected to a first input end of the second Nand gate Nand2_2, an output end of the nor gate nor2 is connected to a second input end of the second Nand gate Nand2_2, an output end of the second Nand gate Nand2_2 is connected to an input end of the fifth inverter inv5, an output end of the fifth inverter inv5 is connected to an input end of the oscillator, and an output end of the oscillator serves as a timing signal output end of the test mode total signal driving circuit 103 and is used for outputting a timing signal.
When the first test mode signal is at low level 0, the directly controlled D flip-flop is reset, and the positive Q output of the output terminal is at low level 0, i.e. the total test mode signal output is at low level 0. When the first test mode signal is at a high level 1, the directly controlled D flip-flop is active, and at this time, when the second test mode signal is at a low level 0, the two signals of the first and second test mode signals jointly enable the nor gate nor2 to output a high level 1, and the xor gate xor2 to output a high level 1, so that the second nand gate nand2_2 outputs a low level 0, and outputs a timing signal after passing through the fifth inverter inv5, for controlling the oscillator and the timer to operate, when the timer times to a delay time Ttm for entering the test mode, the clock terminal CLK of the D flip-flop is active, and triggers the output level of the positive Q terminal to flip, and the output level is flipped from the low level 0 to the high level 1, that is, the test mode total signal is flipped to the high level 1, so that the chip enters the test mode.
Referring to fig. 5, for the sake of understanding the operation timing, fig. 5 is a timing diagram of the signals in the present application, firstly, it must be ensured that the first test mode signal changes from high level 1 first to enable the D flip-flop to be effective, and secondly, the time for maintaining the high level 1 of the second test mode signal must be longer than the delay time Ttm to ensure that the time is enough to enter the test mode. When both conditions are satisfied, a test mode total signal is sent out to enter a test mode when the timing reaches Ttm, and after the test mode is entered, a second test mode signal is reset to a normal low level.
It can be seen that, in the embodiment of the present application, as shown in fig. 3, the chip may be controlled to enter the test mode only by powering up three terminals VCC, VC1, and VC2 (for example, an external voltage of V0-Vn in fig. 3), a voltage between VCC and VC1 is first increased to be greater than 5V to enable a first test signal 1 inside the chip to be valid, and then a voltage higher than the charged voltage is provided between VC1 and VC2 to enable a second test mode signal to be generated inside the chip, at this time, the internal timer 104 is triggered to start timing, but after the timing reaches a designed Ttm delay, the total test mode signal is controlled to be valid, and finally, the chip is connected to the test mode end through the total test mode signal to enable the chip to enter the test mode. Avoid under the extreme condition like heavy current charging through this application, the overcurrent state that charges promptly, can have the possibility of erroneous judgement, can make the effective accurate entering test mode of chip, greatly shorten test time, improve efficiency of software testing, reduce test cost, not only guarantee that the chip is not disturbed completely when normal application, effectively prevent the mistake and trigger the anomaly of getting into test mode, in addition, the negative pressure that can not make chip VM end makes the chip put the nothing recovery value excessively, other circumstances that influence the functional test, can guarantee after chip level survey gets into test mode, all functional items all can all cover the test comprehensively, use safe and reliable more, effectively promote the quality of product.
In an embodiment, there is also provided a test system, which includes a test battery and the battery protection chip as described in the previous embodiments.
It should be noted that, based on the battery protection chip provided in the embodiment of the present application, the control method of the test mode provided by the battery protection chip is applicable to a battery protection chip with n > -2 nodes, the determination voltage 5V for generating the first test mode signal in the above embodiment is not limited to 5V, and may be designed to be any voltage according to different practical applications, and is not specifically limited, and different voltage determinations may be implemented by adjusting the number of PMOS between VCC and VC1, and in addition, each initial logic level in the above test mode is not limited to an initial high or low, and may be changed to an initially opposite logic in this embodiment by adding a logic gate, and is not specifically limited.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (5)
1. A battery protection chip is characterized by comprising a chip power supply end, a battery voltage positive sampling end, a battery voltage negative sampling end, a first test mode signal generating circuit, a second test mode signal generating circuit, a test mode total signal driving circuit and a timer;
the power supply end of the chip is connected with the first end of the first test mode signal generating circuit, the positive battery voltage sampling end is connected with the second end of the first test mode signal generating circuit, and the output end of the first test mode signal generating circuit is connected with the first input end of the test mode total signal driving circuit;
the positive battery voltage sampling end is connected with the first end of the second test mode signal generating circuit, the negative battery voltage sampling end is connected with the second end of the second test mode signal generating circuit, and the output end of the second test mode signal generating circuit is connected with the second input end of the test mode total signal driving circuit;
the output end of the timer is connected with the third input end of the test mode total signal driving circuit, the input end of the timer is connected with the timing signal output end of the test mode total signal driving circuit, and the control mode total signal output end of the test mode total signal driving circuit is used for being connected to the chip test mode signal end.
2. The battery protection chip of claim 1, wherein the first test mode signal generating circuit comprises a first resistor, a second resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a normal phase schmitt trigger;
one end of the first resistor is used as a first end of the first test mode signal generating circuit, the other end of the first resistor is connected to the drain electrode of the first PMOS tube, the grid electrode and the source electrode of the first PMOS tube are connected to the drain electrode of the second PMOS tube after being connected in common, the grid electrode and the drain electrode of the second PMOS tube are connected to the drain electrode of the third PMOS tube after being connected in common, and the grid electrode and the source electrode of the third PMOS tube are connected to the drain electrode of the fourth PMOS tube after being connected in common;
one end of the second resistor is used as a second end of the first test mode signal generating circuit, the other end of the second resistor is connected to a grid electrode of the fourth PMOS tube, a source electrode of the fourth PMOS tube is connected to a drain electrode of the first NMOS tube, a grid electrode of the first NMOS tube is connected to a low-voltage power supply voltage, a source electrode of the first NMOS tube, a drain electrode of the second NMOS tube and an output end of the normal phase Schmitt trigger are connected in common, a grid electrode of the second NMOS tube is connected to a bias voltage, and a source electrode of the second NMOS tube is connected to a chip grounding end;
and the output end of the normal phase Schmitt trigger is used as the output end of the first test mode signal generating circuit.
3. The battery protection chip of claim 1, wherein the second test mode signal generating circuit comprises a third resistor, a fourth resistor, a voltage comparator, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first inverter;
one end of the third resistor and one end of the fourth resistor are connected to the negative input end of the voltage comparator after being connected in common, the positive input end of the voltage comparator is connected to the reference voltage end, and the output end of the voltage comparator is connected to the grid electrode of the fifth PMOS tube; the other end of the third resistor and the drain electrode of the fifth PMOS tube are connected in common to be used as a first end of the second test mode signal generating circuit, and the other end of the fourth resistor is used as a second end of the second test mode signal generating circuit;
the source electrode of the fifth PMOS tube is connected to the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected to low-voltage power supply voltage, the source electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the input end of the first phase inverter are connected in common, the grid electrode of the fourth NMOS tube is connected to bias voltage, the source electrode of the fourth NMOS tube is connected to the ground end of a chip, and the output end of the first phase inverter is used as the output end of the second test mode signal generating circuit.
4. The battery protection chip of any one of claims 1-3, wherein the test mode total signal driving circuit comprises a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, an XOR gate, a NOR gate, a D flip-flop, and an oscillator;
the R end of the D flip-flop and the input end of the second inverter are connected in common to be used as a first input end of the test mode total signal driving circuit, and the output end of the second inverter is connected to the first output end of the NOR gate;
the input end of the third inverter and the second input end of the nor gate are connected in common to serve as the second input end of the test mode total signal driving circuit, the output end of the third inverter, the first input end of the first nand gate and the first input end of the exclusive-or gate are connected in common, and the second input end of the first nand gate serves as the third input end of the test mode total signal driving circuit;
the output end of the first NAND gate is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the clock end of the D flip-flop, the positive Q end of the D flip-flop is connected with the second input end of the XOR gate and serves as a chip test mode signal end of the test mode total signal driving circuit, and the D end of the D flip-flop is connected to a power supply end;
the output end of the exclusive-or gate is connected to the first input end of the second nand gate, the output end of the nor gate is connected to the second input end of the second nand gate, the output end of the second nand gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the input end of the oscillator, and the output end of the oscillator is used as the timing signal output end of the test mode total signal driving circuit.
5. A test system comprising a test battery and the battery protection chip according to any one of claims 1 to 4.
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| CN202111363721.5A CN114217203A (en) | 2021-11-17 | 2021-11-17 | Battery protection chip and test system |
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| CN202111363721.5A CN114217203A (en) | 2021-11-17 | 2021-11-17 | Battery protection chip and test system |
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