CN213341636U - Test port protection circuit - Google Patents
Test port protection circuit Download PDFInfo
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- CN213341636U CN213341636U CN202021408113.2U CN202021408113U CN213341636U CN 213341636 U CN213341636 U CN 213341636U CN 202021408113 U CN202021408113 U CN 202021408113U CN 213341636 U CN213341636 U CN 213341636U
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Abstract
The utility model provides a test port protection circuit, include: the device comprises a normal output circuit, a first end of the normal output circuit is electrically connected with a TEST end, a second end of the normal output circuit is electrically connected with an output end of a first phase inverter, an input end of the first phase inverter is electrically connected with a DATA end, the normal output circuit comprises a high-level acquisition circuit, a low-level acquisition circuit and a signal output circuit, and the signal output circuit comprises a pull-up protection circuit, a pull-up circuit, a pull-down protection circuit and a pull-down circuit; and a first end of the test output circuit is electrically connected with the TESTDATA end, and a second end of the test output circuit is electrically connected with a third end of the normal output circuit. The utility model provides a test port protection circuit, chip can normally export test signal under test mode, can effectual protection test port circuit and prevent electrostatic interference under normal mode of operation.
Description
Technical Field
The utility model relates to a circuit design field, in particular to test port protection circuit.
Background
With the development of integrated circuit technology, the design of chips is more and more complex, and in order to keep the test cost within a reasonable limit, a testability design technology can be adopted during chip design, and how to quickly and conveniently obtain various test vectors of the chips is one of the problems which need to be solved in the industry.
Many chips can be switched from a normal working mode to a test mode during testing, and certain protective measures are provided for preventing the port state in the test state from influencing the normal mode, but the protective measures do not consider much influence of static electricity introduced from the outside, so that problems are easy to occur in the whole machine static electricity test process.
SUMMERY OF THE UTILITY MODEL
The utility model provides a test port protection circuit, its purpose can not keep apart the chip completely between different modes in order to the traditional port protection circuit of solution, and the chip receives external disturbance's problem easily.
In order to achieve the above object, an embodiment of the present invention provides a test port protection circuit, including:
the device comprises a normal output circuit, a first end of the normal output circuit is electrically connected with a TEST end, a second end of the normal output circuit is electrically connected with an output end of a first phase inverter, an input end of the first phase inverter is electrically connected with a DATA end, the normal output circuit comprises a high-level acquisition circuit, a low-level acquisition circuit and a signal output circuit, and the signal output circuit comprises a pull-up protection circuit, a pull-up circuit, a pull-down protection circuit and a pull-down circuit;
the first end of the test output circuit is electrically connected with the TESTDATA end, and the second end of the test output circuit is electrically connected with the third end of the normal output circuit;
and the first end of the protection circuit is electrically connected with the fourth end of the normal output circuit, and the second end of the protection circuit is electrically connected with the third end of the test output circuit.
Wherein, the high level acquisition circuit includes:
the first input end of the NAND gate is electrically connected with the output end of the first inverter;
the input end of the second inverter is electrically connected with the TEST end, and the output end of the second inverter is electrically connected with the second input end of the NAND gate;
and the input end of the third inverter is electrically connected with the output end of the NOR gate.
Wherein, the low level acquisition circuit includes:
a first input end of the NOR gate is electrically connected with the output end of the first phase inverter, and a second input end of the NOR gate is electrically connected with the TEST end;
the input end of the fourth inverter is electrically connected with the output end of the third inverter;
and the input end of the fifth inverter is electrically connected with the output end of the NAND gate, and the output end of the fifth inverter is electrically connected with the input end of the sixth inverter.
Wherein the pull-up protection circuit comprises:
the source end of the first PMOS tube is respectively and electrically connected with a power supply end and the substrate end of the first PMOS tube, and the gate end of the first PMOS tube is electrically connected with the source end of the first PMOS tube;
a source terminal of the second PMOS tube is electrically connected with a drain terminal of the first PMOS tube, a gate terminal of the second PMOS tube is electrically connected with a gate terminal of the first PMOS tube, and a substrate terminal of the second PMOS tube is electrically connected with a substrate terminal of the first PMOS tube;
the drain end of the first NMOS tube is electrically connected with the drain end of the second PMOS tube, the grid end of the first NMOS tube is respectively and electrically connected with the grid end and the OUT end of the second PMOS tube, and the source end of the first NMOS tube is respectively and electrically connected with the substrate end and the grounding end of the first NMOS tube.
Wherein the pull-up circuit comprises:
a source terminal of the third PMOS tube is electrically connected with a power supply terminal and a substrate terminal of the third PMOS tube respectively, and a gate terminal of the third PMOS tube is electrically connected with an output terminal of the fourth phase inverter;
the source end of the fourth PMOS tube is electrically connected with the drain end of the third PMOS tube, the substrate end of the fourth PMOS tube is electrically connected with the substrate end of the third PMOS tube, the gate end of the fourth PMOS tube is electrically connected with the drain end of the second PMOS tube, and the drain end of the fourth PMOS tube is electrically connected with the gate end of the first NMOS tube.
Wherein the pull-down protection circuit comprises:
a source terminal of the fifth PMOS tube is electrically connected with a power supply terminal and a substrate terminal of the fifth PMOS tube respectively;
the drain end of the second NMOS tube is electrically connected with the drain end of the fifth PMOS tube;
and the drain end of the third NMOS tube is electrically connected with the source end of the second NMOS tube, the substrate end of the third NMOS tube is electrically connected with the substrate end of the second NMOS tube, the gate end of the third NMOS tube is respectively electrically connected with the gate end of the fifth PMOS tube and the source end of the third NMOS tube, and the source end of the third NMOS tube is respectively electrically connected with the substrate end of the third NMOS tube and the grounding end.
Wherein the pull-down circuit comprises:
the drain end of the fourth NMOS tube is electrically connected with the drain end of the fourth PMOS tube, and the gate end of the fourth NMOS tube is electrically connected with the drain end of the fifth PMOS tube;
the drain end of the fifth NMOS tube is electrically connected with the source end of the fourth NMOS tube, the substrate end of the fifth NMOS tube is electrically connected with the substrate end of the fourth NMOS tube, the gate end of the fifth NMOS tube is electrically connected with the output end of the sixth phase inverter, and the source end of the fifth NMOS tube is respectively electrically connected with the substrate end of the fifth NMOS tube and the grounding end.
Wherein the test output circuit comprises:
a first tri-state gate having a first input electrically connected to said TESTDATA terminal and a second input electrically connected to an output of said second inverter;
and the first input end of the second tri-state gate is electrically connected with the output end of the first tri-state gate, and the second input end of the second tri-state gate is electrically connected with the second input end of the first tri-state gate.
Wherein the protection circuit includes:
a source terminal of the sixth PMOS transistor is electrically connected to a power supply terminal and a substrate terminal of the sixth PMOS transistor, respectively, a gate terminal of the sixth PMOS transistor is electrically connected to an input terminal of the second inverter, and a drain terminal of the sixth PMOS transistor is electrically connected to an output terminal of the first tri-state gate;
and the drain end of the sixth NMOS tube is electrically connected with the output end of the second tri-state gate, the gate end of the sixth NMOS tube is electrically connected with the second input end of the second tri-state gate, and the source end of the sixth NMOS tube is respectively electrically connected with the substrate end and the grounding end of the sixth NMOS tube.
Wherein, still include:
a first end of the first resistor is electrically connected with a drain end of the sixth NMOS tube;
a first end of the second resistor is electrically connected with a second end of the first resistor, and a second end of the second resistor is respectively electrically connected with a drain end and an OUT end of the fourth PMOS tube;
a first end of the third resistor is electrically connected with a second end of the second resistor;
a first end of the fourth resistor is electrically connected with a second end of the third resistor, and a second end of the fourth resistor is electrically connected with a gate end of the second NMOS transistor;
and the drain end of the seventh NMOS tube is electrically connected with the second end of the fourth resistor, the gate end of the seventh NMOS tube is electrically connected with the source end of the seventh NMOS tube, and the source end of the seventh NMOS tube is respectively electrically connected with the substrate end and the grounding end of the seventh NMOS tube.
The above technical scheme of the utility model has following beneficial effect:
the above embodiment of the utility model test port protection circuit, the chip can normally output test signal under test mode, can effectual protection test port circuit and prevent electrostatic interference under normal operating mode, realize the protection to test port, guarantee that the chip is kept apart completely at normal mode and test mode two kinds of states, prevent that the chip from getting into test mode or indefinite state mode because of external disturbance under normal mode.
Drawings
Fig. 1 is a specific circuit diagram of the present invention;
fig. 2 is a flow chart of the present invention.
[ description of reference ]
1-a first inverter; a 2-NAND gate; 3-a second inverter; 4-a third inverter; 5-NOR gate; 6-a fourth inverter; 7-a fifth inverter; 8-a sixth inverter; 9-a first PMOS tube; 10-a second PMOS tube; 11-first NMOS transistor; 12-a third PMOS tube; 13-fourth PMOS tube; 14-fifth PMOS tube; 15-second NMOS tube; 16-third NMOS tube; 17-fourth NMOS transistor; 18-fifth NMOS tube; 19-a first tri-state gate; 20-a second tri-state gate; 21-sixth PMOS tube; 22-sixth NMOS tube; 23-a first resistance; 24-a second resistance; 25-a third resistance; 26-a fourth resistance; 27-seventh NMOS transistor.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
The utility model discloses can not keep apart the chip completely between different modes to current port protection circuit, the chip receives external disturbance's problem easily, provides a test port protection circuit.
As shown in fig. 1-2, an embodiment of the present invention provides a test port protection circuit, including: the circuit comprises a normal output circuit, a first end of the normal output circuit is electrically connected with a TEST end, a second end of the normal output circuit is electrically connected with an output end of a first phase inverter 1, an input end of the first phase inverter 1 is electrically connected with a DATA end, the normal output circuit comprises a high-level acquisition circuit, a low-level acquisition circuit and a signal output circuit, and the signal output circuit comprises a pull-up protection circuit, a pull-up circuit, a pull-down protection circuit and a pull-down circuit; the first end of the test output circuit is electrically connected with the TESTDATA end, and the second end of the test output circuit is electrically connected with the third end of the normal output circuit; and the first end of the protection circuit is electrically connected with the fourth end of the normal output circuit, and the second end of the protection circuit is electrically connected with the third end of the test output circuit.
The utility model discloses an above-mentioned embodiment test port protection circuit, for realizing that the chip can both correctly work under test mode and normal mode, and possess corresponding antistatic and external disturbance ability, adopt normal output circuit test output circuit with protection circuit. The sixth PMOS transistor 21 and the sixth NMOS transistor 22 of the protection circuit provide a discharge path to power and ground when the chip is in a normal operating mode and a test mode, so as to prevent current introduced from the port from interfering or damaging the internal structure, and then cooperate with the ESD structure of the output port, thereby achieving the purpose of protecting the output port.
Wherein, the high level acquisition circuit includes: a first input end of the NAND gate 2 is electrically connected with an output end of the first inverter 1; the input end of the second inverter 3 is electrically connected with the TEST end, and the output end of the second inverter 3 is electrically connected with the second input end of the NAND gate 2; and the input end of the third inverter 4 is electrically connected with the output end of the NOR gate 5.
The utility model discloses an above-mentioned embodiment test port protection circuit, high level acquisition circuit include NAND gate 2 the second phase inverter 3 with third phase inverter 4, NAND gate 2's first input is used for receiving the data signal of chip, NAND gate 2's second input is used for receiving test mode control signal.
Wherein, the low level acquisition circuit includes: a first input end of the nor gate 5 is electrically connected with the output end of the first inverter 1, and a second input end of the nor gate 5 is electrically connected with a TEST end; a fourth inverter 6, an input end of the fourth inverter 6 is electrically connected with an output end of the third inverter 4; and an input end of the fifth inverter 7 is electrically connected with an output end of the nand gate 2, and an output end of the fifth inverter 7 is electrically connected with an input end of the sixth inverter 8.
The utility model discloses an above-mentioned embodiment test port protection circuit, low level acquisition circuit include nor gate 5 fourth phase inverter 6 with fifth phase inverter 7, nor gate 5's first input is used for receiving the data signal of chip, nor gate 5's second input is used for receiving test mode control signal.
Wherein the pull-up protection circuit comprises: a first PMOS transistor 9, a source terminal of the first PMOS transistor 9 being electrically connected to a power source terminal and a substrate terminal of the first PMOS transistor 9, respectively, and a gate terminal of the first PMOS transistor 9 being electrically connected to the source terminal of the first PMOS transistor 9; a second PMOS transistor 10, a source terminal of the second PMOS transistor 10 being electrically connected to a drain terminal of the first PMOS transistor 9, a gate terminal of the second PMOS transistor 10 being electrically connected to a gate terminal of the first PMOS transistor 9, a substrate terminal of the second PMOS transistor 10 being electrically connected to a substrate terminal of the first PMOS transistor 9; the drain terminal of the first NMOS tube 11 is electrically connected to the drain terminal of the second PMOS tube 10, the gate terminal of the first NMOS tube 11 is electrically connected to the gate terminal and the OUT terminal of the second PMOS tube 10, respectively, and the source terminal of the first NMOS tube 11 is electrically connected to the substrate terminal and the ground terminal of the first NMOS tube 11, respectively.
Wherein the pull-up circuit comprises: a third PMOS transistor 12, a source terminal of the third PMOS transistor 12 being electrically connected to a power supply terminal and a substrate terminal of the third PMOS transistor 12, respectively, and a gate terminal of the third PMOS transistor 12 being electrically connected to an output terminal of the fourth inverter 6; a fourth PMOS transistor 13, a source terminal of the fourth PMOS transistor 13 is electrically connected to a drain terminal of the third PMOS transistor 12, a substrate terminal of the fourth PMOS transistor 13 is electrically connected to a substrate terminal of the third PMOS transistor 12, a gate terminal of the fourth PMOS transistor 13 is electrically connected to a drain terminal of the second PMOS transistor 10, and a drain terminal of the fourth PMOS transistor 13 is electrically connected to a gate terminal of the first NMOS transistor 11.
Wherein the pull-down protection circuit comprises: a fifth PMOS transistor 14, wherein a source terminal of the fifth PMOS transistor 14 is electrically connected to a power source terminal and a substrate terminal of the fifth PMOS transistor 14, respectively; a second NMOS transistor 15, wherein a drain end of the second NMOS transistor 15 is electrically connected to a drain end of the fifth PMOS transistor 14; a drain terminal of the third NMOS tube 16 is electrically connected to the source terminal of the second NMOS tube 15, a substrate terminal of the third NMOS tube 16 is electrically connected to the substrate terminal of the second NMOS tube 15, a gate terminal of the third NMOS tube 16 is electrically connected to a gate terminal of the fifth PMOS tube 14 and the source terminal of the third NMOS tube 16, respectively, and a source terminal of the third NMOS tube 16 is electrically connected to the substrate terminal of the third NMOS tube 16 and a ground terminal of the third NMOS tube 16, respectively.
Wherein the pull-down circuit comprises: a fourth NMOS transistor 17, a drain terminal of the fourth NMOS transistor 17 being electrically connected to a drain terminal of the fourth PMOS transistor 13, and a gate terminal of the fourth NMOS transistor 17 being electrically connected to a drain terminal of the fifth PMOS transistor 14; a fifth NMOS tube 18, a drain terminal of the fifth NMOS tube 18 is electrically connected to a source terminal of the fourth NMOS tube 17, a substrate terminal of the fifth NMOS tube 18 is electrically connected to a substrate terminal of the fourth NMOS tube 17, a gate terminal of the fifth NMOS tube 18 is electrically connected to an output terminal of the sixth inverter 8, and a source terminal of the fifth NMOS tube 18 is electrically connected to a substrate terminal and a ground terminal of the fifth NMOS tube 18, respectively.
Wherein the test output circuit comprises: a first tri-state gate 19, a first input terminal of said first tri-state gate 19 being electrically connected to said TESTDATA terminal, a second input terminal of said first tri-state gate 19 being electrically connected to an output terminal of said second inverter 3; a second tri-state gate 20, a first input of said second tri-state gate 20 being electrically connected to an output of said first tri-state gate 19, a second input of said second tri-state gate 20 being electrically connected to a second input of said first tri-state gate 19.
Wherein the protection circuit includes: a sixth PMOS transistor 21, a source terminal of the sixth PMOS transistor 21 is electrically connected to a power supply terminal and a substrate terminal of the sixth PMOS transistor 21, a gate terminal of the sixth PMOS transistor 21 is electrically connected to an input terminal of the second inverter 3, and a drain terminal of the sixth PMOS transistor 21 is electrically connected to an output terminal of the first tri-state gate 19; a sixth NMOS tube 22, a drain terminal of the sixth NMOS tube 22 is electrically connected to the output terminal of the second tri-state gate 20, a gate terminal of the sixth NMOS tube 22 is electrically connected to the second input terminal of the second tri-state gate 20, and a source terminal of the sixth NMOS tube 22 is electrically connected to the substrate terminal and the ground terminal of the sixth NMOS tube 22, respectively.
Wherein, still include: a first resistor 23, wherein a first end of the first resistor 23 is electrically connected to a drain end of the sixth NMOS transistor 22; a first end of the second resistor 24 is electrically connected to a second end of the first resistor 23, and second ends of the second resistors 24 are respectively electrically connected to a drain end and an OUT end of the fourth PMOS transistor 13; a third resistor 25, wherein a first end of the third resistor 25 is electrically connected to a second end of the second resistor 24; a fourth resistor 26, a first end of the fourth resistor 26 is electrically connected to a second end of the third resistor 25, and a second end of the fourth resistor 26 is electrically connected to the gate terminal of the second NMOS transistor 15; a seventh NMOS tube 27, a drain terminal of the seventh NMOS tube 27 is electrically connected to the second terminal of the fourth resistor 26, a gate terminal of the seventh NMOS tube 27 is electrically connected to a source terminal of the seventh NMOS tube 27, and the source terminal of the seventh NMOS tube 27 is electrically connected to a substrate terminal and a ground terminal of the seventh NMOS tube 27, respectively.
The utility model discloses an above-mentioned embodiment test port protection circuit, the chip is in two kinds of modes at work: as shown in fig. 2, when the input test signal is invalid, the chip enters a test mode, the GPIO port of the chip outputs a normal working signal and data, and the sixth PMOS transistor 21 and the sixth NMOS transistor 22 of the protection circuit protecting the test output port are turned on to start working, thereby discharging crosstalk current and electrostatic current. When the input test signal is enabled to be effective, the chip enters a test mode, a normal GPIO port is multiplexed to output a test signal, meanwhile, the sixth PMOS tube 21 and the sixth NMOS tube 22 of the protection circuit of the test port are closed, no current is released, a normal output test value is ensured, when the chip is subjected to external static electricity or other crosstalk in a normal working mode, the sixth PMOS tube 21 and the sixth NMOS tube 22 can be pulled down to release interference current to the ground, and when the first tri-state gate 19 and the second tri-state gate 20 are broken down by excessive external current, the sixth PMOS tube 21 and the sixth NMOS tube 22 are pulled up to release the current to a power supply, so that the reliability and the capacity of the chip are improved.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (1)
1. A test port protection circuit, comprising:
the device comprises a normal output circuit, a first end of the normal output circuit is electrically connected with a TEST end, a second end of the normal output circuit is electrically connected with an output end of a first phase inverter, an input end of the first phase inverter is electrically connected with a DATA end, the normal output circuit comprises a high-level acquisition circuit, a low-level acquisition circuit and a signal output circuit, and the signal output circuit comprises a pull-up protection circuit, a pull-up circuit, a pull-down protection circuit and a pull-down circuit;
the first end of the test output circuit is electrically connected with the TESTDATA end, and the second end of the test output circuit is electrically connected with the third end of the normal output circuit;
a first end of the protection circuit is electrically connected with a fourth end of the normal output circuit, and a second end of the protection circuit is electrically connected with a third end of the test output circuit;
the high level acquisition circuit includes:
the first input end of the NAND gate is electrically connected with the output end of the first inverter;
the input end of the second inverter is electrically connected with the TEST end, and the output end of the second inverter is electrically connected with the second input end of the NAND gate;
the input end of the third inverter is electrically connected with the output end of the NOR gate;
the low level acquisition circuit includes:
a first input end of the NOR gate is electrically connected with the output end of the first phase inverter, and a second input end of the NOR gate is electrically connected with the TEST end;
the input end of the fourth inverter is electrically connected with the output end of the third inverter;
the input end of the fifth inverter is electrically connected with the output end of the NAND gate, and the output end of the fifth inverter is electrically connected with the input end of the sixth inverter;
the pull-up protection circuit includes:
the source end of the first PMOS tube is respectively and electrically connected with a power supply end and the substrate end of the first PMOS tube, and the gate end of the first PMOS tube is electrically connected with the source end of the first PMOS tube;
a source terminal of the second PMOS tube is electrically connected with a drain terminal of the first PMOS tube, a gate terminal of the second PMOS tube is electrically connected with a gate terminal of the first PMOS tube, and a substrate terminal of the second PMOS tube is electrically connected with a substrate terminal of the first PMOS tube;
the drain end of the first NMOS tube is electrically connected with the drain end of the second PMOS tube, the gate end of the first NMOS tube is respectively and electrically connected with the gate end and the OUT end of the second PMOS tube, and the source end of the first NMOS tube is respectively and electrically connected with the substrate end and the grounding end of the first NMOS tube;
the pull-up circuit includes:
a source terminal of the third PMOS tube is electrically connected with a power supply terminal and a substrate terminal of the third PMOS tube respectively, and a gate terminal of the third PMOS tube is electrically connected with an output terminal of the fourth phase inverter;
a source terminal of the fourth PMOS tube is electrically connected with a drain terminal of the third PMOS tube, a substrate terminal of the fourth PMOS tube is electrically connected with a substrate terminal of the third PMOS tube, a gate terminal of the fourth PMOS tube is electrically connected with a drain terminal of the second PMOS tube, and a drain terminal of the fourth PMOS tube is electrically connected with a gate terminal of the first NMOS tube;
the pull-down protection circuit includes:
a source terminal of the fifth PMOS tube is electrically connected with a power supply terminal and a substrate terminal of the fifth PMOS tube respectively;
the drain end of the second NMOS tube is electrically connected with the drain end of the fifth PMOS tube;
the drain end of the third NMOS tube is electrically connected with the source end of the second NMOS tube, the substrate end of the third NMOS tube is electrically connected with the substrate end of the second NMOS tube, the gate end of the third NMOS tube is respectively electrically connected with the gate end of the fifth PMOS tube and the source end of the third NMOS tube, and the source end of the third NMOS tube is respectively electrically connected with the substrate end of the third NMOS tube and the grounding end;
the pull-down circuit includes:
the drain end of the fourth NMOS tube is electrically connected with the drain end of the fourth PMOS tube, and the gate end of the fourth NMOS tube is electrically connected with the drain end of the fifth PMOS tube;
a drain terminal of the fifth NMOS transistor is electrically connected to a source terminal of the fourth NMOS transistor, a substrate terminal of the fifth NMOS transistor is electrically connected to a substrate terminal of the fourth NMOS transistor, a gate terminal of the fifth NMOS transistor is electrically connected to an output terminal of the sixth inverter, and source terminals of the fifth NMOS transistor are electrically connected to a substrate terminal and a ground terminal of the fifth NMOS transistor, respectively;
the test output circuit includes:
a first tri-state gate having a first input electrically connected to said TESTDATA terminal and a second input electrically connected to an output of said second inverter;
a second tri-state gate having a first input electrically connected to the output of the first tri-state gate and a second input electrically connected to the second input of the first tri-state gate;
the protection circuit includes:
a source terminal of the sixth PMOS transistor is electrically connected to a power supply terminal and a substrate terminal of the sixth PMOS transistor, respectively, a gate terminal of the sixth PMOS transistor is electrically connected to an input terminal of the second inverter, and a drain terminal of the sixth PMOS transistor is electrically connected to an output terminal of the first tri-state gate;
a drain terminal of the sixth NMOS transistor is electrically connected to an output terminal of the second tri-state gate, a gate terminal of the sixth NMOS transistor is electrically connected to a second input terminal of the second tri-state gate, and a source terminal of the sixth NMOS transistor is electrically connected to a substrate terminal and a ground terminal of the sixth NMOS transistor, respectively;
further comprising:
a first end of the first resistor is electrically connected with a drain end of the sixth NMOS tube;
a first end of the second resistor is electrically connected with a second end of the first resistor, and a second end of the second resistor is respectively electrically connected with a drain end and an OUT end of the fourth PMOS tube;
a first end of the third resistor is electrically connected with a second end of the second resistor;
a first end of the fourth resistor is electrically connected with a second end of the third resistor, and a second end of the fourth resistor is electrically connected with a gate end of the second NMOS transistor;
and the drain end of the seventh NMOS tube is electrically connected with the second end of the fourth resistor, the gate end of the seventh NMOS tube is electrically connected with the source end of the seventh NMOS tube, and the source end of the seventh NMOS tube is respectively electrically connected with the substrate end and the grounding end of the seventh NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021408113.2U CN213341636U (en) | 2020-07-16 | 2020-07-16 | Test port protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021408113.2U CN213341636U (en) | 2020-07-16 | 2020-07-16 | Test port protection circuit |
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| CN213341636U true CN213341636U (en) | 2021-06-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114217203A (en) * | 2021-11-17 | 2022-03-22 | 深圳市创芯微微电子有限公司 | Battery protection chip and test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114217203A (en) * | 2021-11-17 | 2022-03-22 | 深圳市创芯微微电子有限公司 | Battery protection chip and test system |
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