CN212542446U

CN212542446U - Novel schottky diode of double-groove

Info

Publication number: CN212542446U
Application number: CN202021477848.0U
Authority: CN
Inventors: 薛涛; 关仕汉; 迟晓丽
Original assignee: Zibo Hanlin Semiconductor Co ltd
Current assignee: Zibo Hanlin Semiconductor Co ltd
Priority date: 2020-07-24
Filing date: 2020-07-24
Publication date: 2021-02-12
Anticipated expiration: 2030-07-24

Abstract

The utility model discloses a novel double-groove Schottky diode, which comprises an N + type substrate and an N-type epitaxial layer, wherein the upper surface of the N + type substrate is provided with the N-type epitaxial layer, 1 or more voltage reduction rings are symmetrically arranged on the outer circle of a chip on the upper surface of the N-type epitaxial layer, a first groove is uniformly arranged at the center of the upper surface of the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is positioned between the two first grooves and is provided with a second groove, the voltage reduction rings and the inner wall of the first groove are provided with a silicon oxide insulating layer, and polycrystalline silicon is filled in the voltage reduction rings and the first grooves; the utility model discloses a set up first slot and second slot on N-type epitaxial layer surface, adopt the design of double flute, can effectively block the electric current when the reverse circular current of chip through first slot, can effectively increase the area at schottky interface through the second slot, great increase the electrically conductive area reduce the forward pressure drop, efficiency when improving the product and switching on.

Description

Novel schottky diode of double-groove

Technical Field

The utility model relates to a semiconductor device makes technical field, specifically is a novel schottky diode of double flute.

Background

The traditional groove type Schottky needs to make an insulating layer (silicon oxide) in a groove thick for achieving high voltage resistance, so that the effective conductive area is sacrificed, the forward voltage drop is increased, the conduction efficiency is lowered, or the area of a chip is enlarged for ensuring proper forward voltage drop, and the manufacturing cost is increased.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a novel schottky diode of double flute to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: a novel double-groove Schottky diode comprises an N + type substrate and an N-type epitaxial layer, the upper surface of the N + type substrate is provided with an N-type epitaxial layer, the outer ring of the chip on the upper surface of the N-type epitaxial layer is symmetrically provided with 1 or more voltage reduction rings, first grooves are uniformly arranged at the center of the upper surface of the N-type epitaxial layer, a second groove is arranged between the two first grooves on the upper surface of the N-type epitaxial layer, the inner walls of the voltage reducing ring and the first groove are both provided with silicon oxide insulating layers, the insides of the voltage reducing ring and the first groove are both filled with polysilicon, silicon oxide protective layers are deposited on outer rings of the chips on the upper surface of the N-type epitaxial layer, Schottky interfaces are arranged on the upper surface of the N-type epitaxial layer between the silicon oxide protective layers and on the inner wall of the second groove.

Wherein the Schottky interface is located on the inner wall of the second trench.

Wherein a depth dimension of the first trench is greater than a depth dimension of the second trench.

And the width dimension of the voltage reducing ring is greater than that of the first groove.

And the silicon oxide protective layer and the Schottky interface cover the upper surface of the N-type epitaxial layer.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses a set up first slot and second slot on N type epitaxial layer surface, adopt the design of double flute, can effectively block the electric current when the reverse circular current of chip through first slot, can effectively increase the area at schottky interface through the second slot, great increase conductive area reduces the forward pressure drop, efficiency when improving the product forward and switching on.

Drawings

Fig. 1 is a schematic view of the main sectional structure of the present invention.

In the figure: a 1-N + type substrate; a 2-N-type epitaxial layer; 3-a silicon oxide protective layer; 4-reducing the pressure ring; 5-a first trench; 6-a second trench; 7-a silicon oxide insulating layer; 8-polycrystalline silicon; 9-schottky interface.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a novel double-groove Schottky diode comprises an N + type substrate 1 and an N-type epitaxial layer 2.

The upper surface of the N + type substrate 1 is provided with an N-type

epitaxial layer

2, 1 or more voltage reduction rings 4 are symmetrically arranged on the outer ring of a chip on the upper surface of the N-type epitaxial layer 2, first grooves 5 are uniformly arranged at the center of the upper surface of the N-type epitaxial layer 2, a second groove 6 is arranged between the two first grooves 5 on the upper surface of the N-type epitaxial layer 2, silicon oxide insulating layers 7 are arranged on the inner walls of the voltage reduction rings 4 and the first grooves 5, polycrystalline silicon 8 is filled in the voltage reduction rings 4 and the first grooves 5, silicon oxide protective layers 3 are deposited on the outer ring of the chip on the upper surface of the N-type epitaxial layer 2, the upper surface of the N-type epitaxial layer 2 is arranged between the silicon oxide protective layers 3, and Schottky interfaces 9 are arranged on the inner walls of the second grooves.

The schottky interface 9 is located between the inner wall of the second trench 6 and the upper surface of the N-type epitaxial layer 2 and the silicon oxide protection layer 3.

Wherein the depth dimension of the first trench 5 is larger than the depth dimension of the second trench 6.

Wherein, the width dimension of the voltage-reducing ring 4 is larger than the width dimension of the first trench 5.

Wherein, the silicon oxide protective layer 3 and the Schottky interface 9 cover the upper surface of the N-type epitaxial layer 2.

Wherein, the first trench 5 can effectively block current when the chip is reversely electrified.

Wherein, can effectively increase the area at schottky interface through second slot 6, great increase conducting area reduces the forward voltage drop, efficiency when improving the product and switching on.

The working principle is as follows: during manufacturing, a layer of silicon oxide for forming a groove is arranged on the surface of the N-type epitaxial layer 2, then photoresist is coated, the position of the groove of the silicon oxide is etched by using a photomask to form a silicon oxide template, a first groove 5 and a voltage reduction ring 4 are formed on the surface of the N-type epitaxial layer 2 through the template, then a layer of silicon oxide insulating layer 7 is arranged on the inner walls of the first groove 5 and the voltage reduction ring 4, polysilicon 8 is filled in the first groove 5 and the voltage reduction ring 4, meanwhile, the polysilicon 8 on the surface of a chip is ground or etched, so that the upper surface of the polysilicon 8 and the upper surface of the N-type epitaxial layer 2 are positioned on the same horizontal plane, silicon oxide deposition is carried out on the surface of the chip, then a second groove 6 is formed between the first grooves 5 on the surface of the N-type epitaxial layer 2, the depth of the second groove 6 is smaller than that of the first grooves 5, and, stay in chip outer lane oxide layer and form chip silicon oxide protective layer 3, then make schottky interface 9 cover the upper surface that 2 naked leaks of N-type epitaxial layer, and second slot 6 inner wall, make positive metal, the chip back attenuate, the chip preparation is accomplished to preparation back metal level, this diode is through setting up first slot 5 and second slot 6 on 2 surfaces of N-type epitaxial layer, adopt the design of two slots, can effectively block the electric current when the reverse circular telegram of chip flows through first slot 5, can effectively increase the area at schottky interface through second slot 6, great increase the conducting area and reduced forward voltage drop, efficiency when improving the product and switching on.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A novel double-groove Schottky diode comprises an N + type substrate (1) and an N-type epitaxial layer (2), and is characterized in that: an N-type epitaxial layer (2) is arranged on the upper surface of the N + type substrate (1), the outer ring of the chip on the upper surface of the N-type epitaxial layer (2) is symmetrically provided with 1 or more voltage reduction rings (4), the center of the upper surface of the N-type epitaxial layer (2) is uniformly provided with first grooves (5), a second groove (6) is arranged on the upper surface of the N-type epitaxial layer (2) between the two first grooves (5), the inner walls of the voltage reducing ring (4) and the first groove (5) are both provided with a silicon oxide insulating layer (7), the interior of the voltage reducing ring (4) and the interior of the first groove (5) are both filled with polysilicon (8), a silicon oxide protective layer (3) is deposited on the outer ring of the chip on the upper surface of the N-type epitaxial layer (2), schottky interfaces (9) are arranged on the upper surface of the N-type epitaxial layer (2), between the silicon oxide protective layers (3) and on the inner wall of the second groove.

2. A novel double trench schottky diode as in claim 1 wherein: the Schottky interface (9) is positioned on the inner wall of the second groove (6).

3. A novel double trench schottky diode as in claim 1 wherein: the depth dimension of the first trench (5) is greater than the depth dimension of the second trench (6).

4. A novel double trench schottky diode as in claim 1 wherein: the width dimension of the voltage reducing ring (4) is larger than that of the first groove (5).

5. A novel double trench schottky diode as in claim 1 wherein: the silicon oxide protective layer (3) and the Schottky interface (9) cover the upper surface of the N-type epitaxial layer (2).