CN208352298U - A kind of groove MOS barrier Schottky diode - Google Patents
A kind of groove MOS barrier Schottky diode Download PDFInfo
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- CN208352298U CN208352298U CN201820842476.3U CN201820842476U CN208352298U CN 208352298 U CN208352298 U CN 208352298U CN 201820842476 U CN201820842476 U CN 201820842476U CN 208352298 U CN208352298 U CN 208352298U
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- 230000004888 barrier function Effects 0.000 title claims abstract description 56
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 22
- 238000001259 photo etching Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000002253 acid Substances 0.000 description 3
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
A kind of groove MOS barrier Schottky diode, belongs to technical field of semiconductors.The cathode and anode drawn including groove MOS barrier schottky chip and respectively, including substrate (6) and epitaxial layer (4), the surface of epitaxial layer (4) is provided with active area groove (5) and pressure ring groove (3), it is characterized by: chip cutting position (12) are at the middle part of the pressure ring groove (3), from chip cutting position (12), cutting forms cut surface (10), has passivation layer (16) covering in cut surface (10) and lower edges area.In this groove MOS barrier Schottky diode, it is cut in the middle part of pressure ring groove, eliminate pressure ring crooked radian position in the prior art, improve the pressure-resistant performance of chip, the manufacture for realizing chip only with one of photoetching simultaneously, substantially reduces complex process degree and production cost.
Description
Technical field
A kind of groove MOS barrier Schottky diode, belongs to technical field of semiconductors.
Background technique
In recent years due to the low conducting pressure of Schottky barrier diode (Schottky Barrier Diode, abbreviation SBD)
Drop and extremely short reverse recovery time cause people to the raising of circuit system efficiency and pay much attention to and be widely used.SBD has three
A feature is more prominent: (1) because schottky barrier height is less than PN junction barrier height, the cut-in voltage and conduction voltage drop of SBD
It is smaller than PIN diode, power loss in circuit can be reduced to reduced levels；(2) junction capacity of SBD is lower, its work
Working frequency is up to 100GHz；(3) SBD is the injection there is no minority carrier, therefore switching speed is faster, itself Reverse recovery
Time is the charge and discharge time of Schottky barrier capacitor.
Traditional Schottky diode due to reverse blocking capability close to 200V when, the forward voltage drop VF of Schottky rectifier
By close to the forward voltage drop of PIN rectifier, therefore the reverse BV of traditional Schottky barrier diode is generally below
200V, the efficiency being allowed in the application are lower.
In order to reduce conduction voltage drop to reduce own loss, groove MOS barrier Schottky diode is proposed
(Trench MOS-Barrier SBD, abbreviation TMBS).The main advantage of TMBS product design is it by planar Schottky device
The maximum field on surface is transferred to the ability inside the extension of trench bottom.It can thus inhibit potential barrier to decline effect, reduce
The reverse leakage of given Schottky barrier, it means that TMBS product can use resistance more lower than planar Schottky rectifier
Rate and lower potential barrier extension realize forward voltage and turn off gain.
Existing groove MOS barrier Schottky diode structure is as shown in figure 11, including substrate 6, is in the top of substrate 6
Epitaxial layer 4 is arranged at intervals with several active area grooves 5 on the surface of epitaxial layer 4, is pressure ring in the outside of active area groove 5
Groove 3, the inner sidewall of active area groove 5 and pressure ring groove 3 formed groove internal oxidation layer 2, inside by polysilicon 9 into
Row filling.It is additionally provided with insulating layer 17 in 4 top surface edge of epitaxial layer, anode metal layer 1 is covered on 4 surface of epitaxial layer and is located at
The inside of insulating layer 17.There are as follows on product and technique for the groove MOS barrier Schottky diode of the prior art
Defect: (1) being formed with arcwall face in the bottom of pressure ring groove 3, and the bigger potential lines of crooked radian are closeer, and electric field strength is got over
Greatly, this pressure-resistant performance for affecting chip.(2) third photo etching technique is at least needed in prior art: being in epitaxial layer 4 for the first time
Surface active area groove 5 and pressure ring groove 3 are opened up by photoetching process；Second of photoetching process is to 17 light of insulating layer
Quarter is allowed to form contact hole, to be further formed schottky interface 7；Third time photoetching is to carry out photoetching to anode metal layer 1,
It is allowed to positioned at the inside of insulating layer 17, therefore production technology is complex in the prior art, and needs wider one or more
Pressure ring improves chip pressure resistance performance.
Summary of the invention
Technical problem to be solved by the utility model is: overcoming the deficiencies of the prior art and provide one kind in the middle part of pressure ring
It is cut, eliminates pressure ring crooked radian position in the prior art, improved the pressure-resistant performance of chip, make complex process journey
The groove MOS barrier Schottky diode that degree and production cost substantially reduce.
The technical scheme adopted by the utility model to solve the technical problem is as follows: two pole of groove MOS barrier schottky
Pipe, the cathode and anode drawn respectively including groove MOS barrier schottky chip and from chip by lead, plough groove type
MOS barrier schottky chip includes the epitaxial layer above substrate and substrate, and the surface of epitaxial layer is provided with active area groove
Pressure ring groove with active area outer ring is located at, the anode metal layer connecting with lead is formed on the surface of epitaxial layer, is being served as a contrast
The bottom surface at bottom forms the cathode metal layer connecting with lead, it is characterised in that: chip cutting position is in the pressure ring groove
Middle part cuts to form cut surface from chip cutting position, is covered with passivation layer at the lower edges of cut surface and cut surface.
Preferably, it is provided with groove internal oxidation layer on the inner wall of the pressure ring groove and fills polysilicon.
Preferably, groove internal oxidation layer is provided on the inner wall of the active area groove and filled with polysilicon.
Preferably, draw respectively by the way that soldering-tin layer welding is described on the surface of the anode metal layer and cathode metal layer
Line.
Preferably, passivation layer is equally covered in the outer side surface of the anode metal layer and cathode metal layer.
Preferably, the soldering-tin layer is located at the inside of passivation layer.
Compared with prior art, beneficial effect possessed by the utility model is:
It in this groove MOS barrier Schottky diode, is cut, is eliminated in the prior art in the middle part of pressure ring
Pressure ring crooked radian position improves the pressure-resistant performance of chip, substantially reduces complex process degree and production cost.
In this groove MOS barrier schottky wafer, chip cutting position at the middle part of the pressure ring groove,
Cut surface is cut longitudinally to form in the middle part of each pressure ring groove, cutting forms several isolated groove MOSs after completing
Barrier schottky chip, in each groove MOS barrier schottky chip, several active area grooves including middle part and
Positioned at the half of outside pressure ring groove, i.e., the same pressure ring is located at two adjacent groove MOSs after dicing
In barrier schottky chip.
Since cutting position is located at the middle part of pressure ring groove, pressure ring channel bottom Curved in the prior art is eliminated
At arcwall face, reduce its electric field strength, improve the pressure-resistant performance of chip.The spacing of the active area groove of chip is according to resistance to
Pressure is adjusted, and the pinch off of current channel is realized in the broadening of PN junction depletion region when reverse-biased, effectively Schottky barrier is inhibited to reduce
Effect.
The processes such as the welded, acid wash passivation of groove MOS barrier schottky chip after cutting separation, in cut surface and
Lower edges area forms a floor passivation layer, and soldering-tin layer is located at the inside of passivation layer, forms passivation layer by the outlet in chip,
So that electric current can not circulate from the side of chip, instead of the effect of insulating layer in the prior art, therefore it is existing to eliminate progress
Second and third road lithography step in technology, due in the production technology of this groove MOS barrier schottky chip, only
Using one of photoetching process, compared at least needing three photoetching processes in the prior art, complex process degree and it is produced into
It is substantially reduced on this.
Detailed description of the invention
Fig. 1 is groove MOS barrier schottky chip structure schematic diagram.
Fig. 2 ~ Fig. 8 is groove MOS barrier schottky chip manufacturing flow chart.
Fig. 9 is groove MOS barrier Schottky diode structural schematic diagram.
Figure 10 is enlarged drawing at A in Fig. 9.
Figure 11 is prior art groove MOS barrier schottky chip structure schematic diagram.
Wherein: 1, anode metal layer 2, groove internal oxidation layer 3, pressure ring groove 4, epitaxial layer 5, active area groove
6, substrate 7, schottky interface 8, cathode metal layer 9, polysilicon 10, cut surface 11, the first oxide layer 12, chip cutting
Position 13, soldering-tin layer 14, chip 15, lead 16, passivation layer 17, insulating layer.
Specific embodiment
Fig. 1 ~ 10 are the most preferred embodiments of the utility model, and 1 ~ 10 pair of the utility model is done furtherly with reference to the accompanying drawing
It is bright.
As shown in Figure 1, a kind of groove MOS barrier schottky chip, including substrate 6, it is epitaxial layer in the top of substrate 6
4, several pressure ring grooves 3 are arranged at intervals on the surface of epitaxial layer 4, are additionally provided between two neighboring pressure ring groove 3
Several active area grooves 5 are provided with groove internal oxidation layer 2 on the inner wall of active area groove 5 and pressure ring groove 3,
The inside of active area groove 5 and pressure ring groove 3 is filled by polysilicon 9.It is not opened up on the surface of epitaxial layer 4 active
The position of area's groove 5 and pressure ring groove 3 forms schottky interface 7.It is additionally provided with anode metal layer 1 and cathode metal layer 8,
Wherein anode metal layer 1 is covered on the surface of polysilicon 9 and schottky interface 7, for drawing this groove MOS potential barrier Xiao Te
The anode of base chip, cathode metal layer 8 are covered on the bottom surface of substrate 6, for drawing this groove MOS barrier schottky chip
Cathode.
In this groove MOS barrier schottky wafer, chip cutting position 12 is in the pressure ring groove 3
Portion is cut longitudinally to form cut surface 10 at the middle part of each pressure ring groove 3, and cutting forms several isolated ditches after completing
Slot type MOS barrier schottky chip, in each groove MOS barrier schottky chip, several active areas including middle part
Groove 5 and half positioned at outside pressure ring groove 3, i.e., the same pressure ring groove 3 is located at adjacent after dicing
Two groove MOS barrier schottky chips in.
Since chip cutting position 12 is located at the middle part of pressure ring groove 3,3 bottom of pressure ring groove in the prior art is eliminated
The arcwall face that portion is formed by bending reduces its electric field strength, improves the pressure-resistant performance of groove MOS barrier schottky chip.
The spacing of the active area groove 5 of groove MOS barrier schottky chip is adjusted according to pressure resistance, PN junction depletion region when reverse-biased
The pinch off of current channel is realized in broadening, and Schottky barrier is effectively inhibited to reduce effect.
As shown in Fig. 2 ~ 8, groove MOS barrier schottky chip as shown in Figure 1 is made, includes the following steps:
Step 1, epitaxial layer 4 is formed in the top of substrate 6, then carries out first time oxidation processes on the surface of epitaxial layer 4,
The first oxide layer 11 is formed on the surface of epitaxial layer 4, then one of lithographic process is carried out on the surface of epitaxial layer 4, etches resistance to
Pressure ring groove 3 and active area groove 5, as shown in Figure 2.
Step 2, second of oxidation processes is carried out in the upper surface of epitaxial layer 4, forms second layer oxide layer, the second oxide layer
As groove internal oxidation layer 2, as shown in Figure 3.
Step 3, the depositing operation that polysilicon 9 is carried out in 4 upper surface of epitaxial layer, in pressure ring groove 3 and active area groove 5
Deposit polycrystalline silicon 9 simultaneously, as shown in Figure 4.
Step 4, it carries out the technique such as chemically-mechanicapolish polishing on surface, the polysilicon 9 of 4 upper surface of epitaxial layer and oxide layer is gone
It removes, as shown in Figure 5.
Step 5, schottky interface metal (such as titanium, platinum, molybdenum, vanadium, tungsten, aluminium etc.), annealing are sputtered in 4 upper surface of epitaxial layer
Etc. techniques formed schottky interface 7, as shown in Figure 6.
Step 6, the underrun prior art on the surface of epitaxial layer 4 and substrate 6 is respectively formed 1 He of anode metal layer
Cathode metal layer 8 obtains groove MOS barrier schottky wafer as shown in Figure 7.
Step 7, groove MOS barrier schottky wafer is cut by chip cutting position 12 shown in fig. 8, it will
Whole wafer is divided into crystal grain, obtains groove MOS barrier schottky chip as shown in Figure 1.
As shown in Fig. 9 ~ 10, groove MOS barrier schottky chip (hereinafter referred to as chip 14) as shown in Figure 1 is being obtained
Afterwards, pass through 13 welding lead 15 of soldering-tin layer respectively in the anode metal layer 1 of chip 14 and 8 surface of cathode metal layer, by welding
Technique dresses up axial diode, is destroyed since chip 14 cuts trailing flank Schottky junction structure, and electric current circulates from 14 side of chip,
The function of losing Schottky diode needs to carry out acid wash passivation process (mixed acid) to the border of chip 14 to wash off edge,
A floor passivation layer 16 is formed in 14 side of chip and lower edges area, ultimately forms groove MOS barrier Schottky diode
Finished product.
Wherein soldering-tin layer 13 is located at the inside of passivation layer 16, forms passivation layer 16 by the outlet in chip 14, so that
Electric current can not circulate from the side of chip 14, and instead of the effect of insulating layer 17 in the prior art, therefore it is existing to eliminate progress
Second and third road lithography step in technology, due in the production technology of this groove MOS barrier schottky chip, only
Using one of photoetching process, compared at least needing three photoetching processes in the prior art, complex process degree and it is produced into
It is substantially reduced on this.
The above descriptions are merely preferred embodiments of the present invention, is not to make other forms to the utility model
Limitation, any person skilled in the art is changed or is modified as possibly also with the technology contents of the disclosure above equivalent
The equivalent embodiment of variation.But it is all without departing from the content of the technical scheme of the utility model, the technology according to the utility model is real
Matter any simple modification, equivalent variations and remodeling to the above embodiments, still fall within the guarantor of technical solutions of the utility model
Protect range.
Claims (6)
1. a kind of groove MOS barrier Schottky diode, including groove MOS barrier schottky chip and lead to from chip
Cathode and anode that lead (15) is drawn respectively are crossed, groove MOS barrier schottky chip includes substrate (6) and substrate (6)
The epitaxial layer (4) of top is provided with active area groove (5) and pressure ring positioned at active area outer ring on the surface of epitaxial layer (4)
Groove (3) is formed with the anode metal layer (1) connecting with lead (15) on the surface of epitaxial layer (4), in the bottom surface of substrate (6)
Form the cathode metal layer (8) connecting with lead (15), it is characterised in that: chip cutting position (12) are in the pressure ring groove
(3) middle part, from chip cutting position (12), cutting forms cut surface (10), cut surface (10) and cut surface (10) up and down
Edge is covered with passivation layer (16).
2. groove MOS barrier Schottky diode according to claim 1, it is characterised in that: in the pressure ring
It is provided with groove internal oxidation layer (2) on the inner wall of groove (3) and fills polysilicon (9).
3. groove MOS barrier Schottky diode according to claim 1, it is characterised in that: in the active area
Groove internal oxidation layer (2) is provided on the inner wall of groove (5) and filled with polysilicon (9).
4. groove MOS barrier Schottky diode according to claim 1, it is characterised in that: in the anode metal
The surface of layer (1) and cathode metal layer (8) passes through soldering-tin layer (13) welding lead (15) respectively.
5. groove MOS barrier Schottky diode according to claim 1, it is characterised in that: in the anode metal
The outer side surface of layer (1) and cathode metal layer (8) is equally covered with passivation layer (16).
6. groove MOS barrier Schottky diode according to claim 4, it is characterised in that: the soldering-tin layer
(13) it is located at the inside of passivation layer (16).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820842476.3U CN208352298U (en) | 2018-06-01 | 2018-06-01 | A kind of groove MOS barrier Schottky diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820842476.3U CN208352298U (en) | 2018-06-01 | 2018-06-01 | A kind of groove MOS barrier Schottky diode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550631A (en) * | 2018-06-01 | 2018-09-18 | 淄博汉林半导体有限公司 | A kind of groove MOS barrier Schottky diode and manufacturing method |
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2018
- 2018-06-01 CN CN201820842476.3U patent/CN208352298U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550631A (en) * | 2018-06-01 | 2018-09-18 | 淄博汉林半导体有限公司 | A kind of groove MOS barrier Schottky diode and manufacturing method |
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