CN212111533U - Probe card with new structure for testing DFN packaged IC - Google Patents

Probe card with new structure for testing DFN packaged IC Download PDF

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Publication number
CN212111533U
CN212111533U CN202020219296.7U CN202020219296U CN212111533U CN 212111533 U CN212111533 U CN 212111533U CN 202020219296 U CN202020219296 U CN 202020219296U CN 212111533 U CN212111533 U CN 212111533U
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CN
China
Prior art keywords
probe card
epoxy
printed circuit
circuit board
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN202020219296.7U
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Chinese (zh)
Inventor
安奎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Yiran Semiconductor Test Co ltd
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Shanghai Yiran Semiconductor Test Co ltd
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Priority to CN202020219296.7U priority Critical patent/CN212111533U/en
Application granted granted Critical
Publication of CN212111533U publication Critical patent/CN212111533U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

The utility model discloses a belong to probe card and make technical field, specifically be a new construction probe card for testing DFN encapsulation IC, it includes: the IC pin packaged by the QFN package is placed in a groove at the top of the machining part, so that the IC pin is contacted with the inner needle of the epoxy probe card in the epoxy probe card, and a signal is led out from the socket of the printed circuit board, thereby reducing the number of the machining parts, not depending on a special printed circuit board, shortening the machining time, reducing the manufacturing cost and reducing the cost for testing.

Description

Probe card with new structure for testing DFN packaged IC
Technical Field
The utility model relates to a probe card makes technical field, specifically is a new construction probe card for testing DFN encapsulation IC.
Background
The QFN packaged IC is granular and is a cuboid, pins to be tested are arranged on the QFN packaged IC, final detection is needed to be carried out again at the end of manufacturing, and whether the QFN packaged IC is good or bad is discriminated. Firstly, combining the socket and the special printed circuit board, placing the QFN packaged IC in the groove, pressing down to enable the pins of the IC to be in contact with the spring pins in the socket, and leading out signals from the socket of the printed circuit board.
SOCKET is used for testing QFN packaged IC, because the number and the positions of pins of the IC are different, a corresponding special printed circuit board needs to be manufactured for each variety, and SOCKET mechanical processing parts are more, so that in the test of a plurality of varieties and small-batch products, the variety of the printed circuit boards is more, the SOCKET manufacturing period is longer, and the cost is higher.
SUMMERY OF THE UTILITY MODEL
This section is for the purpose of summarizing some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and in the abstract of the specification and the title of the application to avoid obscuring the purpose of this section, the abstract of the specification and the title of the application, and such simplifications or omissions are not intended to limit the scope of the invention.
The present invention has been made in view of the above and/or other problems with the prior art probe cards for testing DFN packaged ICs.
Therefore, the present invention is directed to a probe card with a new structure for testing DFN packaged ICs, which can reduce the number of machined parts, does not depend on a dedicated printed circuit board, shortens the machining time, reduces the manufacturing cost, and reduces the cost for testing.
For solving the technical problem, according to the utility model discloses an aspect, the utility model provides a following technical scheme:
a new structure probe card for testing DFN packaged ICs, comprising: the PCB comprises a universal printed circuit board, an epoxy probe card, a machining part and a QFN package, wherein a printed circuit board socket is arranged on the right side of the top of the universal printed circuit board, the epoxy probe card is arranged on the left side of the top of the universal printed circuit board, a plurality of epoxy probe card inner needles are arranged on the top of the epoxy probe card, the machining part is arranged on the top of the epoxy probe card, the plurality of epoxy probe card inner needles are inserted into the machining part, the QFN package is arranged on the top of the machining part, and a plurality of IC pins are arranged at the bottom of the Q.
As a preferred embodiment of the present invention, a probe card with a new structure for testing DFN packaged ICs, wherein: the inner needles of the epoxy probe card are uniformly distributed on the top of the epoxy probe card.
As a preferred embodiment of the present invention, a probe card with a new structure for testing DFN packaged ICs, wherein: a plurality of IC pins are uniformly distributed at the bottom of the QFN package.
As a preferred embodiment of the present invention, a probe card with a new structure for testing DFN packaged ICs, wherein: and a plurality of inner needles of the epoxy probe card are exposed at the top of the machining part.
As a preferred embodiment of the present invention, a probe card with a new structure for testing DFN packaged ICs, wherein: and a clamping groove is formed in the top of the machining part and matched with the QFN package.
Compared with the prior art: the method comprises the steps of manufacturing an epoxy probe card according to an IC pin test position, manufacturing the epoxy probe card by using a universal printed circuit board, leading out a signal through the universal printed circuit board, installing a mechanical processing part manufactured according to a test part and peripheral dimensions of a packaged IC, exposing an inner needle of the epoxy probe card for a certain length, placing the QFN packaged IC pin in a groove at the top of the mechanical processing part, pressing down the QFN package, enabling the IC pin to be in contact with the inner needle of the epoxy probe card in the epoxy probe card, leading out the signal from a socket of the printed circuit board, reducing the number of the mechanical processing part, not depending on a special printed circuit board, shortening the processing time, reducing the manufacturing cost and reducing the cost for testing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail with reference to the accompanying drawings and detailed embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor. Wherein:
fig. 1 is a schematic structural diagram of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be implemented in other ways than those specifically described herein, and one skilled in the art may similarly generalize the present invention without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, for convenience of explanation, the sectional view showing the device structure will not be enlarged partially according to the general scale, and the schematic drawings are only examples, and should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The utility model provides a new construction probe card for testing DFN encapsulation IC can reduce the quantity of machining part, does not rely on dedicated printed circuit board, has shortened process time, reduces the cost of manufacture, for the test reduce the cost, please refer to figure 1, include: a general purpose printed wiring board 100, an epoxy probe card 200, a machined part 300, and a QFN package 400;
referring to fig. 1 again, the general printed circuit board 100 is connected to a printed circuit board socket 110, specifically, the printed circuit board socket 110 is installed on the right side of the top of the general printed circuit board 100, and the printed circuit board socket 110 is connected to an external power supply device to supply power to the general printed circuit board 100.
Referring to fig. 1 again, the epoxy probe card 200 has epoxy probe card inner pins 210, specifically, the epoxy probe card 200 is installed on the left side of the top of the general printed circuit board 100, the epoxy probe card inner pins 210 are uniformly distributed on the top of the epoxy probe card 200, the epoxy probe card 200 is fabricated according to the test positions of the IC pins 410, the general printed circuit board 100 is used to fabricate the epoxy probe card 200, and signals are led out through the general printed circuit board 100.
Referring to fig. 1 again, the machining unit 300 is installed on the top of the epoxy probe card 200, the inner pins 210 of the epoxy probe card are inserted into the machining unit 300, and the machining unit 300, which is fabricated according to the test site and the peripheral size of the packaged IC, is installed on the fabricated epoxy probe card 200 such that the inner pins 210 of the epoxy probe card are exposed by a certain length.
Referring again to fig. 1, QFN package 400 has IC pins 410. specifically, the packaged IC pins 410 of QFN package 400 are placed in a slot at the top of machined part 300, and QFN package 400 is pressed down so that IC pins 410 contact inner pins 210 of epoxy probe card 200, thereby drawing signals from printed circuit board socket 110.
When the method is used specifically, an epoxy probe card 200 is manufactured according to the test position of an IC pin 410, the universal printed circuit board 100 is used to manufacture the epoxy probe card 200, a signal is led out through the universal printed circuit board 100, a machined part 300 which is manufactured according to the test position and the peripheral size of a packaged IC is installed, the inner pin 210 of the epoxy probe card is exposed for a certain length, the IC pin 410 packaged by the QFN package 400 is placed in a groove at the top of the machined part 300, the QFN package 400 is pressed downwards, the IC pin 410 is in contact with the inner pin 210 of the epoxy probe card 200, the signal is led out from a printed circuit board socket 110, the number of the machined parts 300 is reduced, a special printed circuit board is not relied on, the processing time is shortened, the manufacturing cost is reduced, and the cost is reduced for testing.
A plurality of the epoxy probe card inner pins 210 are uniformly distributed on the top of the epoxy probe card 200, so that the epoxy probe card inner pins 210 are uniformly contacted with the IC pins 410.
A plurality of the IC pins 410 are uniformly distributed at the bottom of the QFN package 400, so that the IC pins 410 are uniformly contacted with the inner pins 210 of the epoxy probe card.
A plurality of the epoxy probe card inner pins 210 are exposed at the top of the machining part 300, and the epoxy probe card inner pins 210 are conveniently contacted with the IC pins 410.
The top of the machining part 300 is provided with a clamping groove, and the clamping groove is matched with the QFN package 400, so that the QFN package 400 can be conveniently installed and fixed, and the inner needle 210 of the epoxy probe card can be conveniently contacted with the IC pin 410.
While the invention has been described above with reference to an embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the various features of the disclosed embodiments of the present invention can be used in any combination with each other, and the non-exhaustive description of these combinations in this specification is merely for the sake of brevity and resource conservation. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (5)

1. A probe card of new construction for testing DFN packaged ICs, comprising: the PCB comprises a universal printed circuit board (100), an epoxy probe card (200), a machining part (300) and a QFN package (400), wherein a printed circuit board socket (110) is arranged on the right side of the top of the universal printed circuit board (100), the epoxy probe card (200) is arranged on the left side of the top of the universal printed circuit board (100), a plurality of epoxy probe card inner pins (210) are arranged on the top of the epoxy probe card (200), the machining part (300) is arranged on the top of the epoxy probe card (200), the plurality of epoxy probe card inner pins (210) are inserted into the machining part (300), the QFN package (400) is arranged on the top of the machining part (300), and a plurality of IC pins (410) are arranged at the bottom of the QFN package.
2. The probe card of claim 1, wherein a plurality of said epoxy probe card inner pins (210) are evenly distributed on top of epoxy probe card (200).
3. The new structure probe card for testing DFN packaged ICs as claimed in claim 1, wherein a plurality of said IC pins (410) are evenly distributed at the bottom of QFN package (400).
4. The probe card of claim 1, wherein a plurality of said epoxy probe card inner pins (210) are exposed at the top of a machined part (300).
5. The probe card of claim 1, wherein the machined part (300) is provided with a card slot on top, the card slot is matched with the QFN package (400).
CN202020219296.7U 2020-02-27 2020-02-27 Probe card with new structure for testing DFN packaged IC Expired - Fee Related CN212111533U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202020219296.7U CN212111533U (en) 2020-02-27 2020-02-27 Probe card with new structure for testing DFN packaged IC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202020219296.7U CN212111533U (en) 2020-02-27 2020-02-27 Probe card with new structure for testing DFN packaged IC

Publications (1)

Publication Number Publication Date
CN212111533U true CN212111533U (en) 2020-12-08

Family

ID=73632285

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202020219296.7U Expired - Fee Related CN212111533U (en) 2020-02-27 2020-02-27 Probe card with new structure for testing DFN packaged IC

Country Status (1)

Country Link
CN (1) CN212111533U (en)

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20201208

CF01 Termination of patent right due to non-payment of annual fee