CN215449490U - Semiconductor chip test board card - Google Patents

Abstract

The utility model provides a semiconductor chip test board card for testing the electrical property of an integrated circuit package, which comprises: the test socket comprises a first joint unit, a second joint unit and an insulating support, wherein the insulating support is provided with a plug hole, the first joint unit surrounds the inner side of the plug hole, and the second joint unit is arranged at the center of the plug hole. Through setting up the test seat into the structure of first joint unit and second joint unit, first joint unit centers on the spliced eye can inboard be laid, and spliced eye central point department is located to the second joint unit, can effectual test dedicated integrated circuit package piece, carries out effectual test to the package piece that has the fin simultaneously, simple structure, and it is convenient to make, and is with low costs.

Description

Semiconductor chip test board card

Technical Field

The utility model relates to the technical field of testing, in particular to a semiconductor chip testing board card.

Background

With the increasing trend of electronic products, such as light, thin, short, multi-functional and miniaturized IC processes, the IC package is developed from low-pin dual-pin package, plastic die carrier package to high-pin quad flat package. The quad flat package has leads on the four sides of the package, and the leads are L-shaped. Quad flat packages can be classified into several types, such as plastic quad flat packages, micro quad flat packages, and thin quad flat packages. Common plastic quad flat package (IC) chips have very small pin pitch and very fine pins, and are commonly used for large-scale or very large-scale Integrated Circuit (lsi) packages, and the number of pins is often over 100. The micro quad flat package is a micro and lightweight package, and is generally used for application-specific integrated circuits, digital signal processors, microprocessors/controllers, graphics processors, bipolar arrays, and the like. The thin quad flat package is suitable for miniaturized package, and the height and volume of the thin quad flat package are suitable for miniaturized printed circuit board structure.

After the IC package is completed, sampling tests must be performed before leaving the factory to confirm that the design function has been met. The conventional IC package test requires a bonding test by three main components. Firstly, a test handler of a handling system takes out the packaged IC package from a carrier, and mounts the IC package on a test socket matched with pins of the IC package, and sets environmental parameters. Then, the test socket is connected with a test board, the test board is a conversion interface of the signal transmission contact, and the signal on the pin of the tested IC package can be connected to the test head of the test machine. Finally, the tester executes the preset test program to completely evaluate whether the preset functions of the chip can be achieved.

With the densification of the pins of the IC package, the metal probes to be manufactured are also becoming finer and the density of the metal probes is also increasing, which makes the probe manufacturing difficult and expensive, and the probes are fragile, easy to bend and break.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention has been made to provide a semiconductor chip test board that overcomes or at least partially solves the above problems.

In order to solve the above problems, the present invention discloses a semiconductor chip test board for performing an electrical test on a test integrated circuit package, comprising: the test socket comprises a first joint unit, a second joint unit and an insulating support, wherein the insulating support is provided with a plug hole, the first joint unit surrounds the inner side of the plug hole, and the second joint unit is arranged at the center of the plug hole.

Further, the insulating support is fixedly connected with the test circuit board through threads.

Furthermore, the plug hole is a square hole.

Further, the first jointing units are respectively arranged along four sides of the inner side of the square hole.

Furthermore, the second joint unit is provided with four conductive probes, and the four conductive probes are arranged at the center of the plugging hole.

Furthermore, the testing device also comprises a base, wherein the base is fixedly arranged on the bottom surface of the testing circuit board.

Further, the number of the first engaging units is set to 28.

Further, the integrated circuit package is a QFN package test structure.

Further, the test circuit board further comprises a socket, and the socket is connected with the test circuit board.

The utility model has the following advantages: through setting up the test seat into the structure of first joint unit and second joint unit, first joint unit centers on the spliced eye can inboard be laid, and spliced eye central point department is located to the second joint unit, can effectual test dedicated integrated circuit package piece, carries out effectual test to the package piece that has the fin simultaneously, simple structure, and it is convenient to make, and is with low costs.

Drawings

FIG. 1 is a schematic structural diagram of a semiconductor chip test board according to the present invention;

fig. 2 is a schematic structural diagram of a test socket in a semiconductor chip test board according to the present invention.

1 socket, 2 test circuit board, 3 insulating support, 4 test socket, 41 first jointing unit, 42 second jointing unit.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

One of the core concepts of the present invention is to provide a semiconductor chip test board for performing an electrical test on a test integrated circuit package, comprising: the testing device comprises a testing circuit board 2 and a testing seat 4, wherein the testing seat 4 comprises a first joint unit 41, a second joint unit 42 and an insulating support 3, the insulating support 3 is provided with a plug hole, the first joint unit 41 is arranged around the inner side of the plug hole, and the second joint unit 42 is arranged at the center of the plug hole. Through setting the test socket 4 into the structure of the first jointing unit 41 and the second jointing unit 42, the first jointing unit 41 can be arranged around the inserting hole at the inner side, and the second jointing unit 42 is arranged at the center of the inserting hole, so that the special integrated circuit packaging piece can be effectively tested, and meanwhile, the packaging piece with the radiating fin can be effectively tested, and the test socket has the advantages of simple structure, convenience in manufacturing and low cost.

Referring to fig. 1, a block diagram of a semiconductor chip test board according to the present invention is shown, which is used for performing an electrical test on a test integrated circuit package, and specifically includes: the testing device comprises a testing circuit board 2 and a testing seat 4, wherein the testing seat 4 comprises a first joint unit 41, a second joint unit 42 and an insulating support 3, the insulating support 3 is provided with a plug hole, the first joint unit 41 is arranged around the inner side of the plug hole, and the second joint unit 42 is arranged at the center of the plug hole. In this embodiment, the semiconductor chip test board is used for testing a dedicated integrated circuit package, the dedicated integrated circuit package is a square package, and a heat sink is attached to the surface of the integrated circuit package, the second bonding unit 42 disposed at the center of the insertion hole in this application is used for bonding the heat sink to test the performance of the heat sink, and the first bonding unit 41 is used for bonding the outer contact pins of the square package to electrically test the package.

In this embodiment, the insulating support 3 is fixedly connected to the test circuit board 2 by a screw. Adopt the screw with insulating support 3 and test circuit board 2 fixed connection, its connected mode is stable, easy dismounting.

In this embodiment, the insertion hole is a square hole. The plugging hole is set to be square, a special square packaging piece can be arranged, and the first bonding units 41 are respectively arranged along four sides of the inner side of the square hole, so that the test is stable.

In this embodiment, the second bonding unit 42 is provided with four conductive probes, and the four conductive probes are arranged at the center of the plugging hole. The four conductive probes are used for testing the radiating fin of the special packaging piece. In particular, the conductive probe is a metal probe.

In this embodiment, the testing circuit board further comprises a base, and the base is fixedly arranged on the bottom surface of the testing circuit board.

In the present embodiment, the first engaging units 41 are provided in 28 numbers.

In this embodiment, the ic Package is a QFN (Quad Flat No-leads) Package test structure. QFN is a leadless package, square or rectangular, with a large area of exposed pads at the center of the bottom of the package for heat conduction, and conductive pads surrounding the large pads around the periphery of the package for electrical connection. QFN packages provide excellent electrical performance because they do not have gull-wing leads as do conventional packages, the electrical path between the internal leads and the pads is short, the self-inductance, and the wiring resistance within the package is low. In addition, it provides excellent heat dissipation through the exposed leadframe pad, which has a direct heat dissipation path for dissipating heat within the package. Heat dissipating pads are typically soldered directly to the Circuit Board and heat dissipating vias in the PCB help dissipate excess power into the copper ground plate, thereby absorbing excess heat.

In the embodiment, the test device further comprises a socket 1, and the socket 1 is connected with the test circuit board 2.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The above detailed description is made on the semiconductor chip test board provided by the present invention, and the principle and the implementation of the present invention are explained by applying a specific example, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (9)

1. A semiconductor chip test board for electrically testing a test integrated circuit package, comprising: the test socket comprises a first joint unit, a second joint unit and an insulating support, wherein the insulating support is provided with a plug hole, the first joint unit surrounds the inner side of the plug hole, and the second joint unit is arranged at the center of the plug hole.

2. The semiconductor chip test board of claim 1, wherein the insulating support is fixedly connected to the test circuit board by a screw thread.

3. The semiconductor chip test board of claim 1, wherein the insertion hole is a square hole.

4. The semiconductor chip test board of claim 3, wherein the first bonding units are respectively arranged along four sides of the inside of the square hole.

5. The semiconductor chip test board of claim 1, wherein the second bonding unit is provided with four conductive probes, and the four conductive probes are arranged at the center of the plugging hole.

6. The semiconductor chip test board of claim 1, further comprising a base, wherein the base is fixedly disposed on a bottom surface of the test circuit board.

7. The semiconductor chip test board of claim 1, wherein the number of the first bonding units is 28.

8. The semiconductor chip test board of claim 1, wherein the integrated circuit package is a QFN package test structure.

9. The semiconductor chip test board of claim 1, further comprising a socket, the socket being connected to the test circuit board.

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