CN212010956U

CN212010956U - Bonding wire structure for chip packaging

Info

Publication number: CN212010956U
Application number: CN202020963005.5U
Authority: CN
Inventors: 陈亮; 吴均
Original assignee: Edadoc Co ltd
Current assignee: Edadoc Co ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2020-11-24
Anticipated expiration: 2030-06-01

Abstract

The utility model discloses a bonding wire structure of chip package, including first link, second link and transition end, first link is connected with the chip bonding, the second link is connected with the encapsulation base plate bonding, first link warp the transition end is connected the second link, first link diameter is less than the second link, the size of transition end is from connecting a lateral connection of second link one side of first link evenly reduces. The utility model discloses an add the size that the transition end reduced the bonding wire, make it can enough satisfy the bonding of small-size chip, can make the impedance of bonding wire approach packaging substrate's characteristic impedance again, compare with traditional bonding wire, the utility model discloses an impedance reduces and improves the degree and reaches 8%, and insertion loss falls and improves the degree and reaches 100%, and return loss reaches agreement index requirement completely, fully satisfies the requirement of the high-speed transmission signal of small-size chip, improves signal transmission's quality.

Description

Bonding wire structure for chip packaging

Technical Field

The utility model relates to a chip package technical field, more specifically say, relate to a chip package's bonding wire structure.

Background

System-in-package is essentially a high-density integration technique with certain system functions that integrates multiple active chips, passive devices, MEMS devices, optical devices, etc. in a single package, where an active chip may be referred to as a DIE or an IC in some form of package, a chip-on-board package requires that the DIE be attached to an interconnect substrate using conductive or non-conductive glue, and then wire bonding, which is a form of connection of a DIE to the package substrate using gold wire or other conductor during the process, to achieve electrical connection.

The bonding wires are conductors for electrically connecting the bare chip and the packaging substrate, and signals are transmitted between the bare chip and the packaging substrate through the bonding wires. However, since the bonding wire is exposed in the air and the dielectric constant of the surrounding medium is 1, the impedance of the bonding wire is higher than the characteristic impedance of the transmission line on the package substrate, which causes impedance abrupt change in the transmission process, and the signal is reflected at the bonding wire, thereby affecting the transmission quality of the signal. In addition, the higher the signal rate is, the more the abrupt change of the impedance of the bonding wire has an influence on the signal, which is not favorable for the high-speed transmission requirement of the chip.

The existing method for reducing the impedance of the bonding wire is to use a gold wire with a larger diameter for bonding, however, with the development of miniaturization in the electronic industry, the chip manufacturing process is smaller and smaller, the size of the bare chip is also gradually reduced, the size of the lead of the bare chip is limited, so that the bonding wire adhesion space is limited, the available area of some chips is only 2 mils by 2 mils, the bonding is difficult to use the thicker gold wire, and the requirement of high-speed transmission of small chips cannot be met.

The above disadvantages need to be improved.

Disclosure of Invention

In order to overcome the deficiencies of the prior art, the utility model provides a chip package's bonding wire structure.

The utility model discloses technical scheme as follows:

a bonding wire structure for chip packaging comprises a first connecting end, a second connecting end and a transition end, wherein the first connecting end is in bonding connection with a chip, the second connecting end is in bonding connection with a packaging substrate, the first connecting end is connected with the second connecting end through the transition end, the diameter of the first connecting end is smaller than that of the second connecting end, and the size of the transition end is uniformly reduced from one side connected with the second connecting end to the side connected with the first connecting end.

In the bonding wire structure of the chip package, the length of the second connection end accounts for 70% of the total length of the bonding wire.

In the bonding wire structure of the chip package, the length of the first connection end accounts for 20% of the total length of the bonding wire.

In the bonding wire structure of the chip package, the length of the transition end accounts for 10% of the total length of the bonding wire.

In the bonding wire structure for chip packaging, the first connection end is a cylinder.

In the bonding wire structure for chip packaging, the second connecting end is a cylinder.

In the bonding wire structure for chip packaging, the transition end is in a truncated cone shape.

In the bonding wire structure for chip packaging, the transition end is bent upwards to form an arc shape.

In the bonding wire structure for chip packaging, the transition end is higher than the chip and the packaging substrate.

In the bonding wire structure for chip packaging, the first connection end and the second connection end are respectively inclined to the chip and the packaging substrate.

According to the above scheme the utility model discloses, its beneficial effect lies in, the utility model discloses an add the size that the transition end reduced the bonding wire, make it can enough satisfy the bonding of small-size chip, can make the impedance of bonding wire approach packaging substrate's characteristic impedance again, compare with traditional bonding wire, the utility model discloses an impedance reduces improvement degree and reaches 8%, and insertion loss reduces improvement degree and reaches 100%, and return loss reaches the agreement index completely, fully satisfies the requirement of small-size chip high-speed transmission signal, improves signal transmission's quality.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a schematic structural diagram of the present invention.

Fig. 3 is an impedance comparison diagram of the present invention and a conventional bonding wire structure.

Fig. 4 is an insertion loss comparison diagram of the present invention and a conventional bonding wire structure.

Fig. 5 is a return loss contrast diagram of the present invention and a conventional bonding wire structure.

Wherein, in the figures, the respective reference numerals:

1. a first connection end; 2. a second connection end; 3. a transition end; 4. a chip; 5. and packaging the substrate.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

It will be understood that when an element is referred to as being "fixed" or "disposed" or "connected" to another element, it can be directly or indirectly located on the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

A bonding wire structure for chip packaging is shown in figures 1 and 2 and comprises a first connecting end 1, a second connecting end 2 and a transition end 3, wherein the first connecting end 1 is in bonding connection with a chip 4, the second connecting end 2 is in bonding connection with a packaging substrate 5, the first connecting end 1 is connected with the second connecting end 2 through the transition end 3, the diameter of the first connecting end 1 is smaller than that of the second connecting end 2, and the size of the transition end 3 is uniformly reduced from one side connected with the second connecting end to one side connected with the first connecting end 1.

The utility model discloses an add transition end 3 in order to reduce the size of bonding wire gradually, make it enough satisfy the bonding of small-size chip 4, can make the impedance of bonding wire approach packaging substrate 5's characteristic impedance again, fully satisfy the requirement of the high-speed transmission signal of small-size chip 4, improve signal transmission's quality.

In one embodiment, the length of the first connection end 1 is 20% of the total length of the bonding wire.

In one embodiment, the length of the transition end 3 is 10% of the total length of the bond wire.

In one embodiment, the length of the second connection end 2 is 70% of the total length of the bond wire.

In one embodiment, the first connection end 1 is a cylinder.

In one embodiment, the second connection end 2 is cylindrical.

In one embodiment, the transition end 3 is frustoconical.

In one embodiment, the first connection end 1 has a diameter of 1 mil and a length of 7 mils; second link end 2 has a diameter of 1.8 mils and a length of 24.5 mils; the transition tip 3 has a diameter that transitions from 1 mil to 1.8 mils and a length of 3.5 mils.

In one embodiment, the transition end 3 is curved upwardly in a circular arc shape.

In one embodiment, the transition end 3 is higher than the chip 4 and the package substrate 5.

In one embodiment, the first connection end 1 and the second connection end 2 are respectively inclined to the chip 4 and the package substrate 5.

The first connecting end 1 and the second connecting end 2 are elevated above the chip 4 and the packaging substrate 5, so that the transition end 3 is parallel to the packaging substrate 5 and the chip 4, the connection part of the transition end 3 and the first connecting end 1 and the second connecting end is stable and natural, and meanwhile, the connection part is convenient to be connected with the chip 4 and the packaging substrate 5, and the arrangement of the chip 4 and the packaging substrate 5 is not influenced.

Compare with traditional bonding wire, the utility model has the advantages of as follows:

1. as shown in fig. 3, the dotted line represents the impedance of the conventional bonding wire, and the solid line represents the impedance of the present invention, it can be known that the impedance of the present invention is reduced by about 10 ohms compared with the conventional bonding wire, and the improvement degree reaches 8%.

2. As shown in fig. 4, the broken line represents the insertion loss of traditional bonding wire, and the solid line represents the utility model discloses an insertion loss can be known the utility model discloses an insertion loss is low than the insertion loss of traditional bonding wire, when the frequency is 15GHz, the utility model discloses an insertion loss reduces 0.575dB than traditional bonding wire, and the improvement degree reaches 100%.

3. As shown in fig. 5, the solid line represents the return loss that CEI-28G-VSR protocol index required, and the dot-dash line represents the return loss of traditional bonding wire, and the dotted line represents the utility model discloses a return loss, can know the utility model discloses a return loss is lower than traditional bonding wire to fully satisfy the protocol index requirement.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. The bonding wire structure for chip packaging is characterized by comprising a first connecting end, a second connecting end and a transition end, wherein the first connecting end is in bonding connection with a chip, the second connecting end is in bonding connection with a packaging substrate, the first connecting end is connected with the second connecting end through the transition end, the diameter of the first connecting end is smaller than that of the second connecting end, and the size of the transition end is uniformly reduced from one side connected with the second connecting end to the side connected with the first connecting end.

2. The bond wire structure of a chip package according to claim 1, wherein the length of the second connecting terminal is 70% of the total length of the bond wire.

3. The bonding wire structure of a chip package according to claim 1, wherein the length of the first connection end is 20% of the total length of the bonding wire.

4. The bond wire structure of a chip package of claim 1, wherein the length of the transition end is 10% of the total length of the bond wire.

5. The bonding wire structure of chip package according to claim 1, wherein the first connecting end is a cylinder.

6. The bond wire structure of a chip package of claim 1, wherein the second connecting end is cylindrical.

7. The bond wire structure of a chip package of claim 1, wherein said transition end is frustoconical.

8. The bonding wire structure of a chip package according to claim 1, wherein the transition end has a circular arc shape.

9. The bonding wire structure of chip package according to claim 1, wherein the transition end is higher than the chip and the package substrate.

10. The bonding wire structure of chip package according to claim 1, wherein the first connection end and the second connection end are respectively inclined to the chip and the package substrate.