CN216563117U

CN216563117U - Component packaging structure and optical module with same

Info

Publication number: CN216563117U
Application number: CN202122281202.6U
Authority: CN
Inventors: 汪振中; 贾秀红
Original assignee: Innolight Technology Suzhou Ltd
Current assignee: Innolight Technology Suzhou Ltd
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2022-05-17
Anticipated expiration: 2031-09-18

Abstract

The utility model provides a component packaging structure and an optical module with the same, wherein the component packaging structure comprises a circuit board and a chip, the upper surface of the chip is provided with at least one chip bonding pad, the surface of the circuit board is provided with a wiring layer, the wiring layer comprises at least one connecting end arranged close to the chip, the component packaging structure also comprises at least one transition substrate arranged on the circuit board, and the height of the transition substrate is less than that of the chip; the transition substrate is close to the chip, the upper surface of the transition substrate is provided with a transition bonding pad, the chip bonding pad is electrically connected with the transition bonding pad through a first bonding lead, and the transition bonding pad is electrically connected with the connecting end of the wiring layer. The transition substrate is arranged between the chip and the connecting end of the wiring layer to serve as a transition structure for lead connection, so that the length of a chip bonding lead is shortened, and the inductance formed by the lead is reduced.

Description

Component packaging structure and optical module with same

Technical Field

The utility model relates to the technical field of electronic packaging, in particular to a component packaging structure and an optical module with the same.

Background

In the field of optical modules and the like, a wire bonding process is the most widely used technology in the electrical connection process of chip components, is simple and easy to use, is suitable for mass production, and generally arranges a chip on a circuit board or a substrate and interconnects the chip and the circuit board through a wire. The lead generally exhibits an inductive component, and the longer the line length and the wider the line width are, the more serious the reduction, so that the PCB (Printed Circuit Board) design increases the pad area on the original transmission line impedance, thereby increasing the capacitance and improving the bandwidth.

In practical use, the thickness of the chip is relatively thick, which may result in an excessively long lead length from the chip to the circuit board if the chip is placed on the circuit board (PCB). If the chip is arranged at the edge of the circuit board, the manufacturing tolerance needs to be considered and the chip is limited by the existing circuit board processing technology, a certain distance is reserved between a pad of the circuit board and the edge of the circuit board, and the lead needs to extend further inwards the circuit board, so that the length of the lead is further increased, and the lead forms larger inductance to influence the bandwidth of the optical module.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a component packaging structure and an optical module with the same, which can effectively improve bandwidth.

The utility model provides a component packaging structure, which comprises a circuit board and a chip, wherein at least one chip bonding pad is arranged on the upper surface of the chip, a wiring layer is formed on the surface of the circuit board, the wiring layer comprises at least one connecting end arranged close to the chip, the component packaging structure also comprises at least one transition substrate arranged on the circuit board, and the height of the transition substrate is smaller than that of the chip;

the transition substrate is adjacent to the chip, a transition bonding pad is arranged on the upper surface of the transition substrate, the chip bonding pad is electrically connected with the transition bonding pad through a first bonding lead, and the transition bonding pad is electrically connected with the connecting end of the wiring layer.

As a further improvement of the present invention, the transition substrate is a capacitive substrate.

As a further improvement of the present invention, the transition substrate includes at least one dielectric layer and an upper conductive layer and a lower conductive layer respectively disposed on the upper and lower surfaces of the dielectric layer, wherein the transition pad is located on the upper conductive layer.

As a further improvement of the present invention, the transition substrate is fixedly connected to the circuit board through a conductive adhesive, and the conductive adhesive layer forms the lower conductive layer.

As a further improvement of the utility model, the transition substrate is a ceramic substrate, a silicon substrate, an aluminum nitride substrate or an aluminum oxide substrate.

As a further improvement of the present invention, the wiring layer connection terminals include a signal connection terminal and a ground connection terminal.

As a further improvement of the present invention, the transition pad is electrically connected to the wiring layer connection terminal through a second bonding wire.

As a further improvement of the present invention, each of the transition pads is electrically connected to the corresponding connection terminal of the wiring layer through at least two second bonding wires.

As a further improvement of the present invention, the transition pad is electrically connected to the wiring layer connection terminal through a conductive via.

As a further improvement of the present invention, the package structure includes at least two transition substrates, the heights of the at least two transition substrates are gradually reduced from the chip side to the connection end side of the wiring layer, and corresponding transition pads of the at least two transition substrates are electrically connected in sequence;

or the transition substrate is provided with at least two steps, the height of the at least two steps is gradually reduced from the direction close to the chip side to the circuit board connecting end, and the transition bonding pads are arranged on the step surfaces of the at least two steps.

The utility model also provides an optical module which comprises the assembly packaging structure.

The utility model has the beneficial effects that: the transition substrate is arranged between the connecting end of the chip and the circuit board and used as a transition structure for lead connection, the length of a chip bonding lead is shortened, so that the inductance formed by the lead is reduced, meanwhile, a CLCLCLC equivalent transmission line structure is formed among the circuit board, the capacitive transition substrate and the chip and matched with the impedance of the circuit board, so that the impedance matching problem of the whole link can be effectively improved, and the bandwidth of the link is improved.

Drawings

Fig. 1 is a schematic view of a package structure of the device in embodiment 1 of the present invention.

Fig. 2 is a top view of a package structure of the device in embodiment 1 of the present invention.

Fig. 3 is a schematic view of a package structure of the device in embodiment 2 of the present invention.

Fig. 4 is a top view of a package structure of the device in embodiment 2 of the present invention.

Fig. 5 is a schematic view of a package structure of the device in embodiment 3 of the present invention.

Fig. 6 is a top view of a package structure of the device in embodiment 3 of the present invention.

Fig. 7 is a schematic diagram of a package structure of the device in embodiment 3 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.

Example 1

As shown in fig. 1 and fig. 2, a package structure 1 for a component according to embodiment 1 of the present invention includes a circuit board 11, a chip 12, and at least one transition substrate 13, where the chip 12 is disposed on the circuit board 11, and a plurality of chip pads 121 are disposed on an upper surface of the chip 12 and used as input/output terminals of the chip 12. The circuit board 11 has a wiring layer 111 formed on a surface thereof, and the wiring layer 111 includes a wiring layer connection terminal 1111 disposed adjacent to the chip 12.

In this embodiment, the package structure 1 is applied to an optical module, and the high-speed chip 12 disposed on the circuit board 11 may be a DSP digital signal processor, a DRV laser driver, a TIA transimpedance amplifier, an LD laser chip, or a PIC integrated photonic chip.

The transition substrate 13 is located on one side of the chip 12 adjacent to the wiring layer connection end 1111, and the height of the transition substrate 13 is lower than that of the chip 12, the transition pad 131 is arranged on the upper surface of the transition substrate 13, the chip pad 121 and the transition pad 131 are electrically connected through the first bonding wire 14, and the transition pad 131 and the wiring layer connection end 1111 are electrically connected through the second bonding wire 15.

It should be noted that the wiring layer connection terminal 1111 is referred to as a position of the wiring layer 111 facing the chip 12 for electrical connection with the transition substrate 13, and is not strictly at the end of the wiring layer 111.

The first bonding wire 14 and the second bonding wire 15 are metal wires such as gold wires, silver wires, and copper wires, and specifically, gold wires are used as the wires in the present embodiment.

Usually, the chip 12 has a certain thickness, the chip 12 disposed on the circuit board 11 has a larger height difference with the circuit board 11, and is directly wire-bonded to the circuit board 11 from the chip pad 121, and the wire-bonding length is longer, which easily causes problems such as impedance mismatch of the link, thereby affecting the link bandwidth. Here, by providing the transition substrate 13 as a transition structure of the wire connection between the chip 12 and the connection end of the wiring layer 111, the transition pad height of the transition substrate 13 is between the chip pad and the connection end of the wiring layer of the circuit board, so that a single long wire originally connected directly from the chip pad 121 to the connection end of the wiring layer 111 is divided into a plurality of short wires. According to a calculation formula of gold wire inductance:

wherein L is_wThe inductance of the gold wire is shown, l is the length of the gold wire, and d is the diameter of the gold wire, so that the inductance of the gold wire and the length of the gold wire are logarithmic, the inductance formed by a plurality of short leads is smaller than the inductance formed by a long lead, therefore, the chip 12 is electrically connected to the wiring layer connecting end 1111 by combining a plurality of short leads instead of a long lead through the transition substrate, the inductance of the leads can be reduced, the impedance matching of a link is improved, and the bandwidth of the link is improved.

The transition substrate 13 may be a split structure, and is respectively located at the side regions of the chip 12 where the bonding pads are disposed. When the bonding pads are disposed on all four sides of the chip 12, the transition substrate 13 may be a frame structure enclosing the chip 12, and the specific structure and distribution position of the transition substrate 13 on the periphery of the chip 12 may be specifically adjusted according to the sizes, wiring patterns, and the like of the chip 12 and the circuit board 11, so long as the transition substrate 13 is used as a transition connection structure of the leads.

Specifically, in the present embodiment, a transition substrate 13 is disposed on the side of the chip 12, the chip pad 121 and the transition substrate 13 are connected by a first bonding wire 14, and the transition substrate 13 and the connection end of the wiring layer 111 are connected by a second bonding wire 15, so that the wires form a two-step structure.

Furthermore, as shown in fig. 2, since the transition pads 131 have a larger area than the die pads 121, a plurality of second bonding wires 15 can be disposed between each transition pad 131 and the corresponding wiring layer connection 1111 to achieve electrical connection, and the plurality of wires arranged densely can further reduce the inductance of the wires. Specifically, in the present embodiment, each transition pad 131 and the connection terminal of the wiring layer 111 are connected by two leads. The distance between two adjacent leads can be specifically adjusted according to the size of the transition pad 131, the actual inductance of the leads, and other factors.

Since there is a difference in the number of the leads, the chip pad 121 and the transition pad 131 are usually electrically connected by one first bonding lead 14, the transition pad 131 and the wiring layer connection 1111 are electrically connected by a plurality of second bonding leads 15, and the spacing distance between the adjacent second bonding leads 15 is different from the spacing distance between the adjacent first bonding leads 14, therefore, the specific height of the transition pad 131 can be determined by simulation or simulation combined with actual measurement, so as to minimize the inductance formed by the entire leads.

The transition substrate 13 is a capacitive substrate, so that the component package structure 1 is formed from the chip 12, the first bonding wire 14, the transition substrate 13, the second bonding wire 15 to a CLCLC structure of the circuit board 11 (C represents a capacitive component, and L represents an inductive component), and an equivalent transmission line structure of the structure is matched with the impedance of the circuit board 11, so that the impedance matching of the entire link can be improved, and the link bandwidth can be increased.

Specifically, the transition substrate 13 includes at least one dielectric layer 13a and an upper conductive layer 13b and a lower conductive layer 13c respectively disposed on the upper and lower surfaces of the dielectric layer 13a, so that the transition substrate 13 integrally forms a parallel plate capacitor structure in which the transition pad 131 is located on the upper conductive layer 13b, which is a gold plating layer.

The lower surface of the transition substrate 13 is fixedly connected to the circuit board 11 by a conductive adhesive 133 such as silver paste, and the conductive adhesive 133 layer not only can play a role of structural fixation, but also forms the lower conductive layer 13c, and forms a parallel plate capacitor structure together with other structures of the transition substrate 13. In other embodiments of the present invention, a metal layer may be additionally disposed on the bottom of the transition substrate 13 as the lower conductive layer 13 c.

Further, as shown in fig. 2, the wiring layer connection terminal 1111 includes a signal connection terminal 1111a and a ground connection terminal 1111b, and the lower conductive layer 13c of the transition substrate 13 is insulated from the signal connection terminal 1111a to avoid short circuit. The lower conductive layer 13c of the intermediate substrate 13 is electrically connected to the ground connection terminal 1111 b.

The dielectric layer 13a is a ceramic substrate, a silicon substrate, an aluminum nitride substrate, or an aluminum oxide substrate.

Preferably, the dielectric layer 13a is a ceramic substrate 132, the ceramic substrate 132 has excellent workability and high dimensional accuracy, the transition substrate 13 of a ceramic structure is provided at the chip 12 and the wiring layer connection terminals 1111, the manufacturing tolerance of the circuit board 11 can be compensated, and the lead-out distance on the chip pad 121 can be further shortened by providing the transition substrate 13 at a position adjacent to the side of the chip 12.

In other embodiments, other materials may be used as dielectric layer 13a of transition substrate 13, as long as a parallel plate capacitor structure can be formed in cooperation with upper conductive layer 13b and lower conductive layer 13 c.

Example 2

As shown in fig. 3 and 4, for a package structure 2 of a component provided in embodiment 2 of the present invention, the general structure is similar to that of embodiment 1, and the package structure is applied to an optical module, where a high-speed chip 22 disposed on a circuit board 21 may be a DSP digital signal processor, a DRV laser driver, a TIA transimpedance amplifier, an LD laser chip, or a PIC integrated photonic chip, and the difference from embodiment 1 is that:

the chip 22 is disposed outside the circuit board 21 and near the board edge of the circuit board, the high-speed chip 22 disposed on the board edge of the circuit board 21 may be a PIC integrated photonic chip, a DRV driver chip, or a TIA transimpedance amplifier, and the high-speed chips 22 may be disposed on a heat sink 23.

In addition, the high-speed chip 22 at the edge of the circuit board 21 may also be an LD laser chip, which is usually disposed on a substrate to form a COC (chip on carrier) structure, and the COC is then placed on a heat sink 23, and the substrate of the COC is electrically connected to the transition substrate through bonding wires.

Considering the manufacturing tolerance and being limited by the existing circuit board processing technology, the distance from the pad (connecting end) of the circuit board to the edge of the circuit board is large, usually more than 100 μm, which causes the lead from the chip to the pad of the circuit board to extend further into the circuit board, i.e. the length of the lead line is further increased, so that the lead forms a large inductance, which affects the bandwidth of the optical module. In the embodiment, the transition substrate is arranged on the circuit board close to the chip, the distance from the transition bonding pad of the transition substrate 13 to the edge of the transition substrate can be reduced to be within 30 micrometers, and the first bonding lead is only electrically connected with the chip bonding pad and the transition bonding pad, so that the length of the bonding lead can be greatly shortened. Through the switching of the transition substrate, the problem of long routing between the chip and the circuit board is solved, and the impedance matching of the link is improved, so that the bandwidth of the link is improved.

Example 3

As shown in fig. 5 and fig. 6, for a package structure 3 of a component provided in embodiment 3 of the present invention, the general structure of which is similar to that of embodiment 1, and which is applied to an optical module, a high-speed chip 32 disposed on a circuit board 31 may be a DSP digital signal processor, a DRV laser driver, a TIA transimpedance amplifier, an LD laser chip, or a PIC integrated photonic chip, and the difference between the package structure and the embodiment 1 is that:

the transition pad 33 is electrically connected to the wiring layer connection terminal 3111 through a conductive via 331, the conductive via 331 penetrates the transition substrate, a conductive medium is disposed in the transition substrate, and the transition substrate 33 can be soldered on a circuit board through a Surface Mount Technology (SMT).

Example 4

As shown in fig. 7, a package assembly 4 provided in embodiment 4 of the present invention has a general structure similar to that of embodiment 1, and is applied to an optical module, where a high-speed chip 42 disposed on a circuit board 41 may be a DSP digital signal processor, a DRV laser driver, a TIA transimpedance amplifier, an LD laser chip, or a PIC integrated photonic chip, and is different from that of embodiment 1 in that:

at least two transition substrates 43 are arranged between the chip 42 and the wiring layer connecting end 4111, the heights of the transition substrates 43 are gradually reduced from the chip 42 side to the wiring layer connecting end 4111 side, the chip bonding pad 421 is connected to the closest transition bonding pad 431 through a first bonding lead 44, and the transition substrates 43 are electrically connected sequentially through a second bonding lead 45 according to the arrangement sequence, so that the leads form a multi-section short lead structure, and the inductance formed by the leads is further reduced. When a plurality of transition substrates 43 are provided, a plurality of second bonding wires 45 may be provided between two adjacent transition substrates 13 to realize electrical connection. In other embodiments, the at least two transition substrates may be replaced by a single transition substrate having at least two steps, wherein the height of each step is gradually reduced from the direction close to the chip side to the circuit board connection end, and the surface of each step is provided with a transition pad.

The utility model also provides an optical module which comprises a shell and the assembly packaging structure arranged in the shell.

In summary, the transition substrate is arranged between the chip and the connecting end of the wiring layer to serve as a transition structure for lead connection, multiple short leads are formed to replace a single long lead, so that inductance formed by the long leads is effectively reduced, the capacitive transition substrate and other parts of the component packaging structure form a CLCLCLC structure, and an equivalent transmission line structure is matched with impedance of a circuit board, so that impedance matching of the whole link can be effectively improved, and the bandwidth of the link is improved.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.

The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.

Claims

1. The utility model provides a subassembly packaging structure, includes circuit board and chip, the chip upper surface is provided with at least one chip pad, the circuit board surface is formed with the wiring layer, the wiring layer is including closing on at least one link that the chip was arranged, its characterized in that:

the component packaging structure further comprises at least one transition substrate arranged on the circuit board, and the height of the transition substrate is smaller than that of the chip;

the transition substrate is close to the chip, the transition substrate upper surface is provided with a transition pad, the chip pad with through first bonding lead electric connection between the transition pad, transition pad electric connection the link of wiring layer.

2. The device package structure of claim 1, wherein the transition substrate is a capacitive substrate.

3. The component package structure of claim 2, wherein the transition substrate comprises at least one dielectric layer and an upper conductive layer and a lower conductive layer respectively disposed on upper and lower surfaces of the dielectric layer, wherein the transition pad is located on the upper conductive layer.

4. The device package structure of claim 3, wherein the transition substrate is fixedly connected to the circuit board by a conductive adhesive, and the conductive adhesive layer forms the lower conductive layer.

5. The device package structure of claim 2, wherein the transition substrate is a ceramic substrate, a silicon substrate, an aluminum nitride substrate, or an aluminum oxide substrate.

6. The component packaging structure of claim 1, wherein the routing layer connection terminals include signal connection terminals and ground connection terminals.

7. The component package structure of claim 1, wherein the transition pad is electrically connected to the routing layer connection terminal by a second bonding wire.

8. The component package structure of claim 7, wherein each of the transition pads is electrically connected to the corresponding routing layer connection end by at least two of the second bonding wires.

9. The component packaging structure of claim 1, wherein the transition pad is electrically connected to the routing layer connection end by a conductive via.

10. The device package structure of claim 1, wherein the device package structure comprises at least two transition substrates, the height of the at least two transition substrates gradually decreases from the chip side to the wiring layer connection end side, and corresponding transition pads of the at least two transition substrates are electrically connected in sequence;

11. A light module comprising a package according to any one of claims 1 to 10.