KR100708887B1 - multi chip package device with lead frame - Google Patents

multi chip package device with lead frame Download PDF

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KR100708887B1
KR100708887B1 KR1020050044849A KR20050044849A KR100708887B1 KR 100708887 B1 KR100708887 B1 KR 100708887B1 KR 1020050044849 A KR1020050044849 A KR 1020050044849A KR 20050044849 A KR20050044849 A KR 20050044849A KR 100708887 B1 KR100708887 B1 KR 100708887B1
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chip
lead frame
active surface
chips
stacked
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KR1020050044849A
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Korean (ko)
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KR20060122404A (en
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김재준
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디엔제이 클럽 인코
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body

Abstract

본 발명은 리드 프레임이 포함된 칩 적층 패키지 소자에 관한 것으로, 보다 구체적으로는 적층된 복수의 칩을 비아 홀을 통하여 전기적으로 연결하는, 리드 프레임이 포함된 칩 적층 패키지 소자에 관한 것이다.The present invention relates to a chip stack package device including a lead frame, and more particularly, to a chip stack package device including a lead frame that electrically connects a plurality of stacked chips through via holes.

본 발명은, 몰딩부 내부에 위치된 패들에 활성면과 비활성면을 구비하는 복수의 칩이 적층되며 와이어 본딩을 통하여 리드 프레임에 접속되는 패키지 소자로서, 상기 패들에 제1칩의 비활성면이 접착되고, 활성면에 형성된 패드가 리드 프레임에 접속되는 제2칩을 포함하여 적어도 하나의 다른 칩이 제1칩의 활성면에 적층되며, 다른 칩의 활성면과 제1칩의 활성면은 도전성 라인으로 연결된다.The present invention relates to a package device in which a plurality of chips having an active surface and an inactive surface are stacked on a paddle positioned inside a molding unit and connected to a lead frame through wire bonding, wherein the non-active surface of the first chip is adhered to the paddle. At least one other chip is stacked on the active surface of the first chip, including a second chip having a pad formed on the active surface connected to the lead frame, and the active surface of the other chip and the active surface of the first chip are conductive lines. Is connected.

본 발명은 멀티 미디어 및 정보 통신 산업의 급격한 발전에 따른 고집적 및 고성능 반도체 칩에 대한 요구에 부흥하여 제조공정이 간단하고 경제적인 패키지를 제공하는 효과가 있다. The present invention has the effect of providing a package with a simple and economical manufacturing process in response to the demand for high-integration and high-performance semiconductor chip due to the rapid development of the multimedia and telecommunication industry.

리드 프레임, 패키지, 도전성 라인, 비아 홀, 와이어 본딩 Lead Frame, Package, Conductive Line, Via Hole, Wire Bonding

Description

리드 프레임이 포함된 칩 적층 패키지 소자{multi chip package device with lead frame}Multi chip package device with lead frame

도1은 종래의 복수의 메모리 칩을 적층한 패키지(stacked package)를 도시한 도면,1 is a diagram illustrating a stacked package of a plurality of conventional memory chips;

도2는 종래의 다른 복수의 메모리 칩을 적층한 패키지(dual die package)를 도시한 도면,FIG. 2 is a diagram illustrating a conventional dual die package in which a plurality of conventional memory chips are stacked; FIG.

도3은 종래의 또 다른 복수의 메모리 칩을 적층한 패키지(multi chip package)를 도시한 도면,FIG. 3 is a diagram illustrating a conventional multi chip package in which a plurality of conventional memory chips are stacked; FIG.

도4는 본 발명의 일실시예에 따른 리드 프레임이 포함된 칩 적층 패키지 소자를 도시한 도면이다.4 is a diagram illustrating a chip stack package device including a lead frame according to an embodiment of the present invention.

<도면 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 리드 프레임이 포함된 칩 적층 패키지 소자100: chip stack package element with lead frame

110 : 몰딩부 120 : 패들110: molding part 120: paddle

130,132,133,134 : 칩 136 : 도전성 라인130,132,133,134: chip 136: conductive line

138 : 도전성 탄성 중합체 140 : 리드 프레임138: conductive elastomer 140: lead frame

142 : 와이어142: wire

본 발명은 리드 프레임이 포함된 칩 적층 패키지 소자에 관한 것으로, 보다 구체적으로는 적층된 복수의 칩을 비아 홀을 통하여 전기적으로 연결하는, 리드 프레임이 포함된 칩 적층 패키지 소자에 관한 것이다.The present invention relates to a chip stack package device including a lead frame, and more particularly, to a chip stack package device including a lead frame that electrically connects a plurality of stacked chips through via holes.

일반적으로, 패키지 소자란 웨이퍼 공정에 의해 만들어진 개개의 칩(chip)을 실제 전자부품으로 사용할 수 있도록 전기적으로 연결해주고, 외부의 충격에 보호되도록 밀봉 포장한 소자를 말한다. In general, a package device refers to a device packaged in such a way as to electrically connect individual chips made by a wafer process to be used as actual electronic components and to protect against external impact.

이러한 패키지 소자는 통상 웨이퍼에서 만들어진 칩을 칩 지지 패들(paddle)에 부착하고, 칩 내부의 전기적 연결 단자와 패키지의 전기 연결 단자인 리드 프레임(lead frame)을 전기 도선으로 연결하며, 패키지 내부 칩 및 전기 도선을 보호하기 위하여 플라스틱(plastic) 또는 세라믹(ceramic)동과 같은 몰딩(molding) 물질로 밀봉된 구조를 가진다.Such a package device attaches a chip made from a wafer to a chip support paddle, and connects an electrical connection terminal inside the chip and a lead frame, which is an electrical connection terminal of the package, with electrical leads, In order to protect the electric conductors, the structure is sealed with a molding material such as plastic or ceramic copper.

최근 멀티 미디어 및 정보 통신 산업이 급격히 발전하면서, 고집적 및 고성능 반도체 칩에 대한 지속적인 요구가 증대하고 있다. 이에 따라 칩 사이즈(chip size)가 축소되고 연결 단자는 증가하게 되면서, 칩 제조 보다는 패키지(package)의 물리적, 전기적 특성에 따른 문제가 발생하게 되어, 칩 내부의 전기적 연결 단자와 패키지의 전기 연결 단자인 리드 프레임간의 간격을 좁히는 방법을 통하여 패키지가 생산되고 있다.Recently, with the rapid development of the multimedia and telecommunications industry, there is an increasing demand for highly integrated and high performance semiconductor chips. As a result, the chip size is reduced and the connection terminals are increased, thereby causing problems due to physical and electrical characteristics of the package rather than chip manufacturing. Packages have been produced by narrowing the spacing between in-lead frames.

또한 패키지 형태는 기존의 리드 프레임 방식과는 다른 볼(ball) 방식의 BGA(ball grid array) 패키지 형태가 증가하고 있으며, 패키지의 크기가 장착된 칩의 크기에 가까운 CSP(chip scale package) 패키지 형태로 발전되고 있다. In addition, the package type is increasing in the form of ball grid array (BGA) package of ball method different from the conventional lead frame method, chip size package (CSP) package type close to the size of the chip mounted package size Is being developed.

한편 메모리 칩의 고집적화는 메모리 칩 용량 자체를 키우는 방식과 복수의 메모리 칩을 적층하여 패키지화하는 방식으로 나눌 수 있다.On the other hand, high integration of the memory chip may be divided into a method of increasing the memory chip capacity itself and a method of stacking and packaging a plurality of memory chips.

도1 내지 도3은 종래 복수의 메모리 칩을 적층한 패키지를 도시한 도면이다.1 to 3 are diagrams illustrating a package in which a plurality of conventional memory chips are stacked.

먼저 도1을 참조하면, 종래의 복수의 메모리 칩을 적층한 패키지(stacked package)는, 패키지의 리드프레임의 접속에 의하여 에폭시 몰딩 컴파운드 내부에 위치된 칩(chip)들이 전기적으로 연결되는 구조를 가진다. 즉, 리드 프레임이 장착된 노말 패키지(normal package)를 플렉스 서킷(flex circuit)을 이용하여 상하로 적층함으로써 하나의 패키지 실장 면적에 메모리의 집적도를 2배로 증가시키는 구조를 가진다.First, referring to FIG. 1, a stacked package of a plurality of conventional memory chips has a structure in which chips located in an epoxy molding compound are electrically connected by connecting leadframes of the package. . That is, by stacking a normal package (mounted package) with a lead frame up and down using a flex circuit (flex circuit) has a structure that doubles the density of memory in one package mounting area.

그러나 이러한 구조는 하부 칩과 상부 칩이 각각 메모리 모듈 PCB 포인트까지 거리가 차이가 나게 되므로 전기적 특성이 달라지는 문제점이 있다.However, this structure has a problem in that the electrical characteristics of the lower chip and the upper chip are different since the distances to the memory module PCB points are different.

다음으로 도2를 참조하면, 종래의 다른 복수의 메모리 칩을 적층한 패키지(dual die package)는, 에폭시 몰딩 컴파운드 내부에 2개의 칩을 실장하고, 각각의 칩으로부터 리드 프레임을 에폭시 컴파운드 외부로 인출하는 구조를 가진다. 즉 다운 세트 및 업 세트된 리드 프레임을 트랜스퍼 몰딩(transfer molding)한 후, 트림/폼(trim/form)을 진행한 패키징 기술을 이용하여 메모리 집적도를 2배로 증가시키는 구조를 가진다.Next, referring to FIG. 2, in the conventional dual die package in which a plurality of memory chips are stacked, two chips are mounted in an epoxy molding compound, and a lead frame is drawn out of the epoxy compound from each chip. It has a structure That is, the memory module has a structure of doubling the memory density by using a packaging technique in which a trim / form is performed after transfer molding the down-set and up-set lead frames.

그러나 이러한 구조는 2개의 리드 프레임을 동시에 트림/폼을 행하여야 하므로 정확한 아웃 리드(out lead)를 형성하기 어렵고, 트림을 행할 때 사용하는 트림 펀치(trim punch) 등의 마모가 발생할 우려가 있다.However, such a structure is difficult to form an accurate out lead because two lead frames must be trimmed / formed at the same time, and there is a fear that wear such as a trim punch used when trimming occurs.

마지막으로 도3을 참조하면, 종래의 또 다른 복수의 메모리 칩을 적층한 패키지(multi chip package)는, 에폭시 몰딩 컴파운드 내부에 2개의 칩이 적층되고, 각각의 칩은 와이어 본딩(wire bonding)을 통하여 패키지 하면에 형성된 솔더 볼(solder ball)에 접속되는 구조를 가진다. 즉, 적층된 칩은 더블 앤 롱 와이어 본딩(double and long wire bonding)을 통하여 외부 연결 단자인 솔 더볼에 접속된 CSP(chip scale package) 구조를 가진다.Finally, referring to FIG. 3, in another conventional multi chip package, two chips are stacked in an epoxy molding compound, and each chip is wire bonded. It has a structure that is connected to the solder ball (solder ball) formed on the lower surface of the package through. That is, the stacked chips have a CSP (chip scale package) structure connected to a solder ball, which is an external connection terminal, through double and long wire bonding.

이러한 구조는 칩 사이즈(chip size)가 한정되는 셀룰러 폰(cellular phone)또는 모아일 어플리케이션(application)에 널리 이용되고 있지만, 제조 공정이 복잡한 CSP 공정을 통해 제작되어야 하는 문제점이 있다.Such a structure is widely used in cellular phones or mobile applications in which chip size is limited, but there is a problem that a manufacturing process must be manufactured through a complicated CSP process.

본 발명은 상술한 문제점을 해결하기 위하여 창안된 것으로, 에폭시 몰딩 컴파운드 내부에 복수의 칩을 적층하고, 비아 홀을 통하여 적층된 복수의 칩을 전기적으로 연결하여 상부 칩을 리드 프레임과 와이어 본딩하는, 리드 프레임이 포함된 칩 적층 패키지 소자를 제공하는데 그 목적이 있다.The present invention was devised to solve the above-described problems, and a plurality of chips are stacked in an epoxy molding compound, and the plurality of chips electrically connected through the via holes are electrically bonded to the lead frame by wire bonding. An object of the present invention is to provide a chip stack package device including a lead frame.

본 발명의 다른 목적 및 장점들은 하기에 설명될 것이며, 본 발명의 실시예에 의해 알게 될 것이다. 또한, 본 발명의 목적 및 장점들은 특허청구범위에 나타 낸 수단 및 조합에 의해 실현될 수 있다.Other objects and advantages of the invention will be described below and will be appreciated by the embodiments of the invention. In addition, the objects and advantages of the present invention can be realized by the means and combinations indicated in the claims.

상기와 같은 목적을 달성하기 위한 본 발명은, 몰딩부 내부에 위치된 패들에 활성면과 비활성면을 구비하는 복수의 칩이 적층되며 와이어 본딩을 통하여 리드 프레임에 접속되는 패키지 소자로서, 상기 패들에 제1칩의 비활성면이 접착되고, 활성면에 형성된 패드가 상기 리드 프레임에 접속되는 제2칩을 포함하여 적어도 하나의 다른 칩이 상기 제1칩의 활성면에 적층되며, 다른 칩의 활성면과 제1칩의 활성면은 도전성 라인으로 연결된다.The present invention for achieving the above object, a plurality of chips having an active surface and an inactive surface is stacked on the paddle located inside the molding portion and is a package element connected to the lead frame through wire bonding, At least one other chip is laminated to the active surface of the first chip, including the second chip to which the inactive surface of the first chip is bonded, and a pad formed on the active surface is connected to the lead frame, and the active surface of the other chip And the active surface of the first chip are connected by conductive lines.

여기에서 상기 패들에는 접착제가 도포되는 것이 바람직하다.In this case, it is preferable that an adhesive is applied to the paddle.

또한 상기 패드는 알루미늄을 기반으로 하는 금속 층으로 형성될 수 있다.The pad may also be formed of a metal layer based on aluminum.

또한 상기 도전성 라인은 상기 다른 칩을 관통하는 홀이나 홀의 일부를 이용하여 형성되는 것이 바람직하다.In addition, the conductive line is preferably formed using a hole or a part of the hole penetrating the other chip.

또한 상기 홀은 드릴(drill) 또는 식각(etching) 중 어느 하나의 방법으로 형성될 수 있다.In addition, the hole may be formed by any one method of drilling or etching.

또한 상기 도전성 라인은 텡스텐(W), 티타늄(Ti), 알루미늄(Al), 지르코늄(Zr), 크롬(Cr), 구리(Cu), 니켈(Ni), 금(Au), 은(Ag), 납(Pd) 또는 인듐 주석 화합물(ITO: Indium Tin Oxide) 중 적어도 하나를 포함하여 형성될 수 있다.In addition, the conductive line is tungsten (W), titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), copper (Cu), nickel (Ni), gold (Au), silver (Ag) It may be formed including at least one of lead (Pd) or indium tin oxide (ITO).

이하 첨부된 도면을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사 전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in this specification and claims should not be construed as being limited to the ordinary or dictionary meanings, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일 실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

도4는 본 발명의 일실시 예에 따른 리드 프레임이 포함된 칩 적층 패키지 소자의 구성도이다. 4 is a block diagram of a chip stack package device including a lead frame according to an embodiment of the present invention.

도시된 바와 같이, 리드 프레임이 포함된 칩 적층 패키지 소자는 몰딩부(110) 내부에 위치된 패들(120) 상면에 적층된 복수의 칩(130,132,133,134)이 와이어(142) 본딩을 통하여 연결 단자인 리드 프레임(140)에 전기적으로 접속되는 구조를 가진다. 복수의 칩(103,132,133,134)은 2 이상의 칩을 의미하며, 본 실시 예에서는 4개의 칩이 적층된 구조를 예시하여 설명한다.As shown, a chip stack package device including a lead frame includes a plurality of chips 130, 132, 133, and 134 stacked on an upper surface of the paddle 120 located inside the molding unit 110, through which wires 142 are bonded. It has a structure that is electrically connected to the frame 140. The plurality of chips 103, 132, 133, and 134 refer to two or more chips. In the present embodiment, a structure in which four chips are stacked will be described.

상기 몰딩부(110)는 패키지 소자의 외관을 구성하는 부분으로 적층된 복수의 칩(130,132,133,134)과 전기도선을 보호한다. The molding part 110 protects the plurality of chips 130, 132, 133, 134 and electrical conductors stacked as a part constituting the appearance of the package device.

몰딩부(110)는 낮은 탄성률을 갖고, 장착되는 칩(130,132,133,134)과 비슷한 열팽창 계수를 가지는 재료로 형성되는 것이 바람직하다. 예를 들면, 몰딩부(110)를 구성하는 재료는 플라스틱 에폭시 수지(EMC: epoxy molding compound) 또는 세 라믹(ceramic)일 수 있다. The molding part 110 may be formed of a material having a low elastic modulus and having a coefficient of thermal expansion similar to that of the chips 130, 132, 133, and 134 to be mounted. For example, the material constituting the molding part 110 may be a plastic epoxy resin (EMC) or ceramic.

바람직한 플라스틱 에폭시 수지는 열팽창률을 감소시키기 위하여 실리카(SiO2) 입자들의 크기와 혼합 배율을 변경시켜 가며 최적점을 찾는 방법 또는 탄성률을 감소시키기 위하여 실리콘 오일을 수지와 반응시켜 합성하는 방법으로 얻어지는 에폭시 수지일 수 있으며, 페닐-메틸-실리콘으로 된 실리콘 수지에 비정질 실리카(SiO2)를 넣어 만든 실리콘 플라스틱일 수 있다.Preferred plastic epoxy resins are epoxy obtained by changing the size and mixing ratio of silica (SiO 2 ) particles to reduce the thermal expansion rate and finding the optimum point or by synthesizing the silicone oil with the resin to reduce the elastic modulus. It may be a resin, and may be a silicone plastic made by adding amorphous silica (SiO 2 ) to a silicone resin of phenyl-methyl-silicon.

상기 패들(120)은 몰딩부(110) 내부에 위치되며 적층된 복수의 칩(130,132,133,134)을 지지한다. 패들(120) 상면에는 적층된 복수의 칩(130,132,133,134) 중 하단부에 위치된 칩(130)이 접착(bonding)될 수 있도록 접착제(adhesive)가 도포되는 것이 바람직하다. 여기에서 접착제(adhesive)는 솔더 합금(Au-Si) 또는 에폭시(epoxy) 수지일 수 있다.The paddle 120 is positioned inside the molding unit 110 and supports the plurality of chips 130, 132, 133, and 134 stacked therein. It is preferable that an adhesive is applied to the upper surface of the paddle 120 so that the chip 130 positioned at the lower end of the plurality of chips 130, 132, 133, and 134 may be bonded. The adhesive may be a solder alloy (Au-Si) or an epoxy resin.

상기 칩(130,132,133,134)은 몰딩부(110) 내부에 위치하는 패들(120)에 적층되는 구성요소로서, 활성면과 비활성면을 구비한다. 여기에서 칩은 IC 칩 또는 메모리 칩일 수 있다.The chips 130, 132, 133, and 134 are components stacked on the paddle 120 positioned inside the molding part 110 and have active and inactive surfaces. Here, the chip may be an IC chip or a memory chip.

복수의 칩(130,132,133,134)이 적층된 구조를 상세히 설명한다. 적층된 복수의 칩(130,132,133,134)은 패들(120)에 접착되는 하부 칩(130), 리드 프레임(140)에 와이어(142) 본딩되는 상부 칩(134) 및 하부 칩(130)과 상부 칩(134) 사이에 위치하는 중간 칩들(133,134)을 포함한다. 적층된 복수의 칩(130,132,133,134) 중 상부 칩(134)과 중간 칩(132,133)은 적층된 칩(130,132,133,134)들의 활성면을 전기 적으로 연결하기 위한 비아 홀(via hole)이 형성되는 것이 바람직하다.A structure in which a plurality of chips 130, 132, 133, and 134 are stacked will be described in detail. The stacked plurality of chips 130, 132, 133, and 134 may include a lower chip 130 bonded to the paddle 120, an upper chip 134 bonded to the lead frame 140, and a lower chip 130 and an upper chip 134. ), The intermediate chips 133 and 134 are positioned between them. The upper chip 134 and the intermediate chips 132 and 133 of the plurality of stacked chips 130, 132, 133 and 134 may preferably have via holes for electrically connecting the active surfaces of the stacked chips 130, 132, 133 and 134.

비아 홀은 레이저 드릴(laser drill), 기계적 드릴(mechanical drill) 등 드릴 방법과 플라즈마(plasma)를 이용한 건식 식각(dry etching), 반응이온식각(reactive ion etching) 등 식각방법을 통하여 형성될 수 있다.The via hole may be formed through a drill method such as a laser drill, a mechanical drill, and an etching method such as dry etching using plasma or reactive ion etching. .

적층된 복수의 칩(130,132,133,134) 중 하부 칩(130)은 비활성면이 접착제를 수단으로 패들(120)에 접착되며, 중간 칩들(132,133)과 상부 칩(134)은 비아 홀이 얼라인(align)된 상태로 하부 칩(130)의 활성면에 순차적으로 적층되고, 비아 홀에는 도전성 라인(136)이 형성된다.The lower chip 130 of the plurality of stacked chips 130, 132, 133, and 134 has an inactive surface bonded to the paddle 120 by means of an adhesive, and the middle chips 132, 133 and the upper chip 134 align via holes. Stacked in order on the active surface of the lower chip 130, and a conductive line 136 is formed in the via hole.

도전성 라인(136)은 적층된 복수의 칩(130,132,133,134)의 활성면을 전기적으로 연결하는 수단으로서, 적층된 복수의 칩(130,132,133,134)에 형성된 비아 홀 또는 비아 홀의 일부를 이용하여 형성될 수 있다.The conductive line 136 is a means for electrically connecting the active surfaces of the plurality of stacked chips 130, 132, 133, and 134. The conductive line 136 may be formed using a part of via holes or via holes formed in the stacked plurality of chips 130, 132, 133, and 134.

도전성 라인(136)은 금속 또는 전도성이 높은 비금속 재료로 형성되는 것이 바람직하다. 예를 들면, 도전성 라인은 텡스텐(W), 티타늄(Ti), 알루미늄(Al), 지르코늄(Zr), 크롬(Cr), 구리(Cu), 니켈(Ni), 금(Au), 은(Ag), 납(Pd) 또는 인듐 주석 화합물(ITO: Indium Tin Oxide) 재질의 금속을 포함하여 형성될 수 있으며, 바람직하게는 크롬, 구리, 니켈의 화합물일 수 있다.Conductive line 136 is preferably formed of a metal or a highly conductive nonmetallic material. For example, the conductive line may be tungsten (W), titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), copper (Cu), nickel (Ni), gold (Au), silver ( Ag, lead (Pd) or indium tin compound (ITO) may be formed to include a metal material, preferably a compound of chromium, copper, nickel.

한편 적층된 복수의 칩(130,132,133,134)들의 사이에는 도전성 탄성 중합체(conductive elastomer)(138)가 형성되는 것이 바람직하다. 도전성 탄성 중합체(138)는 적층된 복수의 칩(130,132,133,134)들 사이의 도전성 라인(136)을 감싸도록 형성될 수 있다. 도전성 탄성 중합체(138)는 적층된 복수의 칩 (130,132,133,134)들 사이에 일정한 갭(gap)을 생성하여 칩의 활성면이 적층된 칩의 비활성면에 밀착되는 것을 방지한다.Meanwhile, it is preferable that a conductive elastomer 138 is formed between the plurality of stacked chips 130, 132, 133, and 134. The conductive elastomer 138 may be formed to surround the conductive line 136 between the plurality of stacked chips 130, 132, 133, and 134. The conductive elastomer 138 creates a constant gap between the plurality of stacked chips 130, 132, 133, 134 to prevent the active surface of the chip from coming into close contact with the inactive surface of the stacked chip.

적층된 복수의 칩(130,132,133,134) 중 상부 칩(134)은 활성면에 전기적 연결 단자로 동작하는 패드(135)가 형성된다. 패드(135)는 알루미늄(Al)을 포함하는 재질로 형성될 수 있다. 예를 들면 패드(135)는 알루미늄(Al) 재질만으로 형성될 수 있으며, 알루미늄(Al)과 구리(Cu)의 합금 재질로 형성될 수 있다.The upper chip 134 of the plurality of stacked chips 130, 132, 133, and 134 has a pad 135 formed on the active surface as an electrical connection terminal. The pad 135 may be formed of a material including aluminum (Al). For example, the pad 135 may be formed of only aluminum (Al) material, and may be formed of an alloy material of aluminum (Al) and copper (Cu).

상부 칩(134)에 형성된 패드(136)는 와이어(142) 본딩을 통하여 리드 프레임(140)에 연결된다.The pad 136 formed on the upper chip 134 is connected to the lead frame 140 through wire 142 bonding.

이로서 몰딩부(110) 내부 적층된 복수의 칩(130,132,133,134)의 활성면은 도전성 라인(136)을 통하여 서로 전기적으로 연결되며, 상부 칩(134)의 패드(135)에 접속되는 리드 프레임(140)을 통하여 외부와 전기적 신호를 주고받을 수 있게 된다.As a result, the active surfaces of the plurality of chips 130, 132, 133, and 134 stacked inside the molding unit 110 are electrically connected to each other through the conductive line 136, and the lead frame 140 is connected to the pad 135 of the upper chip 134. Through it, it is possible to exchange electrical signals with the outside.

상기 리드 프레임(140)은 패키지의 외부 연결 단자로서, 적층된 복수의 칩(130,132,133,134) 중 상부 칩(134)에 형성된 패드(135)와 와이어(wire)(142)를 통하여 접속(bonding)된다. 여기에서 와이어(142)는 금선(gold wire)인 것이 바람직하다.The lead frame 140 is an external connection terminal of a package, and is connected to a pad 135 formed on an upper chip 134 of a plurality of chips 130, 132, 133, and 134 through a wire 142. The wire 142 is preferably a gold wire.

리드 프레임(140)은 PCB(printed circuit board) 기판 등에 실장될 때 쉽게 휘지 않는 강도를 가짐과 동시에 구부릴 때 부러지지 않는 유연성을 가지며, 몰딩부(110)와 같이 장착되는 칩과 비슷한 열팽창 계수를 가지는 재료로 형성되는 것이 바람직하다.The lead frame 140 has a strength that does not easily bend when mounted on a printed circuit board (PCB) substrate, and a flexibility that does not break when bent, and has a coefficient of thermal expansion similar to a chip mounted with the molding part 110. It is preferable to form.

바람직한 리드 프레임(140)의 재료로는 실리콘과 열팽창계수가 비슷한 Fe-Ni-Co 합금, Fe-Ni 합금 또는 열전도도가 우수한 구리 합금(CuFe2P) 등일 수 있다.Preferred materials of the lead frame 140 may be a Fe-Ni-Co alloy, a Fe-Ni alloy, or a copper alloy (CuFe 2 P) having excellent thermal conductivity.

이상과 같이, 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 이것에 의해 한정되지 않으며 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 본 발명의 기술 사상과 아래에 기재될 특허 청구범위의 균등 범위 내에서 다양한 수정 및 변형이 가능함은 물론이다.As mentioned above, although this invention was demonstrated by the limited embodiment and drawing, this invention is not limited by this, The person of ordinary skill in the art to which this invention belongs, Of course, various modifications and variations are possible within the scope of equivalent claims.

상술한 바와 같은 본 발명의 리드 프레임이 포함된 칩 적층 패키지 소자는, 에폭시 몰딩 컴파운드 내부에 복수의 칩을 적층하고, 비아 홀을 통하여 적층된 복수의 칩을 전기적으로 연결하여 상부 칩을 리드 프레임과 와이어 본딩함으로써, 멀티 미디어 및 정보 통신 산업의 급격한 발전에 따른 고집적 및 고성능 반도체 칩에 대한 요구에 부흥하여 제조공정이 간단하고 경제적인 패키지를 제공하는 효과가 있다. In the chip stack package device including the lead frame of the present invention as described above, a plurality of chips are stacked in an epoxy molding compound, and the plurality of chips stacked through the via holes are electrically connected to connect the upper chip to the lead frame. By wire bonding, there is an effect of providing a simple and economical package for the manufacturing process in response to the demand for high-integration and high-performance semiconductor chips due to the rapid development of the multimedia and telecommunication industry.

Claims (6)

몰딩부 내부에 위치된 패들에 활성면과 비활성면을 구비하는 복수의 칩이 적층되며 와이어 본딩을 통하여 리드 프레임에 접속되는 리드 프레임이 포함된 칩 적층 패키지 소자에 있어서,A chip stack package device including a lead frame having a plurality of chips having an active surface and an inactive surface stacked on a paddle positioned inside a molding unit and connected to a lead frame through wire bonding, 상기 몰딩부는 플라스틱 에폭시 수지 또는 세라믹으로 이루어지고, The molding part is made of a plastic epoxy resin or ceramic, 상기 패들과 제1칩의 비활성면은 솔더 합금(Au-Si) 또는 에폭시(epoxy) 수지로 접착되고, The paddle and the inactive surface of the first chip are bonded with a solder alloy (Au-Si) or epoxy resin, 상기 제1칩의 활성면 상에는 활성면에 형성된 패드가 상기 리드 프레임에 접속되는 제2칩을 포함하여 적어도 하나의 다른 칩이 도전성 탄성중합체를 개재하여 적층되며, On the active surface of the first chip, at least one other chip is stacked via the conductive elastomer, including a second chip having a pad formed on the active surface connected to the lead frame, 상기 다른 칩의 활성면과 제1칩의 활성면은 비아 홀 또는 비아 홀의 일부를 이용하여 도전성 라인으로 연결되는 리드 프레임이 포함된 칩 적층 패키지 소자.The chip stack package device of claim 1, wherein the active surface of the other chip and the active surface of the first chip are connected to conductive lines using a via hole or a part of the via hole. 제1항에 있어서, 플라스틱 에폭시 수지는 The method of claim 1 wherein the plastic epoxy resin 열팽창률을 감소시키기 위하여 실리카(SiO2) 입자들의 크기와 혼합 배율을 변경시키면서 최적점을 찾고 탄성률을 감소시키기 위하여 실리콘 오일을 수지와 반응시켜 합성하여 얻어지는 에폭시 수지 또는 페닐-메틸-실리콘으로 된 실리콘 수지에 비정질 실리카(SiO2)를 넣어 만든 실리콘 플라스틱인 것을 특징으로 하는 리드 프레임이 포함된 칩 적층 패키지 소자.Epoxy resin or phenyl-methyl-silicon silicone obtained by synthesizing silicone oil with resin to find the optimum point and reducing the elastic modulus while changing the size and mixing ratio of silica (SiO 2 ) particles to reduce the coefficient of thermal expansion Chip stack package device comprising a lead frame, characterized in that the silicon plastic made of amorphous silica (SiO 2 ) in the resin. 삭제delete 삭제delete 삭제delete 삭제delete
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JP2001135776A (en) * 1999-11-02 2001-05-18 Matsushita Electronics Industry Corp Semiconductor device and method of manufacture the same
JP2001250912A (en) * 2000-03-07 2001-09-14 Seiko Epson Corp Semiconductor device and its manufacturing method and electronic equipment

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JP2001135776A (en) * 1999-11-02 2001-05-18 Matsushita Electronics Industry Corp Semiconductor device and method of manufacture the same
JP2001250912A (en) * 2000-03-07 2001-09-14 Seiko Epson Corp Semiconductor device and its manufacturing method and electronic equipment

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