CN211908758U - High-speed positive and negative surge resistant analog switch circuit - Google Patents
High-speed positive and negative surge resistant analog switch circuit Download PDFInfo
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- CN211908758U CN211908758U CN202020401327.0U CN202020401327U CN211908758U CN 211908758 U CN211908758 U CN 211908758U CN 202020401327 U CN202020401327 U CN 202020401327U CN 211908758 U CN211908758 U CN 211908758U
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Abstract
The utility model provides a high-speed resistant positive negative surge's analog switch circuit, including first, two, three transistor circuit. The first transistor circuit comprises a first transistor and a first gate driving circuit, and when the gate of the first transistor is at a first voltage level, the first transistor is started to reduce the voltage level peak value of the positive surge signal and the negative surge signal in a first stage mode. The second transistor circuit comprises a second transistor and a second gate driving circuit, and when the gate of the second transistor is at a second voltage level, the second transistor is started to reduce the voltage level peak value of the positive surge signal and the negative surge signal in a second-stage mode. The third transistor circuit includes a third transistor and a third gate driving circuit, when the gate of the third transistor is at a third voltage level, the third transistor is activated to reduce the voltage level peak of the positive and negative surge signals to be transmitted to the low voltage output terminal in a third pole manner. The utility model provides an analog switch circuit effectively resists the circuit and produces the positive and negative surge of high pressure when last electricity.
Description
Technical Field
The utility model relates to an electronic circuit field particularly, relates to a high-speed resistant positive negative surge's analog switch circuit.
Background
Generally, many single pole double throw switches are required to be able to transmit both positive and negative voltages, such as audio signals where both positive and negative voltages are present. In practical applications, an alternative switch between audio and USB is often encountered. This requires that one switch be on while the other must be off, which is generally no problem for positive voltages, but if negative, it will be forward-conducting through the other substrate-drain parasitic diode if no special treatment is done.
The traditional 5V NMOS single tube can transmit positive voltage signals and negative voltage signals at the same time by a substrate undercut (undercut) mode, but the VDS of a 5V device can only carry about 12V at the highest. High voltage surges cannot be resisted. In the conventional design, a 5V NMOS + HV LDMOS series connection mode is also often used to carry high voltage and high voltage surge, for example, a 30V LDMOS is adopted, i.e., about +40V surge can be endured. However, since the substrate and the source of the LDMOS are fixedly connected together, Body cannot realize well cutting, so that a negative voltage signal is transmitted to the USB switch through the substrate-drain parasitic diode through the audio and USB common terminals, resulting in that the USB cannot be normally turned off.
SUMMERY OF THE UTILITY MODEL
In view of the above problem, the utility model provides a high-speed resistant positive negative surge's analog switch circuit can effectively solve the problem that the circuit can't resist the high-pressure surge when going up the electricity.
In order to achieve the above object, the utility model adopts the following technical scheme:
in a first aspect, the utility model provides a high-speed resistant positive negative surge's analog switch circuit, analog switch circuit is used for accepting voltage signal by high-pressure input end, voltage signal includes positive voltage signal and/or negative voltage signal, and wherein, positive voltage signal includes positive surge signal, and negative voltage signal includes negative surge signal, analog switch circuit includes:
a first transistor circuit electrically connected to the high voltage input terminal, the first transistor circuit including a first transistor and a first gate driving circuit, a drain of the first transistor being electrically connected to the high voltage input terminal, a gate of the first transistor being electrically connected to one end of the first gate driving circuit, the first gate driving circuit activating the first transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a first stage when the gate of the first transistor is at a first voltage level;
a second transistor circuit including a second transistor and a second gate driving circuit, wherein a drain of the second transistor is electrically connected to a source of the first transistor circuit, a gate of the second transistor is electrically connected to one end of the second gate driving circuit, and when the gate of the second transistor is at a second voltage level, the second gate driving circuit starts the second transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a second stage;
and a third transistor circuit including a third transistor and a third gate driving circuit, wherein a drain of the third transistor is electrically connected to a source of the second transistor circuit, a gate of the third transistor is electrically connected to one end of the third gate driving circuit, and when the gate of the third transistor is at a third voltage level, the third gate driving circuit activates the third transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a third-pole manner, and then transmits the reduced voltage level peak of the positive surge signal or the reduced voltage level peak of the negative surge signal in the third-pole manner to a low-voltage output terminal after reaching a low threshold voltage level.
In an alternative embodiment, the absolute value of the first voltage level is greater than the absolute value of the second voltage level, and the absolute value of the second voltage level is greater than the absolute value of the third voltage level.
As an optional implementation, the first transistor circuit further includes:
a first switch, one end of which is electrically connected to the source of the first transistor, the other end of which is electrically connected to the gate of the first transistor and one end of the first gate driving circuit, wherein when the gate of the first transistor is at the first voltage level, the first switch is closed to turn off the first transistor;
a first substrate selection circuit, an input terminal of the first substrate selection circuit being electrically connected to the source and the drain of the first transistor, an output terminal of the first substrate selection circuit being electrically connected to the substrate of the first transistor, the first substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the first transistor are at a minimum voltage difference value;
a first high-voltage selection circuit, one end of which is electrically connected with the drain electrode of the first transistor, the high-voltage input end and the input end of the first substrate selection circuit;
one end of the first Zener voltage stabilizing diode is electrically connected with the other end of the first high-selection circuit;
one end of the first resistor is electrically connected with the other end of the first Zener voltage stabilizing diode;
one end of the first diode is electrically connected with the other end of the first resistor;
a first low selection circuit, one end of which is electrically connected with the other end of the first diode, and the other end of which is electrically connected with the input end of the first substrate selection circuit and the source electrode of the first transistor;
the first Zener diode, the first resistor and the first diode are used for controlling a voltage difference value between a source electrode and a drain electrode of the first transistor through the first high-selection circuit and the first low-selection circuit.
As an optional implementation, the first gate driving circuit includes:
a second resistor, one end of which is electrically connected with the gate of the first transistor;
one end of the second Zener voltage stabilizing diode is electrically connected with the other end of the second resistor;
one end of the second diode is electrically connected with the other end of the second Zener voltage stabilizing diode;
one end of the third diode is electrically connected with the other end of the second diode;
one end of the fourth diode is electrically connected with the other end of the third diode;
one end of the fifth diode is electrically connected with the other end of the fourth diode;
the drain electrode of the first gate electrode driving transistor is electrically connected with the other end of the fifth diode;
a first capacitor, one end of which is electrically connected to the other end of the second resistor and one end of the second zener diode, and the other end of which is electrically connected to the gate of the first gate driving transistor, wherein when the voltage signal includes the positive surge signal or the negative surge signal, the gate of the first transistor increases the voltage level of the gate of the first gate driving transistor to a start state through the second resistor and the first capacitor;
a third resistor, one end of which is electrically connected with the other end of the first capacitor and the gate of the first gate drive transistor, and the other end of which is grounded;
a third Zener diode, one end of which is electrically connected with the gate of the first gate driving transistor, the other end of the first capacitor and one end of the third resistor;
and the drain and the gate of the second gate driving transistor are electrically connected with the other end of the third Zener voltage stabilizing diode, and the source of the second gate driving transistor is grounded, wherein the third Zener voltage stabilizing diode and the second gate driving transistor are used for stabilizing the voltage difference value of the gate and the source of the first gate driving transistor.
As an optional implementation, the second transistor circuit further includes:
a second switch, one end of which is electrically connected to the source of the second transistor and the other end of which is electrically connected to the gate of the second transistor and one end of the second gate driving circuit, wherein when the gate of the second transistor is at the second voltage level, the second switch is closed to disconnect the second transistor;
a second substrate selection circuit, an input terminal of the second substrate selection circuit being electrically connected to the source and the drain of the second transistor, an output terminal of the second substrate selection circuit being electrically connected to the substrate of the second transistor, the second substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the second transistor are at a minimum voltage difference value;
a second high-selection circuit, one end of which is electrically connected with the drain electrode of the second transistor, the source electrode of the first transistor and the input end of the second substrate selection circuit;
one end of the fourth Zener voltage stabilizing diode is electrically connected with the other end of the second high-voltage selection circuit;
one end of the fourth resistor is electrically connected with the other end of the fourth Zener voltage stabilizing diode;
one end of the sixth diode is electrically connected with the other end of the fourth resistor;
one end of the second low selection circuit is electrically connected with the other end of the sixth diode, and the other end of the second low selection circuit is electrically connected with the input end of the second substrate selection circuit and the source electrode of the second transistor;
the fourth zener diode, the fourth resistor and the sixth diode are used for controlling the voltage difference value between the source and the drain of the second transistor through the second high-selection circuit and the second low-selection circuit.
As an optional implementation, the second gate driving circuit includes:
a fifth resistor, one end of which is electrically connected with the gate of the second transistor;
one end of the fifth Zener voltage stabilizing diode is electrically connected with the other end of the fifth resistor;
one end of the seventh diode is electrically connected with the other end of the fifth Zener voltage stabilizing diode;
one end of the eighth diode is electrically connected with the other end of the seventh diode;
one end of the ninth diode is electrically connected with the other end of the eighth diode;
one end of the twelfth diode is electrically connected with the other end of the ninth diode;
a third gate driving transistor, wherein the drain electrode of the third gate driving transistor is electrically connected with the other end of the twelfth diode;
a second capacitor, one end of which is electrically connected to the other end of the fifth resistor and one end of the fifth zener diode, and the other end of which is electrically connected to the gate of the third gate driving transistor, wherein when the voltage signal includes the positive surge signal or the negative surge signal, the gate of the second transistor increases the voltage level of the gate of the third gate driving transistor to a start state through the fifth resistor and the second capacitor;
one end of the sixth resistor is electrically connected with the other end of the second capacitor and the gate of the third gate drive transistor, and the other end of the sixth resistor is grounded;
a sixth zener diode having one end electrically connected to the gate of the third gate driving transistor, the other end of the second capacitor, and one end of the sixth resistor;
and the drain and the gate of the fourth gate driving transistor are electrically connected with the other end of the sixth Zener diode, and the source of the fourth gate driving transistor is grounded, wherein the sixth Zener diode and the fourth gate driving transistor are used for stabilizing the voltage difference value between the gate and the source of the third gate driving transistor.
As an optional implementation, the third transistor circuit further includes:
a third switch, one end of which is electrically connected to the source of the third transistor and the other end of which is electrically connected to the gate of the third transistor and one end of the third gate driving circuit, wherein when the gate of the third transistor is at the third voltage level, the third switch is turned on to turn off the third transistor;
a third substrate selection circuit, an input terminal of the third substrate selection circuit being electrically connected to the source and the drain of the third transistor, an output terminal of the third substrate selection circuit being electrically connected to the substrate of the third transistor, the third substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the third transistor are at a minimum voltage difference value;
a third high-selection circuit, one end of which is electrically connected with the drain of the third transistor, the source of the second transistor and the input end of the third substrate selection circuit;
one end of the seventh Zener voltage stabilizing diode is electrically connected with the other end of the third high-selection circuit;
one end of the seventh resistor is electrically connected with the other end of the seventh Zener voltage stabilizing diode;
one end of the eleventh diode is electrically connected with the other end of the seventh resistor;
a third low selection circuit, one end of which is electrically connected to the other end of the eleventh diode, and the other end of which is electrically connected to the input end of the third substrate selection circuit and the source of the third transistor;
wherein the seventh zener diode, the seventh resistor, and the eleventh diode are configured to control a voltage difference value between the source and the drain of the third transistor through the third high-selection circuit and the third low-selection circuit.
As an optional implementation, the third gate driving circuit includes:
an eighth resistor, one end of which is electrically connected to the source of the second transistor and the drain of the third transistor;
one end of the eighth Zener voltage stabilizing diode is electrically connected with the other end of the eighth resistor;
a ninth zener diode, one end of which is electrically connected to the other end of the eighth zener diode;
one end of the ninth resistor is electrically connected with the other end of the ninth Zener voltage stabilizing diode, and the other end of the ninth resistor is grounded;
a fifth gate driving transistor, a gate of which is electrically connected to the other end of the ninth zener diode and one end of the ninth resistor, and a source of which is grounded, wherein when the voltage signal includes the positive surge signal or the negative surge signal, a drain of the third transistor raises a voltage level of the gate of the fifth gate driving transistor to a start state through the eighth resistor, the eighth zener diode, the ninth zener diode and the ninth resistor;
a tenth zener diode having one end electrically connected to the other end of the ninth zener diode, one end of the ninth resistor, and the gate of the fifth gate driving transistor;
an eleventh zener diode having one end electrically connected to the other end of the tenth zener diode and the other end grounded, wherein the tenth zener diode and the eleventh zener diode are used to stabilize a voltage difference between the gate and the source of the fifth gate driving transistor;
a tenth resistor, one end of which is electrically connected to the gate of the third transistor;
a twelfth zener diode, one end of which is electrically connected to the other end of the tenth resistor;
and a thirteenth zener diode having one end electrically connected to the other end of the twelfth zener diode and the other end electrically connected to the drain of the fifth gate driving transistor, wherein after the fifth gate driving transistor is turned on, the tenth resistor, the twelfth zener diode, the thirteenth zener diode and the fifth gate driving transistor form a path to reduce the peak voltage level of the positive surge signal or the peak voltage level of the negative surge signal to a low threshold voltage level and transmit the reduced peak voltage level to the low voltage output terminal.
In a second aspect, the present invention provides a control method, applied to an analog switch circuit with high speed resistance to positive and negative surges, the analog switch circuit includes a first transistor circuit, a second transistor circuit and a third transistor circuit, the first transistor circuit is electrically connected to the high voltage input terminal, the first transistor circuit includes a first transistor and a first gate driving circuit, the drain of the first transistor is electrically connected to the high voltage input terminal, the gate of the first transistor is electrically connected to one end of the first gate driving circuit, the second transistor circuit includes a second transistor and a second gate driving circuit, the drain of the second transistor is electrically connected to the source of the first transistor circuit, the gate of the second transistor is electrically connected to one end of the second gate driving circuit, the third transistor circuit includes a third transistor and a third gate driving circuit, the drain of the third transistor is electrically connected to the source of the second transistor circuit, the gate of the third transistor is electrically connected to one end of the third gate driving circuit, the analog switch circuit is configured to receive a voltage signal from the high voltage input terminal, the voltage signal includes a positive voltage signal and/or a negative voltage signal, the positive voltage signal includes a positive surge signal, and the negative voltage signal includes a negative surge signal, and the control method includes:
when the gate of the first transistor is at a first voltage level, the first gate driving circuit starts the first transistor to reduce the voltage level peak value of the positive surge signal or the voltage level peak value of the negative surge signal in a first stage manner;
when the gate of the second transistor is at a second voltage level, the second gate driving circuit starts the second transistor to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in a second stage manner;
when the gate of the third transistor is at a third voltage level, the third gate driving circuit activates the third transistor to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in a third-pole manner, and then transmits the reduced voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in the third-pole manner to the low-voltage output terminal after reaching a low threshold voltage level.
In an alternative embodiment, the absolute value of the first voltage level is greater than the absolute value of the second voltage level, and the absolute value of the second voltage level is greater than the absolute value of the third voltage level.
According to the utility model provides a high-speed resistant positive negative surge's analog switch circuit, including first, two, three transistor circuit. The first transistor circuit comprises a first transistor and a first gate driving circuit, and when the gate of the first transistor is at a first voltage level, the first transistor is started to reduce the voltage level peak value of the positive surge signal and the negative surge signal in a first stage mode. The second transistor circuit comprises a second transistor and a second gate driving circuit, and when the gate of the second transistor is at a second voltage level, the second transistor is started to reduce the voltage level peak value of the positive surge signal and the negative surge signal in a second-stage mode. The third transistor circuit includes a third transistor and a third gate driving circuit, when the gate of the third transistor is at a third voltage level, the third transistor is activated to reduce the voltage level peak of the positive and negative surge signals to be transmitted to the low voltage output terminal in a third pole manner. The circuit can be effectively resisted to generate high-voltage positive and negative surges when being electrified. The utility model provides a control circuit, through the pressure difference of striding of the clamping function control transistor by diode or zener diode, when positive and negative surge, start or close gate drive circuit through on-off control and reduce the surge peak value of flowing through the transistor with gradual mode, increase circuit security. Additionally, the utility model provides a quick surge protection circuit step by step (be regarded as analog switch circuit), and can endure quick positive and negative surge. The Body of the transistor can transmit positive voltage and negative voltage in a trap cutting mode, and the analog switch is very suitable for an audio switch, particularly applied to an interface, so that voltage-resistant damage caused by surge and the like in practical application is greatly reduced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention.
Fig. 1 is a schematic block diagram of a high-speed positive-negative surge-resistant analog switch circuit provided in embodiment 1 of the present invention;
fig. 2 is a schematic circuit diagram of a high-speed positive-negative surge-resistant analog switch circuit provided in embodiment 2 of the present invention;
fig. 2a is a schematic circuit diagram of a first gate driving circuit provided in embodiment 2 of the present invention;
fig. 2b is a schematic circuit diagram of a second gate driving circuit provided in embodiment 2 of the present invention;
fig. 2c is a schematic circuit diagram of a third gate driving circuit provided in embodiment 2 of the present invention;
fig. 3 is a flowchart of a control method provided in embodiment 3 of the present invention.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout.
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic block diagram of a high-speed positive-negative surge-resistant analog switch circuit (hereinafter referred to as "analog switch circuit") provided in embodiment 1 of the present invention. The analog switch circuit 1 includes a first transistor circuit 300, a second transistor circuit 200, and a third transistor circuit 100. Further, the first transistor circuit 300 includes a first transistor 301 and a first gate driving circuit 302, the second transistor circuit 200 includes a second transistor 201 and a second gate driving circuit 202, and the third transistor circuit 100 includes a third transistor 101 and a third gate driving circuit 102. The analog switch circuit 1 is used for receiving a voltage signal from a high voltage input terminal HV. The voltage signal includes a positive voltage signal and/or a negative voltage signal. When the voltage signal is a sine wave or a cosine wave, the voltage signal includes a positive voltage signal and a negative voltage signal. When the voltage signal is a triangular wave, the voltage signal includes a positive voltage signal or a negative voltage signal. The positive voltage signal includes a positive surge signal and the negative voltage signal includes a negative surge signal. In other words, when the circuit is powered up, the positive voltage signal may include a positive surge signal, and the negative voltage signal may include a negative surge signal.
In one embodiment, the first transistor circuit 300 is electrically connected to the high voltage input terminal HV. Further, the drain of the first transistor 301 is electrically connected to the high voltage input terminal HV, and the gate NG3 of the first transistor 301 is electrically connected to one end of the first gate driving circuit 302. The drain of the second transistor 201 is electrically connected to the source of the first transistor 301, and the gate NG2 of the second transistor 201 is electrically connected to one end of the second gate driving circuit 202. The drain of the third transistor 101 is electrically connected to the source of the second transistor circuit 201, and the gate NG1 of the third transistor 101 is electrically connected to one end of the third gate driving circuit 102. In addition, the analog switch circuit 1 may further include a Central Processing Unit (CPU) (not shown), where the CPU includes a plurality of pins, and each pin is used for receiving and transmitting signals, for example, the CPU may be used to control the switch circuit to automatically reduce the peak value of the surge voltage step by step according to the circuit structure, so as to avoid circuit damage.
In one embodiment, when the gate NG3 of the first transistor 301 is at the first voltage level, the first gate driving circuit 302 enables the first transistor 301 to reduce the peak voltage level of the positive surge signal or the peak voltage level of the negative surge signal in a first stage. When the gate NG2 of the second transistor 201 is at the second voltage level, the second gate driving circuit 202 enables the second transistor 201 to reduce the peak voltage level of the positive surge signal or the peak voltage level of the negative surge signal in a second stage. When the gate NG1 of the third transistor 101 is at the third voltage level, the third gate driving circuit 102 activates the third transistor 101 to decrease the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in the third-pole manner, and then transmits the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in the third-pole manner to the low-voltage output terminal LV after the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal is decreased to the low-threshold voltage level.
For example, the first transistor 301, the second transistor 201, and the third transistor circuit 101 in the first transistor circuit 300, the second transistor circuit 200, and the third transistor circuit 100 according to the present invention may be implemented by multi-stage 5V NMOS series connection. The principle explanation section will be described with a three-pole NMOS cascade as an example. The Body of each NMOS stage can be independently cut off, and can be used in an audio and USB alternative single-pole double-throw switch to transmit positive and negative voltages at the same time, so that the other channel is completely disconnected under the condition that one channel is opened. And the utility model discloses a protection circuit of quick positive and negative surge of reply guarantees that IC is not damaged in the application of interface plug. For a rapid surge signal, the grid voltage of the three-pole NMOS is rapidly pulled down step by step through the rapid surge protection circuit, the grid voltage is pulled down, the voltage of the signal is also reduced after the signal passes through the switch, and finally, the residual voltage seen by the low-voltage end is less than 5.6V, so that other devices connected with the low-voltage end in application cannot be damaged. In addition, the OFF withstand voltage of the 5V NMOS is higher and can reach about 12V, and the withstand voltage of about 36V can be achieved by connecting three-pole NMOS in series. For example, the absolute value of the first voltage level is greater than the absolute value of the second voltage level, and the absolute value of the second voltage level is greater than the absolute value of the third voltage level. From the theory of electricity, the circuit structure connected in series can reduce the voltage level peak value of the positive surge signal or the voltage level peak value of the negative surge signal in a step-by-step mode, and effectively avoids the damage to electronic components caused by the reduction of the overhigh voltage difference of each transistor circuit. The utility model discloses reduce circuit cost simultaneously and realize the optimization design to system efficiency, packaging body miniaturization and reduction surge output.
Example 2
Please refer to fig. 1, fig. 2a, fig. 2b and fig. 2 c. Fig. 2 is a schematic circuit diagram of a high-speed positive-negative surge-resistant analog switch circuit provided in embodiment 2 of the present invention. Fig. 2a is a schematic circuit diagram of a first gate driving circuit provided in embodiment 2 of the present invention. Fig. 2b is a schematic circuit diagram of a second gate driving circuit provided in embodiment 2 of the present invention. Fig. 2c is a schematic circuit diagram of a third gate driving circuit provided in embodiment 2 of the present invention. The first transistor circuit 300 includes a first switch 303, a first substrate selection circuit 304, a first high-selection circuit 305, a first zener diode 306, a first resistor 307, a first diode 308, and first low- selection circuits 309, 310. The first gate driving circuit 302 includes a second resistor 324, a second zener diode 314, a second diode 315, a third diode 316, a fourth diode 317, a fifth diode 318, a first gate driving transistor 323, a first capacitor 322, a third resistor 321, a third zener diode 319, and a second gate driving transistor 320.
In one embodiment, one end of the first switch 303 is electrically connected to the source of the first transistor 301. The other end of the first switch 303 is electrically connected to the gate NG3 of the first transistor 301 and one end of the first gate driving circuit 302. When the gate NG3 of the first transistor 301 is at the first voltage level, the first switch 303 is turned on to turn off the first transistor 301. Further, the first switch 303 is closed so that the gate and the source of the first transistor 301 are at the same potential point and are in the cut-off region. The input terminal of the first substrate selection circuit 304 is electrically connected to the source and the drain of the first transistor 301, the output terminal of the first substrate selection circuit 304 is electrically connected to the substrate of the first transistor 301, and the first substrate selection circuit 304 is configured to select a substrate voltage level when the source and the drain of the first transistor 301 are at a minimum voltage difference value. In other words, the first substrate selection circuit 304 is used to provide potential selection to the substrate of the first transistor 301, selecting the minimum of the source and drain voltages of the first transistor 301 as the substrate potential to ensure that the parasitic Body diode of the first transistor 301 is reverse biased.
In one embodiment, one end of the first high voltage selection circuit 305 is electrically connected to the drain of the first transistor 301, the high voltage input terminal HV and the input terminal of the first substrate selection circuit 304. One end of the first zener diode 306 is electrically connected to the other end of the first high-selection circuit 305. One end of the first resistor 307 is electrically connected to the other end of the first zener diode 306. One end of the first diode 308 is electrically connected to the other end of the first resistor 307. One end of the first low- selection circuits 309 and 310 is electrically connected to the other end of the first diode 308, and the other ends of the first low- selection circuits 309 and 310 are electrically connected to the input end of the first substrate selection circuit 304 and the source of the first transistor 301. The first zener diode 306, the first resistor 307 and the first diode 308 are used to control the voltage difference between the source and the drain of the first transistor 301 through the first high-selection circuit 305 and the first low- selection circuits 309 and 310, so as to effectively control the voltage drop of the positive and negative surges step by step of the first transistor circuit 300, thereby avoiding the loss of electronic components.
In one embodiment, one end of the second resistor 324 is electrically connected to the gate NG3 of the first transistor 301. One end of the second zener diode 314 is electrically connected to the other end of the second resistor 324. One end of the second diode 315 is electrically connected to the other end of the second zener diode 314. One end of the third diode 316 is electrically connected to the other end of the second diode 315. One end of the fourth diode 317 is electrically connected to the other end of the third diode 316. One end of the fifth diode 318 is electrically connected to the other end of the fourth diode 317. The drain of the first gate driving transistor 323 is electrically connected to the other end of the fifth diode 318. One end of the first capacitor 322 is electrically connected to the other end of the second resistor 324 and one end of the second zener diode 314, and the other end of the first capacitor 322 is electrically connected to the gate NG3_ P of the first gate driving transistor 323. When the voltage signal includes a positive surge signal or a negative surge signal, the gate NG3 of the first transistor 301 increases the voltage level of the gate NG3_ P of the first gate driving transistor 323 to the activated state through the second resistor 324 and the first capacitor 323.
In one embodiment, one end of the third resistor 321 is electrically connected to the other end of the first capacitor 322 and the gate of the first gate driving transistor 323, and the other end of the third resistor 321 is grounded. One end of the third zener diode 319 is electrically connected to the gate of the first gate driving transistor 323, the other end of the first capacitor 322 and one end of the third resistor 321. The drain and gate of the second gate driving transistor 320 are electrically connected to the other end of the third zener diode 319. The source of the second gate driving transistor 320 is grounded. The third zener diode 319 and the second gate driving transistor 320 are used to stabilize the voltage difference between the gate and the source of the first gate driving transistor 323. In other words, the second zener diode 314 and the second to fifth diodes 315 to 318 are connected in series and electrically connected to the drain of the first gate driving transistor 323, and the gate NG3_ P of the first gate driving transistor 323 is pulled down to the ground through the third resistor 321 and pulled up to the cathode of the second zener diode 314 (regarded as one end of the second zener diode 314) through the first capacitor 322. The third Zener diode 319 and the second gate driving transistor 320 are connected in series to pull the gate NG3_ P of the first gate driving transistor 323 to ground, protecting the first gate driving transistor 323 as V of NMOSGS. For example, the zener diode has a regulated voltage of about 5.8V. When a fast positive surge occurs at the high voltage input terminal HV, the gate-drain coupling capacitor C of the first transistor 301 is passedGDThe voltage level of the gate NG3 of the first transistor 301 is quickly raised. The gate of the first transistor 301The voltage level change of the NG3 is coupled to the gate NG3_ P of the first gate driving transistor 323 through the second resistor 324 and the first capacitor 322 to raise the voltage of the gate NG3_ P of the first gate driving transistor 323, thereby turning on the first gate driving transistor 323, and the gate NG3 of the first transistor 301 is pulled down to a zener diode voltage + four diode forward voltage drops + the second resistor 324 (I * R). The falling voltage of the first gate driving circuit 302 is about 5.8V +4 * 0.7V + I*R＝10V, assuming that I*R＝1V. Because the utility model provides an analog switch circuit 1 is to surge voltage reducing step by step, so in practical application, the capacitance value of first electric capacity 322 (regard as coupling capacitance) will be less than the capacitance value of second electric capacity 222, can remove first electric capacity 322 even. In other embodiments, the capacitance of the capacitor is increased step by step in a multi-stage NMOS switch series connection structure, and the specific value is determined by simulation according to the actual application requirement.
In one embodiment, the second transistor circuit 200 includes a second switch 203, a second substrate selection circuit 204, a second high selection circuit 205, a fourth zener diode 206, a fourth resistor 207, a sixth diode 208, and second low selection circuits 209 and 210. One end of the second switch 203 is electrically connected to the source of the second transistor 201. The other end of the second switch 203 is electrically connected to the gate NG2 of the second transistor 201 and one end of the second gate driving circuit 202. When the gate NG2 of the second transistor 201 is at the second voltage level, the second switch 203 is turned on to turn off the second transistor 201. The input terminal of the second substrate selection circuit 204 is electrically connected to the source and the drain of the second transistor 201. The output terminal of the second substrate selection circuit 204 is electrically connected to the substrate of the second transistor 201, and the second substrate selection circuit 204 is used for selecting the substrate voltage level when the source and drain voltages of the second transistor 201 are at the minimum voltage difference value. One end of the second high-selection circuit 205 is electrically connected to the drain of the second transistor 201, the source of the first transistor 301, and the input of the second substrate selection circuit 204. One end of the fourth zener diode 206 is electrically connected to the other end of the second high-voltage selection circuit 205. One end of the fourth resistor 207 is electrically connected to the other end of the fourth zener diode 206. One end of the sixth diode 208 is electrically connected to the other end of the fourth resistor 207. One end of the second low- selection circuit 209 and 210 is electrically connected to the other end of the sixth diode 208, and the other end of the second low- selection circuit 209 and 210 is electrically connected to the input end of the second substrate selection circuit 204 and the source of the second transistor 201. The fourth zener diode 206, the fourth resistor 207 and the sixth diode 208 are used to control the voltage difference between the source and the drain of the second transistor 201 through the second high-selection circuit 205 and the second low- selection circuits 209 and 210.
In one embodiment, the second gate driving circuit 202 includes a fifth resistor 224, a fifth zener diode 214, a seventh diode 215, an eighth diode 216, a ninth diode 217, a twelfth diode 218, a third gate driving transistor 223, a second capacitor 222, a sixth resistor 221, a sixth zener diode 219, and a fourth gate driving transistor 220. One end of the fifth resistor 224 is electrically connected to the gate NG2 of the second transistor 201. One end of the fifth zener diode 214 is electrically connected to the other end of the fifth resistor 224. One end of the seventh diode 215 is electrically connected to the other end of the fifth zener diode 214. One end of the eighth diode 216 is electrically connected to the other end of the seventh diode 215. One end of the ninth diode 217 is electrically connected to the other end of the eighth diode 216. One end of the twelfth diode 218 is electrically connected to the other end of the ninth diode 217. The drain of the third gate driving transistor 223 is electrically connected to the other end of the twelfth diode 218. One end of the second capacitor 222 is electrically connected to the other end of the fifth resistor 224 and one end of the fifth zener diode 214. The other end of the second capacitor 222 is electrically connected to the gate of the third gate driving transistor 223. When the voltage signal includes a positive surge signal or a negative surge signal, the gate NG2 of the second transistor 210 raises the voltage level of the gate NG2_ P of the third gate driving transistor 223 to the activated state through the fifth resistor 224 and the second capacitor 222. One end of the sixth resistor 221 is electrically connected to the other end of the second capacitor 222 and the gate NG2_ P of the third gate driving transistor 223, and the other end of the sixth resistor 221 is grounded. One end of the sixth zener diode 219 is electrically connected to the gate NG2_ P of the third gate driving transistor 223, the other end of the second capacitor 222 and one end of the sixth resistor 221. The drain and gate of the fourth gate driving transistor 220 are electrically connected to the other end of the sixth zener diode 219. The source of the fourth gate driving transistor 220 is grounded. The sixth zener diode 219 and the fourth gate driving transistor 220 are used to stabilize the voltage difference between the gate and the source of the third gate driving transistor 223, thereby increasing the circuit stability.
In one embodiment, the third transistor circuit 100 includes a third switch 103, a third substrate selection circuit 104, a third high-selection circuit 105, a seventh zener diode 106, a seventh resistor 107, an eleventh diode 108, and third low- selection circuits 109 and 110. One end of the third switch 103 is electrically connected to the source of the third transistor 101. The other end of the third switch 103 is electrically connected to the gate NG1 of the third transistor 101 and one end of the third gate driving circuit 102. When the gate NG1 of the third transistor 101 is at the third voltage level, the third switch 103 is closed to turn off the third transistor 101. An input terminal of the third substrate selection circuit 104 is electrically connected to the source and the drain of the third transistor 101. The output terminal of the third substrate selection circuit 104 is electrically connected to the substrate of the third transistor 101. The third substrate selection circuit 104 is used to select the substrate voltage level when the source and drain voltages of the third transistor 101 are at the minimum voltage difference value.
One end of the third high-selection circuit 105 is electrically connected to the drain of the third transistor 101, the source of the second transistor 201, and the input end of the third substrate selection circuit 104. One end of the seventh zener diode 106 is electrically connected to the other end of the third high-voltage selection circuit 105. One end of the seventh resistor 107 is electrically connected to the other end of the seventh zener diode 106. One end of the eleventh diode 108 is electrically connected to the other end of the seventh resistor 107. One end of the third low- selection circuit 109, 110 is electrically connected to the other end of the eleventh diode 108. The other end of the third low select circuit 109, 110 is electrically connected to the input terminal of the third substrate select circuit 104 and the source and drain of the third transistor 101. The output terminal of the third substrate selection circuit 104 is electrically connected to the substrate of the third transistor 101, and the third substrate selection circuit 104 is used for selecting the substrate voltage level when the source and drain voltages of the third transistor 101 are at the minimum voltage difference value. The seventh zener diode 106, the seventh resistor 107 and the eleventh diode 108 are used for controlling the voltage difference value between the source and the drain of the third transistor 101 through the third high-selection circuit 105 and the third low- selection circuits 109 and 110.
In one embodiment, the third gate driving circuit 102 includes an eighth resistor 114, an eighth zener diode 115, a ninth zener diode 116, a ninth resistor 121, a fifth gate driving transistor 123, a tenth zener diode 119, an eleventh zener diode 120, a tenth resistor 111, a twelfth zener diode 112, and a thirteenth zener diode 113. One end of the eighth resistor 114 is electrically connected to the source of the second transistor 201 and the drain of the third transistor 101. One end of the eighth zener diode 115 is electrically connected to the other end of the eighth resistor 114. One end of the ninth zener diode 116 is electrically connected to the other end of the eighth zener diode 115. One end of the ninth resistor 121 is electrically connected to the other end of the ninth zener diode 116, and the other end of the ninth resistor 121 is grounded. The gate NG1_ P of the fifth gate driving transistor 123 is electrically connected to the other end of the ninth zener diode 116 and one end of the ninth resistor 121. The source of the fifth gate driving transistor 123 is grounded.
When the voltage signal includes a positive surge signal or a negative surge signal, the drain of the third transistor 101 increases the voltage level of the gate NG1_ P of the fifth gate driving transistor 123 to the start state through the eighth resistor 114, the eighth zener diode 115, the ninth zener diode 116 and the ninth resistor 121. One end of the tenth zener diode 119 is electrically connected to the other end of the ninth zener diode 116, one end of the ninth resistor 121, and the gate NG1_ P of the fifth gate driving transistor 123. One end of the eleventh zener diode 120 is electrically connected to the other end of the tenth zener diode 119. The other end of the eleventh zener diode 120 is grounded.
The tenth zener diode 119 and the eleventh zener diode 120 are used to stabilize the voltage difference between the gate and the source of the fifth gate driving transistor 123. One end of the tenth resistor 111 is electrically connected to the gate of the third transistor 101. One end of the twelfth zener diode 112 is electrically connected to the other end of the tenth resistor 111. One end of the thirteenth zener diode 113 is electrically connected to the other end of the twelfth zener diode 112. The other end of the thirteenth zener diode 113 is electrically connected to the drain of the fifth gate driving transistor 123.
After the fifth gate driving transistor 123 is turned on, the tenth resistor 111, the twelfth zener diode 112, the thirteenth zener diode 113 and the fifth gate driving transistor 123 form a path to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal to a low threshold voltage level, and then transmit the voltage level peak to the low voltage output terminal LV. In other words, a fast positive surge at the high voltage input terminal HV is transmitted to the node MID1 through the node MID2 and then through the gate-drain coupling capacitor C of the third transistor 101GDThe voltage level of the gate NG1 of the third transistor 101 is quickly raised. The voltage level of the gate NG1 of the third transistor 101 is changed by the eighth resistor 114, the back-to-back eighth to ninth Zener diodes 115-116 and the ninth resistor 121 to raise the voltage level of the gate NG1_ P of the fifth gate driving transistor 123 and turn on the fifth gate driving transistor 123. The voltage level of the gate NG1 of the third transistor 101 is pulled down to ground through the back-to-back twelfth-to-thirteenth Zener diodes 112-113 and the tenth resistor 111. So that the voltage level of the gate NG1 of the third transistor 101 is pulled down to the zener diode + forward diode voltage difference, about 5.8V +0.5V equals 6.3V, the voltage level of the gate NG1 of the third transistor 101 does not exceed 6.3V, and the voltage level transmitted from the node MID1 to the low voltage output LV is less than 6.3V-0.7V equals 5.6V. The utility model provides an adopt multistage 5V NMOS to establish ties, can be able to bear positive negative high-pressure surge, provided the protection circuit who prevents quick surge simultaneously, surge voltage reduces step by step, and low voltage output LV residual voltage is only 5.6V at last, can not damage other electron device who links to each other rather than, increases the security. In addition, the diode mentioned in the present invention may be not only a true diode but also a diodeThe NMOS or PMOS of the connection mode, i.e. the gate and the drain are shorted, and the drain and the source can be regarded as the positive and negative poles of a diode.
Example 3
Please refer to fig. 2 and fig. 3, fig. 3 is a flowchart of a control method according to embodiment 3 of the present invention. The control method is applied to a high-speed positive and negative surge resistant analog switch circuit, the analog switch circuit comprises a first transistor circuit, a second transistor circuit and a third transistor circuit, and the first transistor circuit is electrically connected with the high-voltage input end. The first transistor circuit comprises a first transistor and a first gate driving circuit, the drain of the first transistor is electrically connected with the high-voltage input end, the gate of the first transistor is electrically connected with one end of the first gate driving circuit, the second transistor circuit comprises a second transistor and a second gate driving circuit, the drain of the second transistor is electrically connected with the source of the first transistor circuit, the gate of the second transistor is electrically connected with one end of the second gate driving circuit, the third transistor circuit comprises a third transistor and a third gate driving circuit, the drain of the third transistor is electrically connected with the source of the second transistor circuit, the gate of the third transistor is electrically connected with one end of the third gate driving circuit, the analog switch circuit is used for receiving a voltage signal from the high-voltage input end, the voltage signal comprises a positive voltage signal and/or a negative voltage signal, the positive voltage signal comprises a positive surge signal, the negative voltage signal comprises a negative surge signal, and the control method comprises the following steps:
s310, when the gate of the first transistor is at the first voltage level, the first gate driving circuit starts the first transistor to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in a first stage mode;
s320, when the gate of the second transistor is at the second voltage level, the second gate driving circuit starts the second transistor to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in a second-stage manner;
s330, when the gate of the third transistor is at the third voltage level, the third gate driving circuit activates the third transistor to reduce the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal in the third-pole manner, and then the voltage level peak of the positive surge signal or the voltage level peak of the negative surge signal is reduced to the low threshold voltage level in the third-pole manner, and then the reduced voltage level peak is transmitted to the low-voltage output terminal.
The absolute value of the first voltage level is greater than the absolute value of the second voltage level, and the absolute value of the second voltage level is greater than the absolute value of the third voltage level.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the above description, in combination with the drawings in the embodiments of the present invention, clearly and completely describes the technical solutions in the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the above detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Claims (8)
1. A high-speed resistant positive and negative surge analog switch circuit, the analog switch circuit being configured to receive a voltage signal from a high voltage input, the voltage signal including a positive voltage signal and/or a negative voltage signal, wherein the positive voltage signal includes a positive surge signal and the negative voltage signal includes a negative surge signal, the analog switch circuit comprising:
a first transistor circuit electrically connected to the high voltage input terminal, the first transistor circuit including a first transistor and a first gate driving circuit, a drain of the first transistor being electrically connected to the high voltage input terminal, a gate of the first transistor being electrically connected to one end of the first gate driving circuit, the first gate driving circuit activating the first transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a first stage when the gate of the first transistor is at a first voltage level;
a second transistor circuit including a second transistor and a second gate driving circuit, wherein a drain of the second transistor is electrically connected to a source of the first transistor circuit, a gate of the second transistor is electrically connected to one end of the second gate driving circuit, and when the gate of the second transistor is at a second voltage level, the second gate driving circuit starts the second transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a second stage;
and a third transistor circuit including a third transistor and a third gate driving circuit, wherein a drain of the third transistor is electrically connected to a source of the second transistor circuit, a gate of the third transistor is electrically connected to one end of the third gate driving circuit, and when the gate of the third transistor is at a third voltage level, the third gate driving circuit activates the third transistor to reduce a voltage level peak of the positive surge signal or a voltage level peak of the negative surge signal in a third-pole manner, and then transmits the reduced voltage level peak of the positive surge signal or the reduced voltage level peak of the negative surge signal in the third-pole manner to a low-voltage output terminal after reaching a low threshold voltage level.
2. The analog switch circuit of claim 1, wherein an absolute value of the first voltage level is greater than an absolute value of the second voltage level, and wherein an absolute value of the second voltage level is greater than an absolute value of the third voltage level.
3. The analog switch circuit of claim 1, wherein the first transistor circuit further comprises:
a first switch, one end of which is electrically connected to the source of the first transistor, the other end of which is electrically connected to the gate of the first transistor and one end of the first gate driving circuit, wherein when the gate of the first transistor is at the first voltage level, the first switch is closed to turn off the first transistor;
a first substrate selection circuit, an input terminal of the first substrate selection circuit being electrically connected to the source and the drain of the first transistor, an output terminal of the first substrate selection circuit being electrically connected to the substrate of the first transistor, the first substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the first transistor are at a minimum voltage difference value;
a first high-voltage selection circuit, one end of which is electrically connected with the drain electrode of the first transistor, the high-voltage input end and the input end of the first substrate selection circuit;
one end of the first Zener voltage stabilizing diode is electrically connected with the other end of the first high-selection circuit;
one end of the first resistor is electrically connected with the other end of the first Zener voltage stabilizing diode;
one end of the first diode is electrically connected with the other end of the first resistor;
a first low selection circuit, one end of which is electrically connected with the other end of the first diode, and the other end of which is electrically connected with the input end of the first substrate selection circuit and the source electrode of the first transistor;
the first Zener diode, the first resistor and the first diode are used for controlling a voltage difference value between a source electrode and a drain electrode of the first transistor through the first high-selection circuit and the first low-selection circuit.
4. The analog switch circuit of claim 1, wherein the first gate driver circuit comprises:
a second resistor, one end of which is electrically connected with the gate of the first transistor;
one end of the second Zener voltage stabilizing diode is electrically connected with the other end of the second resistor;
one end of the second diode is electrically connected with the other end of the second Zener voltage stabilizing diode;
one end of the third diode is electrically connected with the other end of the second diode;
one end of the fourth diode is electrically connected with the other end of the third diode;
one end of the fifth diode is electrically connected with the other end of the fourth diode;
the drain electrode of the first gate electrode driving transistor is electrically connected with the other end of the fifth diode;
a first capacitor, one end of which is electrically connected to the other end of the second resistor and one end of the second zener diode, and the other end of which is electrically connected to the gate of the first gate driving transistor, wherein when the voltage signal includes the positive surge signal or the negative surge signal, the gate of the first transistor increases the voltage level of the gate of the first gate driving transistor to a start state through the second resistor and the first capacitor;
a third resistor, one end of which is electrically connected with the other end of the first capacitor and the gate of the first gate drive transistor, and the other end of which is grounded;
a third Zener diode, one end of which is electrically connected with the gate of the first gate driving transistor, the other end of the first capacitor and one end of the third resistor;
and the drain and the gate of the second gate driving transistor are electrically connected with the other end of the third Zener voltage stabilizing diode, and the source of the second gate driving transistor is grounded, wherein the third Zener voltage stabilizing diode and the second gate driving transistor are used for stabilizing the voltage difference value of the gate and the source of the first gate driving transistor.
5. The analog switch circuit of claim 1, wherein the second transistor circuit further comprises:
a second switch, one end of which is electrically connected to the source of the second transistor and the other end of which is electrically connected to the gate of the second transistor and one end of the second gate driving circuit, wherein when the gate of the second transistor is at the second voltage level, the second switch is closed to disconnect the second transistor;
a second substrate selection circuit, an input terminal of the second substrate selection circuit being electrically connected to the source and the drain of the second transistor, an output terminal of the second substrate selection circuit being electrically connected to the substrate of the second transistor, the second substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the second transistor are at a minimum voltage difference value;
a second high-selection circuit, one end of which is electrically connected with the drain electrode of the second transistor, the source electrode of the first transistor and the input end of the second substrate selection circuit;
one end of the fourth Zener voltage stabilizing diode is electrically connected with the other end of the second high-voltage selection circuit;
one end of the fourth resistor is electrically connected with the other end of the fourth Zener voltage stabilizing diode;
one end of the sixth diode is electrically connected with the other end of the fourth resistor;
one end of the second low selection circuit is electrically connected with the other end of the sixth diode, and the other end of the second low selection circuit is electrically connected with the input end of the second substrate selection circuit and the source electrode of the second transistor;
the fourth zener diode, the fourth resistor and the sixth diode are used for controlling the voltage difference value between the source and the drain of the second transistor through the second high-selection circuit and the second low-selection circuit.
6. The analog switch circuit of claim 1, wherein the second gate driver circuit comprises:
a fifth resistor, one end of which is electrically connected with the gate of the second transistor;
one end of the fifth Zener voltage stabilizing diode is electrically connected with the other end of the fifth resistor;
one end of the seventh diode is electrically connected with the other end of the fifth Zener voltage stabilizing diode;
one end of the eighth diode is electrically connected with the other end of the seventh diode;
one end of the ninth diode is electrically connected with the other end of the eighth diode;
one end of the twelfth diode is electrically connected with the other end of the ninth diode;
a third gate driving transistor, wherein the drain electrode of the third gate driving transistor is electrically connected with the other end of the twelfth diode;
a second capacitor, one end of which is electrically connected to the other end of the fifth resistor and one end of the fifth zener diode, and the other end of which is electrically connected to the gate of the third gate driving transistor, wherein when the voltage signal includes the positive surge signal or the negative surge signal, the gate of the second transistor increases the voltage level of the gate of the third gate driving transistor to a start state through the fifth resistor and the second capacitor;
one end of the sixth resistor is electrically connected with the other end of the second capacitor and the gate of the third gate drive transistor, and the other end of the sixth resistor is grounded;
a sixth zener diode having one end electrically connected to the gate of the third gate driving transistor, the other end of the second capacitor, and one end of the sixth resistor;
and the drain and the gate of the fourth gate driving transistor are electrically connected with the other end of the sixth Zener diode, and the source of the fourth gate driving transistor is grounded, wherein the sixth Zener diode and the fourth gate driving transistor are used for stabilizing the voltage difference value between the gate and the source of the third gate driving transistor.
7. The analog switch circuit of claim 1, wherein the third transistor circuit further comprises:
a third switch, one end of which is electrically connected to the source of the third transistor and the other end of which is electrically connected to the gate of the third transistor and one end of the third gate driving circuit, wherein when the gate of the third transistor is at the third voltage level, the third switch is turned on to turn off the third transistor;
a third substrate selection circuit, an input terminal of the third substrate selection circuit being electrically connected to the source and the drain of the third transistor, an output terminal of the third substrate selection circuit being electrically connected to the substrate of the third transistor, the third substrate selection circuit being configured to select a substrate voltage level when the source and the drain of the third transistor are at a minimum voltage difference value;
a third high-selection circuit, one end of which is electrically connected with the drain of the third transistor, the source of the second transistor and the input end of the third substrate selection circuit;
one end of the seventh Zener voltage stabilizing diode is electrically connected with the other end of the third high-selection circuit;
one end of the seventh resistor is electrically connected with the other end of the seventh Zener voltage stabilizing diode;
one end of the eleventh diode is electrically connected with the other end of the seventh resistor;
a third low selection circuit, one end of which is electrically connected to the other end of the eleventh diode, and the other end of which is electrically connected to the input end of the third substrate selection circuit and the source of the third transistor;
wherein the seventh zener diode, the seventh resistor, and the eleventh diode are configured to control a voltage difference value between the source and the drain of the third transistor through the third high-selection circuit and the third low-selection circuit.
8. The analog switch circuit of claim 1, wherein the third gate driver circuit comprises:
an eighth resistor, one end of which is electrically connected to the source of the second transistor and the drain of the third transistor;
one end of the eighth Zener voltage stabilizing diode is electrically connected with the other end of the eighth resistor;
a ninth zener diode, one end of which is electrically connected to the other end of the eighth zener diode;
one end of the ninth resistor is electrically connected with the other end of the ninth Zener voltage stabilizing diode, and the other end of the ninth resistor is grounded;
a fifth gate driving transistor, a gate of which is electrically connected to the other end of the ninth zener diode and one end of the ninth resistor, and a source of which is grounded, wherein when the voltage signal includes the positive surge signal or the negative surge signal, a drain of the third transistor raises a voltage level of the gate of the fifth gate driving transistor to a start state through the eighth resistor, the eighth zener diode, the ninth zener diode and the ninth resistor;
a tenth zener diode having one end electrically connected to the other end of the ninth zener diode, one end of the ninth resistor, and the gate of the fifth gate driving transistor;
an eleventh zener diode having one end electrically connected to the other end of the tenth zener diode and the other end grounded, wherein the tenth zener diode and the eleventh zener diode are used to stabilize a voltage difference between the gate and the source of the fifth gate driving transistor;
a tenth resistor, one end of which is electrically connected to the gate of the third transistor;
a twelfth zener diode, one end of which is electrically connected to the other end of the tenth resistor;
and a thirteenth zener diode having one end electrically connected to the other end of the twelfth zener diode and the other end electrically connected to the drain of the fifth gate driving transistor, wherein after the fifth gate driving transistor is turned on, the tenth resistor, the twelfth zener diode, the thirteenth zener diode and the fifth gate driving transistor form a path to reduce the peak voltage level of the positive surge signal or the peak voltage level of the negative surge signal to a low threshold voltage level and transmit the reduced peak voltage level to the low voltage output terminal.
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| CN202020401327.0U CN211908758U (en) | 2020-03-26 | 2020-03-26 | High-speed positive and negative surge resistant analog switch circuit |
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| CN202020401327.0U CN211908758U (en) | 2020-03-26 | 2020-03-26 | High-speed positive and negative surge resistant analog switch circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253088A (en) * | 2021-06-25 | 2021-08-13 | 上海瞻芯电子科技有限公司 | Transistor gate oxide testing device and system |
| CN113839652A (en) * | 2021-09-17 | 2021-12-24 | 广芯电子技术（上海）股份有限公司 | Bidirectional withstand voltage switch circuit and analog switch |
-
2020
- 2020-03-26 CN CN202020401327.0U patent/CN211908758U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253088A (en) * | 2021-06-25 | 2021-08-13 | 上海瞻芯电子科技有限公司 | Transistor gate oxide testing device and system |
| CN113839652A (en) * | 2021-09-17 | 2021-12-24 | 广芯电子技术（上海）股份有限公司 | Bidirectional withstand voltage switch circuit and analog switch |
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Address after: 6 / F, building 8, Zilang science and Technology City, Nantong innovation District, 60 Chongzhou Avenue, Nantong City, Jiangsu Province, 226017 Patentee after: Jiangsu Dior Microelectronics Co., Ltd Address before: No.16, Wei 14 Road, Sutong science and Technology Industrial Park, Chongchuan District, Nantong City, Jiangsu Province, 226017 Patentee before: DIAO MICROELECTRONICS Co.,Ltd. |