CN211828749U - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

Info

Publication number
CN211828749U
CN211828749U CN202020023540.2U CN202020023540U CN211828749U CN 211828749 U CN211828749 U CN 211828749U CN 202020023540 U CN202020023540 U CN 202020023540U CN 211828749 U CN211828749 U CN 211828749U
Authority
CN
China
Prior art keywords
chip
base
hole
conductive circuit
circuit layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202020023540.2U
Other languages
Chinese (zh)
Inventor
廖勇波
史波
曹俊
曾丹
肖婷
江伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
Original Assignee
Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gree Electric Appliances Inc of Zhuhai, Zhuhai Zero Boundary Integrated Circuit Co Ltd filed Critical Gree Electric Appliances Inc of Zhuhai
Priority to CN202020023540.2U priority Critical patent/CN211828749U/en
Application granted granted Critical
Publication of CN211828749U publication Critical patent/CN211828749U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model relates to the technical field of chip packaging, and discloses a chip packaging structure which comprises a base, wherein the base is provided with a through hole for flowing a refrigerant; a conductive circuit layer formed on the outer surface of the base; at least one chip formed on one side of the conductive circuit layer, which is far away from the through hole, wherein each chip is fixed on the conductive circuit layer through a welding part; the packaging layer is used for packaging the supporting structure, the conductive circuit layer and the chip; and one end of each pin extends into the packaging layer to be electrically connected with the corresponding chip, and the other end of each pin extends out of the packaging layer. This chip package structure sets up the chip including the surface that has tubular structure's base to can realize the multiaspect encapsulation, improve the utilization ratio, have the refrigerant to flow through in the through-hole of base, thereby can realize the better heat dissipation to the chip, this chip package structure can reach high utilization ratio and high heat dissipation rate, thereby realizes the miniaturization when satisfying high heat dissipation demand.

Description

Chip packaging structure
Technical Field
The utility model relates to a chip package technical field, in particular to chip packaging structure.
Background
With the rise of the strategic emerging industry, the power electronic devices and devices play an important role in advanced manufacturing industries such as wind energy, solar energy, heat pumps, hydropower, biomass energy, green buildings, new energy equipment and the like, and the power electronic market develops at a high speed under the double promotion of the investment increment demand and the energy-saving demand and the pull of the high-speed development of the downstream power electronic device industry demand.
However, power semiconductors, such as power MOSFETs (metal-oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors), have become mature as the main force of the power electronic device market, and in the future, in order to further improve the reliability of the system, the power electronic technology will be developed towards high frequency, miniaturization and modularization.
SUMMERY OF THE UTILITY MODEL
The utility model provides a chip packaging structure, this chip packaging structure can improve the radiating efficiency after the chip package, and this chip packaging structure can increase the encapsulation utilization ratio simultaneously.
In order to achieve the above purpose, the utility model provides the following technical scheme:
a chip package structure, comprising:
the base is provided with a through hole for flowing a refrigerant so as to enable the base to have a tubular structure;
the conductive circuit layer is formed on the outer surface of the base;
at least one chip formed on one side of the conductive circuit layer, which is far away from the through hole, wherein each chip is fixed on the conductive circuit layer through a welding part;
the packaging layer is used for packaging the supporting structure, the conductive circuit layer and the chip;
and one end of each pin extends into the packaging layer to be electrically connected with the corresponding chip, and the other end of each pin extends out of the packaging layer.
The chip packaging structure comprises a base, and a conductive circuit layer, a welding part, a chip and a packaging layer which are formed on the outer surface of the base and are arranged in a stacking manner, wherein the base is provided with a through hole for a refrigerant to flow through, and the packaging layer does not cover the opening of the through hole so as to ensure that the refrigerant can flow through the through hole, thereby realizing the heat dissipation of the chip; the outer surface of the base with the tubular structure in the chip packaging structure is provided with the chip, so that multi-surface packaging can be realized, the utilization rate is improved, a refrigerant flows through the through hole of the base, better heat dissipation of the chip can be realized, the chip packaging structure can achieve high utilization rate and high heat dissipation rate, and miniaturization is realized while the high heat dissipation requirement is met.
Preferably, the circuit board further comprises an isolation groove for dividing the conductive circuit layer into a plurality of independent areas for electrical isolation.
Preferably, the chip is electrically connected with the pins through a conductive circuit layer; or the chip is directly electrically connected with the pin.
Preferably, the chip is electrically connected to the conductive circuit layer through a bonding wire, and the conductive circuit layer is electrically connected to the pin through a bonding wire; or the chip is electrically connected with the pin through a bonding wire.
Preferably, the base is a polygonal tubular structure provided with a through hole.
Preferably, the base is a quadrangular tubular structure provided with a through hole, the quadrangular tubular structure comprises two opposite side walls with a larger area and two opposite side walls with a smaller area along the axial direction of the through hole, and the chip is formed on the two opposite side walls with the larger area.
Preferably, in the through hole formed in the base, a cross section perpendicular to the central axis has a circular shape; or, in the through hole formed in the base, the shape of the cross section perpendicular to the central axis is a polygon.
Preferably, the base forms a through hole in which the respective cross sections perpendicular to the central axis have the same size; alternatively, the through hole formed in the base has different sizes of the respective cross sections perpendicular to the central axis.
Preferably, the base is made of an insulating and heat-conducting material.
Preferably, the material of the base is aluminum nitride, silicon nitride or ceramic.
Preferably, the material of the conductive circuit layer is conductive metal.
Preferably, the chip is a power chip and/or an IC chip.
Drawings
Fig. 1 is a schematic front view structure diagram of a chip package structure according to the present invention;
fig. 2 is a schematic diagram of a first side structure perspective view of a chip package structure according to the present invention;
fig. 3 is a schematic diagram of a second side structure of a chip package structure according to the present invention;
fig. 4 is a schematic front view structure diagram of another chip package structure provided by the present invention.
Icon:
1-a base; 2-a through hole; 3-a conductive circuit layer; 4-chip; 5-a weld; 6-packaging layer; 7-a pin; 8-an isolation groove; 9-welding lines.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, the present invention provides a chip package structure, including:
a base 1, wherein the base 1 is formed with a through hole 2 for flowing a refrigerant so that the base 1 has a tubular structure;
a conductive circuit layer 3 formed on the outer surface of the base 1;
at least one chip 4 formed on the side of the conductive circuit layer 3 away from the through hole 2, each chip 4 being fixed to the conductive circuit layer 3 by a soldering portion 5;
the packaging layer 6 is used for packaging the supporting structure, the conductive circuit layer 3 and the chip 4;
and one end of each pin 7 extends into the packaging layer 6 to be electrically connected with the corresponding chip 4, and the other end of each pin 7 extends out of the packaging layer 6.
The chip packaging structure comprises a base 1, and a conductive circuit layer 3, a welding part 5, a chip 4 and a packaging layer 6 which are formed on the outer surface of the base 1 and are stacked, wherein the base 1 is provided with a through hole 2 for flowing a refrigerant, and the packaging layer 6 does not cover the opening of the through hole 2 so as to ensure that the refrigerant can flow in the through hole 2, thereby realizing the heat dissipation of the chip 4; the surface of the base 1 with the tubular structure in the chip packaging structure is provided with the chip 4, so that multi-surface packaging can be realized, the utilization rate is improved, the refrigerant flows through the through hole 2 of the base 1, better heat dissipation of the chip 4 can be realized, the chip packaging structure can achieve high utilization rate and high heat dissipation rate, and miniaturization is realized while the high heat dissipation requirement is met.
The refrigerant that is disposed in the through hole 2 for heat exchange may be gas or liquid, and the present invention is not limited thereto.
Among the above-mentioned chip package structure, the quantity of through-hole 2 on the base 1 is one or more, when setting up to one, can do heat radiating area big as far as to realize better radiating effect, when setting up to a plurality of, can improve chip package structure's stability when improving the radiating efficiency.
As shown in fig. 1, which is a schematic structural diagram of a front view of a chip package structure provided by the present invention, in the chip package structure, a single in-line pin 7 is adopted, and all the pins 7 are disposed on the same side of a base 1; as shown in fig. 4, which is a schematic structural diagram of a front view of another chip package structure provided by the present invention, in the chip package structure, dual-row patch pins 7 are adopted, one part of the pins 7 are disposed on one side of the base 1, the other part of the pins 7 are disposed on the other side of the base 1, and the two parts of the pins 7 are disposed oppositely; different setting modes of the pins 7 correspond to different line leading-out modes, and can be selected according to actual requirements.
Specifically, as shown in fig. 2, the conductive circuit layer 3 further includes an isolation groove 8 for dividing the conductive circuit layer into a plurality of independent areas for electrical isolation.
The chip packaging structure further comprises an isolation groove 8, the isolation groove 8 and the conductive circuit layer 3 are arranged on the same layer to divide the conductive circuit layer 3 into a plurality of independent areas, so that electric isolation of different areas is achieved, signal interference is prevented from occurring, and stability of the chip packaging structure is guaranteed.
Specifically, as shown in fig. 2 and 3, the chip 4 is electrically connected to the pins 7 through the conductive circuit layer 3; alternatively, the chip 4 is directly electrically connected to the leads 7.
When the chip 4 is electrically connected with the pins 7 through the conductive circuit layer 3, the chip 4 is electrically connected with the conductive circuit layer 3 through the bonding wires 9, and the conductive circuit layer 3 is electrically connected with the pins 7 through the bonding wires 9, so that the electrical connection between the chip 4 and the pins 7 can be realized; when the chip 4 is directly electrically connected with the pins 7, the chip 4 can be directly electrically connected with the pins 7 through the bonding wires 9; the specific connection method depends on the distance between the chip 4 and the leads 7 and the convenience of connection.
In particular, in one embodiment, the base 1 is a polygonal tubular structure provided with through holes 2.
A polygonal tubular structure is employed to fix the chip 4 to the outer surface of either side wall of the polygonal tubular structure.
Specifically, as shown in fig. 1 and 4, the base 1 is a quadrangular tube-like structure provided with the through-hole 2, and the quadrangular tube-like structure includes two opposite large-area side walls on which the chips 4 are formed and two opposite small-area side walls in the axial direction of the through-hole 2.
In a common embodiment, the base 1 is a quadrangular tubular structure, and the quadrangular tubular structure includes two opposite side walls with a larger area and two opposite side walls with a smaller area along the axial direction of the through hole 2, that is, the cross section of the quadrangular tubular structure along the direction perpendicular to the extending direction of the quadrangular tubular structure is rectangular, and the chip 4 is formed on the two opposite side walls with the larger area, so that the design is favorable for reducing the thickness of the chip packaging structure while realizing high utilization rate and high heat dissipation rate, and can be applied to electronic devices requiring ultra-thinning.
Specifically, the base 1 is formed with a through hole 2 in which the shape of a cross section perpendicular to the central axis is circular; alternatively, as shown in fig. 1 and 4, the through-hole 2 formed in the base 1 has a polygonal cross-section perpendicular to the central axis.
Through-hole 2 can be for circular or polygon along the shape in the cross-section of perpendicular to center pin, and the cross-sectional shape of through-hole 2 is not the only factor that influences its radiating effect, but chooses for use the cross-sectional shape that makes 2 side wall areas of through-hole to help increasing the heat exchange area of chip 4 and refrigerant, helps improving this chip package structure's radiating efficiency, to the shape in the cross-section of through-hole 2 along the perpendicular to center pin the utility model discloses do not specially limit.
Specifically, the base 1 is formed with through holes 2 in which the respective cross sections perpendicular to the central axis are the same in size; alternatively, the through-hole 2 formed in the base 1 has different sizes of the respective cross sections perpendicular to the central axis.
The size of each section perpendicular to the central axis in the through hole 2 formed in the base 1 may be the same or different, and preferably, the size of each section perpendicular to the central axis in the through hole 2 formed in the base 1 is set to be the same, which facilitates the manufacturing.
Above-mentioned base 1's through-hole 2 can be followed base 1's extending direction and extended also can be followed base 1's extending direction and be the structure of buckling, only need guarantee the refrigerant can by this through-hole 2 internal flow through can, the utility model discloses do not prescribe a limit to.
Specifically, the base 1 is made of an insulating and thermally conductive material.
The base 1 is made of insulating materials to prevent the chips 4 from interfering with each other, and the base 1 is made of heat conducting materials to facilitate heat exchange between the chips 4 and the refrigerant in the through holes 2.
Specifically, the material of the susceptor 1 is aluminum nitride, silicon nitride, or ceramic.
The material of the through hole 2 is not limited to this, and the above is only the material of the through hole 2 commonly used, and may be other materials with insulating property and thermal conductivity, and the utility model discloses do not do the restriction.
Specifically, the conductive circuit layer 3 is made of a conductive metal.
The material of the conductive circuit layer 3 is usually copper, which has high conductivity and low cost.
Specifically, the chip 4 is a power chip 4 and/or an IC chip 4.
The utility model provides a chip package structure is not restricted to and encapsulates power chip 4 and/or IC chip 4, can go on different chip 4 or the different chip 4 of making up according to the demand through the utility model provides a chip package structure encapsulates, for example, can encapsulate into discrete device, Power Module (PM), Intelligent Power Module (IPM) etc, the utility model provides a chip package structure can realize high utilization and high radiating efficiency.
A preparation method of the chip package structure shown in fig. 1 is as follows:
firstly, preparing a base 1 of a tubular structure with a through hole 2; then, forming a conductive circuit layer 3 on the outer surface of the base 1; then, a bonding portion 5 for fixing the chip 4 is formed on the conductive circuit layer 3, and the chip 4 and the bonding portion 5 are fixed; finally, the subsequent curing, cleaning, wire connection, electrical connection, injection molding, electroplating, baking and curing, rib cutting and the like are performed, but the implementation process varies according to different lead-out forms, which is not listed here.
Wherein, the material of above-mentioned welding part 5 is solder, conducting resin, insulating cement etc. and chip 4 can be fixed etc. for welding or bonding with the fixed mode of welding part 5, the utility model discloses do not do the injecing.
It will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (12)

1. A chip package structure, comprising:
the base is provided with a through hole for flowing a refrigerant so as to enable the base to have a tubular structure;
the conductive circuit layer is formed on the outer surface of the base;
at least one chip formed on one side of the conductive circuit layer, which is far away from the through hole, wherein each chip is fixed on the conductive circuit layer through a welding part;
the packaging layer is used for packaging the supporting structure, the conductive circuit layer and the chip;
and one end of each pin extends into the packaging layer to be electrically connected with the corresponding chip, and the other end of each pin extends out of the packaging layer.
2. The chip package structure according to claim 1, further comprising an isolation trench for dividing the conductive circuit layer into a plurality of independent areas for electrical isolation.
3. The chip package structure according to claim 1, wherein the chip is electrically connected to the leads through a conductive circuit layer; or the chip is directly electrically connected with the pin.
4. The chip package structure according to claim 3, wherein the chip is electrically connected to the conductive circuit layer by bonding wires, and the conductive circuit layer is electrically connected to the leads by bonding wires; or the chip is electrically connected with the pin through a bonding wire.
5. The chip package structure according to claim 1, wherein the base is a polygonal tubular structure provided with a through hole.
6. The chip package structure according to claim 5, wherein the base is a quadrangular tube-shaped structure provided with a through hole, and the quadrangular tube-shaped structure includes two opposite side walls with a larger area and two opposite side walls with a smaller area along an axial direction of the through hole, and the chip is formed on the two opposite side walls with the larger area.
7. The chip package structure according to claim 1, wherein in the through hole formed in the base, a cross section perpendicular to a central axis of the through hole has a circular shape; or, in the through hole formed by the base, the shape of the cross section vertical to the central axis of the through hole is a polygon.
8. The chip packaging structure according to claim 1, wherein the base forms a through hole, and the size of each cross section perpendicular to the central axis of the through hole is the same; or, in the through hole formed in the base, the size of each cross section perpendicular to the central axis of the through hole is different.
9. The chip package structure according to claim 1, wherein the base is made of an insulating and thermally conductive material.
10. The chip package structure according to claim 9, wherein the material of the base is aluminum nitride, silicon nitride, or ceramic.
11. The chip package structure according to claim 1, wherein the conductive circuit layer is made of a conductive metal.
12. The chip package structure according to claim 1, wherein the chip is a power chip and/or an IC chip.
CN202020023540.2U 2020-01-06 2020-01-06 Chip packaging structure Active CN211828749U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202020023540.2U CN211828749U (en) 2020-01-06 2020-01-06 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202020023540.2U CN211828749U (en) 2020-01-06 2020-01-06 Chip packaging structure

Publications (1)

Publication Number Publication Date
CN211828749U true CN211828749U (en) 2020-10-30

Family

ID=73048819

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202020023540.2U Active CN211828749U (en) 2020-01-06 2020-01-06 Chip packaging structure

Country Status (1)

Country Link
CN (1) CN211828749U (en)

Similar Documents

Publication Publication Date Title
CN104716128B (en) The manufacturing method of power module, supply convertor and power module
CN102340233B (en) Power module
CN109427707A (en) A kind of the three-dimension packaging structure and packaging method of power device
CN111554645B (en) Double-sided water-cooling SiC half-bridge module packaging structure integrated with laminated busbar
CN110246835B (en) Three-dimensional integrated high-voltage silicon carbide module packaging structure
EP4447105A1 (en) Packaging module and preparation method therefor, and electronic device
CN114551381B (en) Embedded double-sided heat dissipation MOSFET module packaging structure
CN113823625A (en) Power module and motor controller
TWI446462B (en) Power module
CN107146775A (en) A kind of low stray inductance two-side radiation power model
CN113380738B (en) Direct integrated phase-change radiating silicon carbide power module packaging structure
CN114664810A (en) Wide bandgap power semiconductor module based on bypass copper column heat dissipation
CN211828749U (en) Chip packaging structure
CN110085579B (en) High-integration intelligent power module, manufacturing method thereof and air conditioner
US20230187114A1 (en) Power Inductor, Preparation Method of Power Inductor, and System in Package Module
CN217822755U (en) Adopt two-sided heat dissipation module's of graphite copper cushion packaging structure and electric automobile
CN113078135A (en) Chip packaging structure
CN216413057U (en) Semiconductor circuit having a plurality of transistors
CN212209492U (en) Power module
CN211045412U (en) Crimping type SiC power module packaging structure
CN113053850A (en) Power module packaging structure
CN107256829A (en) A kind of method that utilization thin film technique prepares aluminium nitride copper-clad base plate
CN215644461U (en) Power module and electronic equipment
CN115050703B (en) Power device packaging structure and power converter
CN111431480A (en) Thermovoltaic power generation chip

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant