CN211670427U

CN211670427U - Buried structure high-linearity DFB laser chip for optical communication

Info

Publication number: CN211670427U
Application number: CN202020294935.6U
Authority: CN
Inventors: 薛正群; 邓仁亮; 李敬波; 苏辉
Original assignee: Fujian ZK Litecore Ltd
Current assignee: Fujian ZK Litecore Ltd
Priority date: 2020-03-11
Filing date: 2020-03-11
Publication date: 2020-10-13
Anticipated expiration: 2030-03-11

Abstract

The utility model discloses light communication is with burying high linear DFB laser instrument chip of structure, including semi-insulating InP substrate layer, P-InP, N-InP, P-InP electric current block structure layer and N-InP buffer layer, from the bottom up is in proper order above the N-InP buffer layer: the N-InAlAs electronic barrier layer, the AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure layer, the AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer, the P-InP layer, the P-InGaAs layer and the P-InP layer; the P-InP layer is provided with an SiN medium layer, and a ridge waveguide structure is formed from the upper part of the N-InP buffer layer to the P-InP layer; and the SiN medium layer forms a cantilever structure on the ridge waveguide. The utility model discloses effectively improve reliability, the characteristic of generating heat and the high temperature performance that contain Al to bury the structure laser instrument.

Description

Buried structure high-linearity DFB laser chip for optical communication

Technology neighborhood

The utility model relates to a light communication is with burying high linear DFB laser instrument chip of structure, especially through optimizing the adjustment to aspects such as surface treatment, chip structure that epitaxial structure, material grow, realize containing the preparation that Al material buried the structure laser instrument to effectively improve laser instrument reliability optimization, optimize the carrier injection process, improve and generate heat and high temperature performance.

Background art:

the high-linearity DFB laser is widely applied to the fields of cable televisions, backbone networks, space optical communication and the like, the linearity of the laser is generally improved by improving the output power of the laser, an InP/InGaAsP material system is generally adopted, and a buried structure is used for preparing the high-linearity laser, however, the high-temperature carrier confinement capability of the high-linearity DFB laser is relatively poor due to the characteristics of the InGaAsP material structure; the AlGaInAs material has a better electron limiting effect at high temperature due to larger conduction band quantum well energy level difference and lower valence band quantum well energy level difference, and heavy holes are distributed in the quantum well more uniformly, so that the high-temperature performance of the device is improved; however, in the conventional application, because the Al material has oxidation and reliability problems in the air, the InP/AlGaInAs material system generally adopts a ridge structure to prepare the waveguide in practical application, which also causes the problem of poor carrier lateral confinement capability of the chip.

The invention content is as follows:

an object of the utility model is to provide a light communication is with burying high linear DFB laser chip of structure, this light communication is with burying high linear DFB laser chip of structure through optimizing the adjustment to aspects such as surface treatment, chip structure that epitaxial structure, material grow, realize containing the preparation of Al material buries the structure laser to effectively improve laser reliability optimization, optimize the carrier injection process, improve and generate heat and high temperature performance.

The utility model discloses light communication is with burying high linear DFB laser instrument chip of structure, its characterized in that: the primary structure of the laser chip manufacturing process sequentially comprises a semi-insulating InP substrate layer, P-InP, N-InP, a P-InP current blocking structure layer and an N-InP buffer layer from bottom to top, wherein the semi-insulating InP substrate layer, the P-InP, the N-InP, the P-InP current blocking structure layer and the N-InP buffer layer are sequentially arranged above the N-InP buffer layer along the growth sequence: the N-InAlAs electronic barrier layer, the AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure layer, the AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer, the P-InP layer, the P-InGaAs layer and the P-InP layer; an SiN medium layer is arranged on the P-InP layer, and a ridge waveguide structure is formed from the upper part of the N-InP buffer layer to the P-InP layer; and the SiN medium layer forms a cantilever structure on the ridge waveguide.

Furthermore, the structure of the laser chip before molding in the manufacturing process comprises a P-InP current blocking layer and an N-InP current blocking layer which are sequentially arranged on the primary structure from bottom to top at the side of the ridge waveguide structure; a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contact layer are sequentially arranged on the P-InP current blocking layer after the SiN medium layer is removed, a mesa structure is formed on the P-InGaAs ohmic contact layer, holes are formed in the mesa, and a P-type electrode is formed on the mesa and the left side of the mesa; and an N-type electrode is formed by opening a hole in the region on the right side of the mesa.

The utility model discloses add the current limiting layer of PNP on semi-insulating substrate, further improved the vertical restriction ability of current carrier, the adoption of coplane electrode in addition can accomplish the preparation of P face and N face electrode and can need not physics attenuate technology by the step in one step, further reduces the holistic preparation cost of chip.

Description of the drawings:

fig. 1 is a structural diagram of a laser device after chemical etching to form a ridge waveguide, in which fig. 1 is a semi-insulating InP substrate, 2 is a P/N/P-InP current blocking structure, 3 is an N-InP buffer layer, and 4 is sequentially from bottom to top along a growth sequence: an N-InAlAs electron blocking layer 41, an AlGaInAs lower waveguide layer 42, an AlGaInAs strain multi-quantum well and barrier structure 43, an AlGaInAs upper waveguide layer 44, a P-InAlAs electron blocking layer 45, a P-InP spacer layer 46, a P-InGaAsP grating layer 47, a first P-InP layer 48, a P-InGaAs layer 49 and a second P-InP layer 410; and 5, a SiN medium layer is formed on the ridge waveguide to form a cantilever structure.

Fig. 2 is a structural diagram of a laser before a metal electrode is prepared, fig. 2 is a diagram 6 in which SiN is removed from fig. 1, 7 is a first P-InP current blocking layer, 8 is an N-InP current blocking layer, and 9 is sequentially arranged along a growth direction from bottom to top: a second P-InP current blocking layer 91, a P-InP space layer 92, a P-InGaAsP transition layer 93 and a P-InGaAs ohmic contact layer 94; 10 is a formed mesa structure, the mesa width is about 10 microns, a hole is formed on the mesa, and a P-type electrode is formed on the mesa and the left side of the mesa; an opening is made in the region of about 11 on the right side of the mesa to form an N-type electrode.

The specific implementation mode is as follows:

the utility model discloses the preparation method of the high linear DFB laser chip of buried structure for optical communication, (1) grow on semi-insulating substrate the primary epitaxial structure of laser, adopt the holographic method to prepare even grating, and carry out the regrowth of grating; (2) forming a ridge structure by using a single layer of SiN as a mask, forming a ridge waveguide by using a chemical corrosion method, processing the surface of the ridge waveguide, and sequentially finishing the growth of a current barrier layer and the removal of the SiN in epitaxial equipment; then finishing the final growth; (3) and preparing P-type and N-type electrodes on the surface of the sample to form a coplanar electrode structure, and then carrying out subsequent process preparation on the laser to finish the chip preparation process.

In step (1): putting a two-inch semi-insulating InP substrate into an MOCVD cavity, baking at high temperature, and introducing PH₃Removing particles on the surface of the substrate and improving the surface growth quality; then growing P-InP, N-InP and P-InP structures to further inhibit the diffusion of current to the substrate; and then sequentially growing: the N-InP buffer layer, the N-InAlAs electronic barrier layer, the undoped AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure, the undoped AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer and the P-InP protective layer complete primary regrowth; then preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer; then growing the covering layer structure of the grating: P-InP, P-InGaAs, P-InP to complete the burying of the gratingAnd (5) growing.

In step (2): depositing 400nm SiN by PECVD, forming a SiN ridge structure by photoetching, etching and etching methods, and then carrying out isotropic etching on the wafer by adopting a bromine-based etching solution at a low temperature to an N-InP buffer layer; then corroding the wafer in 10% HF for about 3min, then flushing the wafer with deionized water, drying the wafer with nitrogen, and quickly placing the wafer into a prepared MOCVD cavity; the wafers were sequentially placed at three temperature points prior to growth: baking at 450 deg.C, 550 deg.C and 650 deg.C while introducing large amount of AsH₃/H₂The high-temperature baking process under the combination of gas and temperature gradient effectively removes particles, dirt and oxide layer structures on the surface of the Al-containing material and improves the growth surface quality of the material, which is a key point for improving the reliability of the laser with the Al-containing buried structure; sequentially growing a P-InP/N-InP/P-InP current blocking layer to form a transverse limiting effect of a current carrier; and finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contact layer to finish the epitaxial growth of the material.

In step (3): preparing P-type and N-type electrodes on the upper surface of a sample to form a coplanar electrode, thereby effectively reducing a carrier injection path, improving injection efficiency, reducing heating and improving high-temperature characteristics; the specific process comprises the following steps: adopting bromine system corrosive solution to corrode the two sides of the buried ridge to form an N-type InP buffer layer to form a mesa structure, wherein one side of the mesa is a groove, a ridge opening is prepared on one side of the groove to form a P-surface electrode, an N-surface electrode is prepared on the other side of the mesa, and the N/P-type electrodes adopt the same Ti/Pt/Au metal, so that the cost is further reduced; finally, the prepared chip is dissociated into bar strips, and the high-reflection and high-transmittance optical film is evaporated on the cavity surface to complete the preparation of the chip.

The utility model discloses light communication is with preparation method of burying structure high linearity DFB laser instrument chip: firstly, growing a P-N-P InP electronic barrier layer, an N-InP buffer layer, a waveguide structure, a strain AlGaInAs multi-quantum well and a grating layer on a semi-insulating InP substrate; preparing grating, burying and regrowing the grating, preparing ridge structure with single-layer SiN as mask layer, and adding bromine corrosive solutionCorroding the ridge structure until reaching the substrate layer to form a ridge waveguide structure, wherein SiN on the ridge waveguide forms a cantilever; placing the sample in an HF solution for corrosion, and removing oxides on two sides of the ridge waveguide by utilizing the characteristic of slow SiN corrosion rate; then quickly placing the sample into a prepared MOCVD cavity for regrowing an electron blocking structure, baking the wafer at 450 ℃, 550 ℃ and 650 ℃ before growth to remove particle dirt and an oxide layer on the surface of the wafer, particularly on the surface of an aluminum-containing material structure, and introducing a large amount of AsH during baking₃/H₂To inhibit the volatilization of As in AlGaInAs materials; baking to remove dirt and an oxide layer, simultaneously improving the growth quality of the surface of a sample, and then growing a P-N-P InP electron blocking layer structure; etching by adopting HF solution to remove SiN on the surface of the sample, and finally growing a P-InP space layer, a P-InGaAsP transition structure and a P-InGaAs ohmic contact layer in MOCVD equipment to finish epitaxial growth; preparing an electrode structure of the laser, preparing a groove structure on one side of the ridge structure, and opening a hole on the ridge to form a P-surface electrode; and etching the other side of the ridge to the N-InP buffer layer to prepare an N-type electrode, thereby forming an N-surface electrode and forming a coplanar structure of the N-surface electrode and the P-surface electrode.

The following are more detailed steps:

putting the two-inch Fe-doped InP substrate 1 into an MOCVD cavity, baking at 590 ℃ for 15min, and continuously introducing PH during baking₃A gas; then the growth thickness is 50nm, the doping concentration is 10 respectively¹⁸、2×10¹⁸、10¹⁸The P-InP, N-InP and P-InP structures 2 are used for further inhibiting the current from diffusing to the substrate; and then sequentially growing: 1500nm N-InP buffer layer 3, 50nm N-InAlAs electronic barrier layer 41, 80nm undoped AlGaInAs lower waveguide layer 42, AlGaInAs strained multiple quantum well and barrier structure 43, wherein the thicknesses of the well and the barrier are respectively 5nm and 8nm, the number of quantum well layers is 4, 80nm undoped AlGaInAs upper waveguide layer 44, 50nm P-InAlAs electronic barrier layer 45, 50nm P-InP spacer layer 46, 5nm P-InGaAsP grating layer 47 and 15nm P-InP protective layer, and primary regrowth is completed; then, preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer 47;then growing the covering layer structure of the grating: a 50nm first P-InP layer 48, a 50nm P-InGaAs layer 49, and a 50nm second P-InP layer 410 to complete the buried regrowth of the grating.

Depositing a 400nm SiN dielectric layer 5 by PECVD, and forming a SiN ridge structure by photoetching, etching and chemical corrosion, wherein the width of a SiN strip is about 3.5 microns; isotropic etching is carried out on the wafer by adopting bromine-based etching solution at low temperature, the etching depth reaches the N-InP buffer layer 3, a ridge waveguide structure (shown in figure 1) is formed, and the strip width of the quantum well region is about 2 microns; putting the wafer into 10% HF for corrosion for about 3min, removing surface oxides, flushing with deionized water, drying with nitrogen, and immediately putting the wafer into a prepared MOCVD cavity; baking at 450 deg.C, 550 deg.C and 650 deg.C for 20min before growth, introducing large amount of AsH₃/H₂(100/5000 sccm) gas, gradually raising the baking temperature to remove particles, dirt and oxide layer on the surface of the sample; then, a first P-InP current blocking layer 7, an N-InP current blocking layer 8 and a second P-InP current blocking layer 91 (500/1000/200 nm) are sequentially grown, and the current blocking layers form the transverse limiting function of carriers; and finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a 50nm P-InP space layer 92, a 50nm InGaAsP transition layer 93 and a 50nm P-InGaAs ohmic contact layer 94 to finish the epitaxial growth of the material.

Deposition of 150nm SiO by PECVD₂A dielectric layer 5 formed by photoetching, etching and chemical corrosion to form SiO on the surface₂An opening area; stirring and corroding at low temperature by adopting bromine-based corrosive solution until the N-type InP buffer layer 3 forms a chip structure shown in figure 2, and removing SiO on the surface of the chip₂Layer of 400nm SiO deposited by PECVD₂A passivation layer, which is provided with holes at the positions of the table-board in the figure 2 and the area 11 in the figure 2, and metal electrodes are evaporated, and the alloy forms ohmic contact; and dissociating the chip into bar strips with the cavity length of 1000 microns, and evaporating high-transmittance and high-reflectivity optical films on the light-emitting end face and the backlight end face of the laser to finish the preparation of the chip.

Claims

1. A buried-structure high-linearity DFB laser chip for optical communication, characterized in that: the primary structure of the laser chip manufacturing process sequentially comprises a semi-insulating InP substrate layer (1), P-InP, N-InP, a P-InP current blocking structure layer (2) and an N-InP buffer layer (3) from bottom to top, and sequentially above the N-InP buffer layer (3) along the growth sequence from bottom to top: the light-emitting diode comprises an N-InAlAs electron blocking layer (41), an AlGaInAs lower waveguide layer (42), an AlGaInAs strain multi-quantum well and barrier structure layer (43), an AlGaInAs upper waveguide layer (44), a P-InAlAs electron blocking layer (45), a P-InP spacing layer (46), a P-InGaAsP grating layer (47), a first P-InP layer (48), a P-InGaAs layer (49) and a second P-InP layer (410); an SiN medium layer (5) is arranged on the second P-InP layer (410), and a ridge type waveguide structure is formed from the upper portion of the N-InP buffer layer (3) to the second P-InP layer (410); and the SiN medium layer (5) forms a cantilever structure on the ridge waveguide.

2. The buried-structure high-linearity DFB laser chip for optical communication according to claim 1, wherein: the structure before the laser chip manufacturing process is formed comprises a primary structure (6), wherein a first P-InP current blocking layer (7), an N-InP current blocking layer (8) and a second P-InP current blocking layer (91) are sequentially arranged on the side of a ridge waveguide structure from bottom to top; a P-InP space layer (92), an InGaAsP transition layer (93) and a P-InGaAs ohmic contact layer are sequentially arranged on the P-InP current blocking layer (91) with the SiN dielectric layer (5) removed, a mesa structure (10) is formed on the P-InGaAs ohmic contact layer, holes are formed in the mesa, and a P-type electrode is formed on the mesa and the left side of the mesa; an N-type electrode is formed by opening a hole in a region (11) on the right side of the mesa.