CN111181005A - Buried structure high-linearity DFB laser chip for optical communication and preparation method thereof - Google Patents

Buried structure high-linearity DFB laser chip for optical communication and preparation method thereof Download PDF

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CN111181005A
CN111181005A CN202010167005.9A CN202010167005A CN111181005A CN 111181005 A CN111181005 A CN 111181005A CN 202010167005 A CN202010167005 A CN 202010167005A CN 111181005 A CN111181005 A CN 111181005A
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layer
inp
ridge
grating
sin
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薛正群
邓仁亮
李敬波
苏辉
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Fujian ZK Litecore Ltd
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Fujian ZK Litecore Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H01S5/2206—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers based on III-V materials
    • H01S5/2207—GaAsP based
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers

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  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

The invention relates to a buried structure high-linearity DFB laser chip for optical communication and a preparation method thereof, the steps are as follows: (1) growing the primary epitaxial structure of the laser on a semi-insulating substrate, preparing a uniform grating by a holographic method, and regrowing the grating; (2) forming a ridge structure by using a single layer of SiN as a mask, forming a ridge waveguide by using a chemical corrosion method, processing the surface of the ridge waveguide, and sequentially finishing a current barrier layer and final growth in epitaxial equipment; (3) and preparing P-type and N-type electrodes on the surface of the sample to form a coplanar electrode structure, and then carrying out subsequent process preparation on the laser to finish the chip preparation process. The invention realizes the preparation of the laser with the Al-containing material buried structure by optimizing and adjusting the aspects of the epitaxial structure, the surface treatment of the material growth, the chip structure and the like, and effectively improves the reliability optimization of the laser, the carrier injection process and the heating and high-temperature performance.

Description

Buried structure high-linearity DFB laser chip for optical communication and preparation method thereof
The technical neighborhood is as follows:
the invention relates to a buried structure high-linearity DFB laser chip for optical communication and a preparation method thereof, in particular to preparation of a buried structure laser containing an Al material by optimizing and adjusting the aspects of an epitaxial structure, surface treatment of material growth, a chip structure and the like, and the preparation method can effectively improve the reliability optimization of the laser, optimize a carrier injection process and improve heating and high-temperature performance.
Background art:
the high-linearity DFB laser is widely applied to the fields of cable televisions, backbone networks, space optical communication and the like, the linearity of the laser is generally improved by improving the output power of the laser, an InP/InGaAsP material system is generally adopted, and a buried structure is used for preparing the high-linearity laser, however, the high-temperature carrier confinement capability of the high-linearity DFB laser is relatively poor due to the characteristics of the InGaAsP material structure; the AlGaInAs material has a better electron limiting effect at high temperature due to larger conduction band quantum well energy level difference and lower valence band quantum well energy level difference, and heavy holes are distributed in the quantum well more uniformly, so that the high-temperature performance of the device is improved; however, in the conventional application, because the Al material has oxidation and reliability problems in the air, the InP/AlGaInAs material system generally adopts a ridge structure to prepare the waveguide in practical application, which also causes the problem of poor carrier lateral confinement capability of the chip.
The invention content is as follows:
the invention aims to provide a buried structure high-linearity DFB laser chip for optical communication and a preparation method thereof, wherein the buried structure high-linearity DFB laser chip for optical communication realizes the preparation of a buried structure laser containing an Al material by optimizing and adjusting the aspects of an epitaxial structure, surface treatment of material growth, a chip structure and the like, and effectively improves the reliability optimization of the laser, the carrier injection process and the heating and high-temperature performance.
The invention relates to a preparation method of a buried structure high-linearity DFB laser chip for optical communication, which is characterized by comprising the following steps: (1) growing the primary epitaxial structure of the laser on a semi-insulating substrate, preparing a uniform grating by a holographic method, and regrowing the grating; (2) forming a ridge structure by using a single layer of SiN as a mask, forming a ridge waveguide by using a chemical corrosion method, processing the surface of the ridge waveguide, and sequentially finishing the growth of a current barrier layer and the removal of the SiN in epitaxial equipment; then finishing the final growth; (3) and preparing P-type and N-type electrodes on the surface of the sample to form a coplanar electrode structure, and then carrying out subsequent process preparation on the laser to finish the chip preparation process.
Further, in step (1): putting a two-inch semi-insulating InP substrate into an MOCVD cavity, baking at high temperature, and introducing PH3Removing particles on the surface of the substrate and improving the surface growth quality; then growing P-InP, N-InP and P-InP structures to further inhibit the diffusion of current to the substrate; and then sequentially growing: the N-InP buffer layer, the N-InAlAs electronic barrier layer, the undoped AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure, the undoped AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer and the P-InP protective layer complete primary regrowth; then preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer; then growing the covering layer structure of the grating: P-InP, P-InGaAs, P-InP, completing the buried regrowth of the grating.
Further, in the step (2): depositing 400nm SiN by PECVD, forming a SiN ridge structure by photoetching, etching and etching methods, and then carrying out isotropic etching on the wafer by adopting a bromine-based etching solution at a low temperature to an N-InP buffer layer; then corroding the wafer in 10% HF for about 3min, then flushing the wafer with deionized water, drying the wafer with nitrogen, and quickly placing the wafer into a prepared MOCVD cavity; the wafers were sequentially placed at three temperature points prior to growth: baking at 450 deg.C, 550 deg.C and 650 deg.C while introducing large amount of AsH3/H2High temperature baking process under combination of gas and temperature gradient effectively removes particles, smudges and oxide layer structure on Al-containing material surface and improves material growth surface quality, which is suitable for burying AlImproved reliability of structured lasers is a key point; sequentially growing a P-InP/N-InP/P-InP current blocking layer to form a transverse limiting effect of a current carrier; and finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contact layer to finish the epitaxial growth of the material.
Further, in step (3): preparing P-type and N-type electrodes on the upper surface of a sample to form a coplanar electrode, thereby effectively reducing a carrier injection path, improving injection efficiency, reducing heating and improving high-temperature characteristics; the specific process comprises the following steps: adopting bromine system corrosive solution to corrode the two sides of the buried ridge to form an N-type InP buffer layer to form a mesa structure, wherein one side of the mesa is a groove, a ridge opening is prepared on one side of the groove to form a P-surface electrode, an N-surface electrode is prepared on the other side of the mesa, and the N/P-type electrodes adopt the same Ti/Pt/Au metal, so that the cost is further reduced; finally, the prepared chip is dissociated into bar strips, and the high-reflection and high-transmittance optical film is evaporated on the cavity surface to complete the preparation of the chip.
The invention discloses a preparation method of a buried structure high-linearity DFB laser chip for optical communication, which is characterized by comprising the following steps: firstly, growing a P-N-P InP electronic barrier layer, an N-InP buffer layer, a waveguide structure, a strain AlGaInAs multi-quantum well and a grating layer on a semi-insulating InP substrate; preparing a grating, burying and regrowing the grating, preparing and forming a ridge structure by using a single-layer SiN as a mask layer, corroding the ridge structure to a substrate layer by using a bromine system corrosive solution to form a ridge waveguide structure, wherein the SiN on the ridge waveguide forms a cantilever; placing the sample in an HF solution for corrosion, and removing oxides on two sides of the ridge waveguide by utilizing the characteristic of slow SiN corrosion rate; then quickly placing the sample into a prepared MOCVD cavity for regrowing an electron blocking structure, baking the wafer at 450 ℃, 550 ℃ and 650 ℃ before growth to remove particle dirt and an oxide layer on the surface of the wafer, particularly on the surface of an aluminum-containing material structure, and introducing a large amount of AsH during baking3/H2To inhibit the volatilization of As in AlGaInAs materials; baking to remove dirt and an oxide layer, simultaneously improving the growth quality of the surface of a sample, and then growing a P-N-P InP electron blocking layer structure; etching with HF solutionRemoving SiN on the surface of the sample, and finally growing a P-InP space layer, a P-InGaAsP transition structure and a P-InGaAs ohmic contact layer in MOCVD equipment to finish epitaxial growth; preparing an electrode structure of the laser, preparing a groove structure on one side of the ridge structure, and opening a hole on the ridge to form a P-surface electrode; and etching the other side of the ridge to the N-InP buffer layer to prepare an N-type electrode, thereby forming an N-surface electrode and forming a coplanar structure of the N-surface electrode and the P-surface electrode.
The invention provides a buried structure high-linearity DFB laser chip for optical communication, which is characterized in that: the primary structure of the laser chip manufacturing process sequentially comprises a semi-insulating InP substrate layer, P-InP, N-InP, a P-InP current blocking structure layer and an N-InP buffer layer from bottom to top, wherein the semi-insulating InP substrate layer, the P-InP, the N-InP, the P-InP current blocking structure layer and the N-InP buffer layer are sequentially arranged above the N-InP buffer layer along the growth sequence: the N-InAlAs electronic barrier layer, the AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure layer, the AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer, the P-InP layer, the P-InGaAs layer and the P-InP layer; an SiN medium layer is arranged on the P-InP layer, and a ridge waveguide structure is formed from the upper part of the N-InP buffer layer to the P-InP layer; and the SiN medium layer forms a cantilever structure on the ridge waveguide.
Further, the structure of the laser chip before forming in the manufacturing process comprises sequentially growing a P-InP current blocking layer and an N-InP current blocking layer from bottom to top on the primary structure at the side of the ridge waveguide structure, removing the SiN dielectric layer, sequentially growing a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contact layer on the P-InP current blocking layer, forming a mesa structure on the P-InGaAs ohmic contact layer, forming holes on the mesa, and forming a P-type electrode on the mesa and the left side of the mesa; and an N-type electrode is formed by opening a hole in the region on the right side of the mesa.
The invention adopts an effective surface treatment process and further adopts a step-by-step high-temperature baking process to further remove the technological process of the Al material and particles, dirt and an oxide layer formed by exposure in the air, thereby effectively improving the reliability problem of the laser with the Al-containing material buried structure; in addition, the working efficiency of the laser under high temperature or large current is always a difficult problem, except for adopting the characteristics of the Al-containing material and the characteristics of the buried structure, the PNP current limiting layer is added on the semi-insulating substrate, the longitudinal limiting capability of current carriers is further improved, in addition, the coplanar electrode method is further adopted, and for the laser working under large current, the injection efficiency of the current carriers can be further improved, so that the non-radiative coincidence and the heating are reduced, and the reliability problem caused by the thermal problem is improved; in addition, the adoption of the coplanar electrode can finish the preparation of the P-surface electrode and the N-surface electrode in a single step without a physical thinning process, thereby further reducing the preparation cost of the whole chip.
Description of the drawings:
fig. 1 is a structural diagram of a laser device after chemical etching to form a ridge waveguide, in which fig. 1 is a semi-insulating InP substrate, 2 is a P/N/P-InP current blocking structure, 3 is an N-InP buffer layer, and 4 is sequentially from bottom to top along a growth sequence: an N-InAlAs electron blocking layer 41, an AlGaInAs lower waveguide layer 42, an AlGaInAs strain multi-quantum well and barrier structure 43, an AlGaInAs upper waveguide layer 44, a P-InAlAs electron blocking layer 45, a P-InP spacer layer 46, a P-InGaAsP grating layer 47, a P-InP layer 48, a P-InGaAs layer 49 and a P-InP layer 410; and 5, a SiN medium layer is formed on the ridge waveguide to form a cantilever structure.
Fig. 2 is a structural diagram of a laser before a metal electrode is prepared, fig. 2 is a diagram 6 in which SiN is removed from fig. 1, 7 is a P-InP current blocking layer, 8 is an N-InP current blocking layer, and 9 is sequentially arranged along a growth direction from bottom to top: a P-InP current blocking layer 91, a P-InP space layer 92, a P-InGaAsP transition layer 93 and a P-InGaAs ohmic contact layer 94; 10 is a formed mesa structure, the mesa width is about 10 microns, a hole is formed on the mesa, and a P-type electrode is formed on the mesa and the left side of the mesa; an opening is made in the region of about 11 on the right side of the mesa to form an N-type electrode.
The specific implementation mode is as follows:
the invention relates to a preparation method of a buried structure high-linearity DFB laser chip for optical communication, which comprises the following steps of (1) growing a primary epitaxial structure of a laser on a semi-insulating substrate, preparing a uniform grating by adopting a holographic method, and regrowing the grating; (2) forming a ridge structure by using a single layer of SiN as a mask, forming a ridge waveguide by using a chemical corrosion method, processing the surface of the ridge waveguide, and sequentially finishing the growth of a current barrier layer and the removal of the SiN in epitaxial equipment; then finishing the final growth; (3) and preparing P-type and N-type electrodes on the surface of the sample to form a coplanar electrode structure, and then carrying out subsequent process preparation on the laser to finish the chip preparation process.
In step (1): putting a two-inch semi-insulating InP substrate into an MOCVD cavity, baking at high temperature, and introducing PH3Removing particles on the surface of the substrate and improving the surface growth quality; then growing P-InP, N-InP and P-InP structures to further inhibit the diffusion of current to the substrate; and then sequentially growing: the N-InP buffer layer, the N-InAlAs electronic barrier layer, the undoped AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure, the undoped AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer and the P-InP protective layer complete primary regrowth; then preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer; then growing the covering layer structure of the grating: P-InP, P-InGaAs, P-InP, completing the buried regrowth of the grating.
In step (2): depositing 400nm SiN by PECVD, forming a SiN ridge structure by photoetching, etching and etching methods, and then carrying out isotropic etching on the wafer by adopting a bromine-based etching solution at a low temperature to an N-InP buffer layer; then corroding the wafer in 10% HF for about 3min, then flushing the wafer with deionized water, drying the wafer with nitrogen, and quickly placing the wafer into a prepared MOCVD cavity; the wafers were sequentially placed at three temperature points prior to growth: baking at 450 deg.C, 550 deg.C and 650 deg.C while introducing large amount of AsH3/H2The high-temperature baking process under the combination of gas and temperature gradient effectively removes particles, dirt and oxide layer structures on the surface of the Al-containing material and improves the growth surface quality of the material, which is a key point for improving the reliability of the laser with the Al-containing buried structure; sequentially growing a P-InP/N-InP/P-InP current blocking layer to form a transverse limiting effect of a current carrier; finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contactAnd (4) finishing the epitaxial growth of the material.
In step (3): preparing P-type and N-type electrodes on the upper surface of a sample to form a coplanar electrode, thereby effectively reducing a carrier injection path, improving injection efficiency, reducing heating and improving high-temperature characteristics; the specific process comprises the following steps: adopting bromine system corrosive solution to corrode the two sides of the buried ridge to form an N-type InP buffer layer to form a mesa structure, wherein one side of the mesa is a groove, a ridge opening is prepared on one side of the groove to form a P-surface electrode, an N-surface electrode is prepared on the other side of the mesa, and the N/P-type electrodes adopt the same Ti/Pt/Au metal, so that the cost is further reduced; finally, the prepared chip is dissociated into bar strips, and the high-reflection and high-transmittance optical film is evaporated on the cavity surface to complete the preparation of the chip.
The invention discloses a preparation method of a buried structure high-linearity DFB laser chip for optical communication, which comprises the following steps: firstly, growing a P-N-P InP electronic barrier layer, an N-InP buffer layer, a waveguide structure, a strain AlGaInAs multi-quantum well and a grating layer on a semi-insulating InP substrate; preparing a grating, burying and regrowing the grating, preparing and forming a ridge structure by using a single-layer SiN as a mask layer, corroding the ridge structure to a substrate layer by using a bromine system corrosive solution to form a ridge waveguide structure, wherein the SiN on the ridge waveguide forms a cantilever; placing the sample in an HF solution for corrosion, and removing oxides on two sides of the ridge waveguide by utilizing the characteristic of slow SiN corrosion rate; then quickly placing the sample into a prepared MOCVD cavity for regrowing an electron blocking structure, baking the wafer at 450 ℃, 550 ℃ and 650 ℃ before growth to remove particle dirt and an oxide layer on the surface of the wafer, particularly on the surface of an aluminum-containing material structure, and introducing a large amount of AsH during baking3/H2To inhibit the volatilization of As in AlGaInAs materials; baking to remove dirt and an oxide layer, simultaneously improving the growth quality of the surface of a sample, and then growing a P-N-P InP electron blocking layer structure; etching by adopting HF solution to remove SiN on the surface of the sample, and finally growing a P-InP space layer, a P-InGaAsP transition structure and a P-InGaAs ohmic contact layer in MOCVD equipment to finish epitaxial growth; preparing an electrode structure of the laser, preparing a groove structure on one side of the ridge structure, and opening a hole on the ridge to form a P-surface electrode; and on the other side of the ridgeAnd corroding the N-InP buffer layer to prepare an N-type electrode so as to form an N-surface electrode and form a coplanar structure of the N-surface electrode and the P-surface electrode.
The following are more detailed steps:
putting the two-inch Fe-doped InP substrate 1 into an MOCVD cavity, baking at 590 ℃ for 15min, and continuously introducing PH during baking3A gas; then the growth thickness is 50nm, the doping concentration is 10 respectively18、2×1018、1018The P-InP, N-InP and P-InP structures 2 are used for further inhibiting the current from diffusing to the substrate; and then sequentially growing: 1500nm N-InP buffer layer 3, 50nmN-InAlAs electron barrier layer 41, 80nm undoped AlGaInAs lower waveguide layer 42, AlGaInAs strained multiple quantum well and barrier structure 43, wherein the thicknesses of the well and the barrier are respectively 5nm and 8nm, the number of quantum well layers is 4, 80nm undoped AlGaInAs upper waveguide layer 44, 50nm P-InAlAs electron barrier layer 45, 50nm P-InP spacer layer 46, 5nm P-InGaAsP grating layer 47 and 15nmP-InP protective layer, and primary regrowth is completed; then, preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer 47; then growing the covering layer structure of the grating: a 50nm P-InP layer 48, a 50nm P-InGaAs layer 49, and a 50nm P-InP layer 410 to complete the buried regrowth of the grating.
Depositing a 400nm SiN dielectric layer 5 by PECVD, and forming a SiN ridge structure by photoetching, etching and chemical corrosion, wherein the width of a SiN strip is about 3.5 microns; isotropic etching is carried out on the wafer by adopting bromine-based etching solution at low temperature, the etching depth reaches the N-InP buffer layer 3, a ridge waveguide structure (shown in figure 1) is formed, and the strip width of the quantum well region is about 2 microns; putting the wafer into 10% HF for corrosion for about 3min, removing surface oxides, flushing with deionized water, drying with nitrogen, and immediately putting the wafer into a prepared MOCVD cavity; baking at 450 deg.C, 550 deg.C and 650 deg.C for 20min before growth, introducing large amount of AsH3/H2(100/5000 sccm) gas, gradually raising the baking temperature to remove particles, dirt and oxide layer on the surface of the sample; then a P-InP current blocking layer 7, an N-InP current blocking layer 8 and a P-InP current are sequentially grownA barrier layer 91 (500/1000/200 nm), which forms a lateral confinement effect of carriers; and finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a 50nm P-InP space layer 92, a 50nm InGaAsP transition layer 93 and a 50nm P-InGaAs ohmic contact layer 94 to finish the epitaxial growth of the material.
Deposition of 150nm SiO by PECVD2A dielectric layer 5 formed by photoetching, etching and chemical corrosion to form SiO on the surface2An opening area; stirring and corroding at low temperature by adopting bromine-based corrosive solution until the N-type InP buffer layer 3 forms a chip structure shown in figure 2, and removing SiO on the surface of the chip2Layer of 400nm SiO deposited by PECVD2A passivation layer, which is provided with holes at the positions of the table-board in the figure 2 and the area 11 in the figure 2, and metal electrodes are evaporated, and the alloy forms ohmic contact; and dissociating the chip into bar strips with the cavity length of 1000 microns, and evaporating high-transmittance and high-reflectivity optical films on the light-emitting end face and the backlight end face of the laser to finish the preparation of the chip.

Claims (7)

1. A preparation method of a buried structure high-linearity DFB laser chip for optical communication is characterized in that: (1) growing the primary epitaxial structure of the laser on a semi-insulating substrate, preparing a uniform grating by a holographic method, and regrowing the grating; (2) forming a ridge structure by using a single layer of SiN as a mask, forming a ridge waveguide by using a chemical corrosion method, processing the surface of the ridge waveguide, and sequentially finishing the growth of a current barrier layer and the removal of the SiN in epitaxial equipment; then finishing the final growth; (3) and preparing P-type and N-type electrodes on the surface of the sample to form a coplanar electrode structure, and then carrying out subsequent process preparation on the laser to finish the chip preparation process.
2. The method for manufacturing a buried-structure high-linearity DFB laser chip for optical communication according to claim 1, wherein: in step (1): putting a two-inch semi-insulating InP substrate into an MOCVD cavity, baking at high temperature, and introducing PH3Removing particles on the surface of the substrate and improving the surface growth quality; then growing P-InP, N-InP and P-InP structures to further restrain current from flowing to the substrateDiffusion of (2); and then sequentially growing: the N-InP buffer layer, the N-InAlAs electronic barrier layer, the undoped AlGaInAs lower waveguide layer, the AlGaInAs strained multi-quantum well and barrier structure, the undoped AlGaInAs upper waveguide layer, the P-InAlAs electronic barrier layer, the P-InP spacer layer, the P-InGaAsP grating layer and the P-InP protective layer complete primary regrowth; then preparing a uniform grating on the surface of the wafer by adopting a holographic exposure and chemical corrosion method, wherein the grating corrosion depth penetrates through the P-InGaAsP grating layer; then growing the covering layer structure of the grating: P-InP, P-InGaAs, P-InP, completing the buried regrowth of the grating.
3. The method for manufacturing a buried-structure high-linearity DFB laser chip for optical communication according to claim 1, wherein: in step (2): depositing 400nm SiN by PECVD, forming a SiN ridge structure by photoetching, etching and etching methods, and then carrying out isotropic etching on the wafer by adopting a bromine-based etching solution at a low temperature to an N-InP buffer layer; then corroding the wafer in 10% HF for about 3min, then flushing the wafer with deionized water, drying the wafer with nitrogen, and quickly placing the wafer into a prepared MOCVD cavity; the wafers were sequentially placed at three temperature points prior to growth: baking at 450 deg.C, 550 deg.C and 650 deg.C while introducing large amount of AsH3/H2The high-temperature baking process under the combination of gas and temperature gradient effectively removes particles, dirt and oxide layer structures on the surface of the Al-containing material and improves the growth surface quality of the material, which is a key point for improving the reliability of the laser with the Al-containing buried structure; sequentially growing a P-InP/N-InP/P-InP current blocking layer to form a transverse limiting effect of a current carrier; and finally, removing the dielectric layer on the surface of the wafer, and sequentially growing a P-InP space layer, an InGaAsP transition layer and a P-InGaAs ohmic contact layer to finish the epitaxial growth of the material.
4. The method for manufacturing a buried-structure high-linearity DFB laser chip for optical communication according to claim 1, wherein: in step (3): preparing P-type and N-type electrodes on the upper surface of a sample to form a coplanar electrode, thereby effectively reducing a carrier injection path, improving injection efficiency, reducing heating and improving high-temperature characteristics; the specific process comprises the following steps: adopting bromine system corrosive solution to corrode the two sides of the buried ridge to form an N-type InP buffer layer to form a mesa structure, wherein one side of the mesa is a groove, a ridge opening is prepared on one side of the groove to form a P-surface electrode, an N-surface electrode is prepared on the other side of the mesa, and the N/P-type electrodes adopt the same Ti/Pt/Au metal, so that the cost is further reduced; finally, the prepared chip is dissociated into bar strips, and the high-reflection and high-transmittance optical film is evaporated on the cavity surface to complete the preparation of the chip.
5. A preparation method of a buried structure high-linearity DFB laser chip for optical communication is characterized in that: firstly, growing a P-N-P InP electronic barrier layer, an N-InP buffer layer, a waveguide structure, a strain AlGaInAs multi-quantum well and a grating layer on a semi-insulating InP substrate; preparing a grating, burying and regrowing the grating, preparing and forming a ridge structure by using a single-layer SiN as a mask layer, corroding the ridge structure to a substrate layer by using a bromine system corrosive solution to form a ridge waveguide structure, wherein the SiN on the ridge waveguide forms a cantilever; placing the sample in an HF solution for corrosion, and removing oxides on two sides of the ridge waveguide by utilizing the characteristic of slow SiN corrosion rate; then quickly placing the sample into a prepared MOCVD cavity for regrowing an electron blocking structure, baking the wafer at 450 ℃, 550 ℃ and 650 ℃ before growth to remove particle dirt and an oxide layer on the surface of the wafer, particularly on the surface of an aluminum-containing material structure, and introducing a large amount of AsH during baking3/H2To inhibit the volatilization of As in AlGaInAs materials; baking to remove dirt and an oxide layer, simultaneously improving the growth quality of the surface of a sample, and then growing a P-N-P InP electron blocking layer structure; etching by adopting HF solution to remove SiN on the surface of the sample, and finally growing a P-InP space layer, a P-InGaAsP transition structure and a P-InGaAs ohmic contact layer in MOCVD equipment to finish epitaxial growth; preparing an electrode structure of the laser, preparing a groove structure on one side of the ridge structure, and opening a hole on the ridge to form a P-surface electrode; and etching the other side of the ridge to the N-InP buffer layer to prepare an N-type electrode, thereby forming an N-surface electrode and forming a coplanar structure of the N-surface electrode and the P-surface electrode.
6. A buried-structure high-linearity DFB laser chip for optical communication, characterized in that: the primary structure of the laser chip manufacturing process sequentially comprises a semi-insulating InP substrate layer (1), P-InP, N-InP, a P-InP current blocking structure layer (2) and an N-InP buffer layer (3) from bottom to top, and sequentially above the N-InP buffer layer (3) along the growth sequence from bottom to top: the light-emitting diode comprises an N-InAlAs electron blocking layer (41), an AlGaInAs lower waveguide layer (42), an AlGaInAs strain multi-quantum well and barrier structure layer (43), an AlGaInAs upper waveguide layer (44), a P-InAlAs electron blocking layer (45), a P-InP spacing layer (46), a P-InGaAsP grating layer (47), a P-InP layer (48), a P-InGaAs layer (49) and a P-InP layer (410); an SiN medium layer (5) is arranged on the P-InP layer (410), and a ridge type waveguide structure is formed from the upper portion of the N-InP buffer layer (3) to the P-InP layer (410); and the SiN medium layer (5) forms a cantilever structure on the ridge waveguide.
7. The buried-structure high-linearity DFB laser chip for optical communication according to claim 1, wherein: the structure before the laser chip manufacturing process is formed comprises the steps that on a primary structure (6), a P-InP current blocking layer (7), an N-InP current blocking layer (8) and a P-InP current blocking layer (91) are sequentially grown from bottom to top beside a ridge waveguide structure, after a SiN medium layer (5) is removed, a P-InP space layer (92), an InGaAsP transition layer (93) and a P-InGaAs ohmic contact layer are sequentially grown on the P-InP current blocking layer (91), a mesa structure (10) is formed on the P-InGaAs ohmic contact layer, holes are formed in the mesa, and a P-type electrode is formed on the mesa and the left side of the mesa; an N-type electrode is formed by opening a hole in a region (11) on the right side of the mesa.
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CN112636178A (en) * 2021-03-10 2021-04-09 陕西源杰半导体科技股份有限公司 Laser chip and preparation method
CN113594858A (en) * 2021-08-05 2021-11-02 福建中科光芯光电科技有限公司 Epitaxial layer structure of wide-temperature working single-chip multi-wavelength high-speed DFB laser light source, chip and preparation method of chip
CN113668050A (en) * 2021-08-18 2021-11-19 福建中科光芯光电科技有限公司 Laser-assisted heating MOCVD device and working method thereof
CN113783107A (en) * 2021-09-14 2021-12-10 苏州长光华芯光电技术股份有限公司 Manufacturing method of quantum cascade laser
CN118099945A (en) * 2024-04-29 2024-05-28 南京镭芯光电有限公司 Novel preparation method of current limiting structure of buried heterojunction laser

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112636178A (en) * 2021-03-10 2021-04-09 陕西源杰半导体科技股份有限公司 Laser chip and preparation method
CN113594858A (en) * 2021-08-05 2021-11-02 福建中科光芯光电科技有限公司 Epitaxial layer structure of wide-temperature working single-chip multi-wavelength high-speed DFB laser light source, chip and preparation method of chip
CN113668050A (en) * 2021-08-18 2021-11-19 福建中科光芯光电科技有限公司 Laser-assisted heating MOCVD device and working method thereof
CN113783107A (en) * 2021-09-14 2021-12-10 苏州长光华芯光电技术股份有限公司 Manufacturing method of quantum cascade laser
CN113783107B (en) * 2021-09-14 2022-12-02 苏州长光华芯光电技术股份有限公司 Manufacturing method of quantum cascade laser
CN118099945A (en) * 2024-04-29 2024-05-28 南京镭芯光电有限公司 Novel preparation method of current limiting structure of buried heterojunction laser

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