CN211349331U - Data storage expansion interface system - Google Patents
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- CN211349331U CN211349331U CN201922432841.0U CN201922432841U CN211349331U CN 211349331 U CN211349331 U CN 211349331U CN 201922432841 U CN201922432841 U CN 201922432841U CN 211349331 U CN211349331 U CN 211349331U
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Abstract
The utility model particularly relates to a data storage extension interface system belongs to data storage technical field. The device comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-bit data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with the data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with an address line of the data memory; the address line of the main control unit is connected with the input end of the decoder. The utility model discloses broken through main control unit's address line restriction, the capacity restriction that the traditional extension of data storage found has satisfied the real-time access demand of super-large capacity.
Description
Technical Field
The utility model particularly relates to a data storage extension interface system belongs to data storage technical field.
Background
With the increasing popularity of computer network communication, the construction of computer data storage capacity is more and more important. The existing MCU storage expansion construction comprises the following steps that the first step is to expand the access capacity through P1 and P3 pins of a single chip microcomputer, but the storage expansion is limited by the number of P1 and P3 ports, and the expanded capacity is very limited, for example, a common MCS51 single chip microcomputer can only expand 256 memories at most and occupies P1 and P3 pins of an I/O port; the second method is to expand the serial port, for example, serial port data is converted into parallel port data by using a serial-to-parallel chip 74LS164, and the CS pin of each memory is connected, thereby realizing expansion, but the disadvantages of this construction are that the more the expansion is, the longer the serial port sends, the lower the real-time performance is, and the serial port of the MCU is occupied, which increases difficulty and cost. The number of address pins of the MCU limits the access capacity of the memory, and the use of external memory involves complex protocols and drivers. Therefore, how to expand the memory of the MCU to meet the requirement of ultra-large capacity storage becomes a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The utility model provides a break through the capacity restriction that traditional extension found, satisfy the data storage expansion interface system of the real-time access demand of super-large capacity.
The utility model discloses a realize above-mentioned purpose, adopt following technical scheme:
a data storage expansion interface system comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-bit data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with an address line of a data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gate lines of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control line of the main control unit is respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; the output end of the delay trigger is connected with the controller of the data memory.
As the preferred technical scheme of the utility model, all adopt 74LS373 chips for N I/O extension chips.
As the preferred technical scheme of the utility model, the decoder all adopts 74LS138 chips.
As the preferred technical scheme of the utility model, data memory adopts ROM memory or RAM memory.
As the utility model discloses a preferred technical scheme, main control unit's high order data line quantity and low order data line quantity sum are more than data memory's data line quantity.
As a preferred technical solution of the present invention, the delay flip-flop adopts a 74ABT74 chip.
The technical scheme of the utility model for prior art's beneficial effect does:
the utility model discloses utilized unnecessary data line, obtained huge addressing space, broken through main control unit's address line restriction, the capacity restriction that the traditional extension of data storage found has satisfied the real-time access demand of super-large capacity.
Drawings
Fig. 1 is a schematic structural view of the present invention;
fig. 2 is a schematic view of the working process of the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present technical solution, the present solution is explained below by means of specific embodiments.
Referring to fig. 1, a data storage expansion interface system includes a main control unit, a decoder, an and gate circuit, a delay flip-flop, N I/O expansion chips, and a data storage; the low-bit data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with the data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with an address line of the data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gate lines of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control line of the main control unit is respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; the output end of the delay trigger is connected with the controller of the data memory.
And the N I/O expansion chips are 74LS373 chips. The decoders all adopt 74LS138 chips. The data memory adopts a ROM memory or a RAM memory. The sum of the number of the high-order data lines and the number of the low-order data lines of the main control unit is more than the number of the data lines of the data memory. The time delay trigger adopts a 74ABT74 chip.
As shown in fig. 2, during specific operation, the MCU writes data information into a certain data memory address by expansion; the MCU data lines are higher than the number of the memory data lines. The high order of the MCU data line is the address signal of the memory, and the low order of the MCU data line is the data signal of the memory. The address line of the main control unit is connected with part of the address lines of the data memory, and the high-order data line of the main control unit passes through the address line of the I/O expansion chip connecting part of the data memory.
When the MCU writes data into the data memory, the high-order data is used as an address, and the low-order data is used as data. The MCU sends out a standard read-write time sequence, the MCU writes (data line-high, actual memory address) addresses into the 1 st I/O expansion chip to the N-1 st I/O expansion chip, the 1 st I/O expansion chip to the N-1 th I/O expansion chip latch the addresses to the output end, namely, address signals reach the address line of the memory. The 1 st I/O expansion chip to the N-1 st I/O expansion chip latches the address signal to the output terminal, that is, the address signal reaches the address line of the data memory. Both the upper address and the lower address are given to the address lines of the data memory.
The Nth I/O expansion chip is a data line connected with the memory. The address line of the main control unit selects all I/O chips through a decoder, the control signal of the control line of the MCU and the address line of the MCU are decoded and then are subjected to AND gate phase, and the control signal of the control line of the MCU is delayed by a delay trigger and then is sent to the control line of the data memory. The data memory receives the address signal, the control signal and the data, and obtains the correct time sequence, the MCU can store the data into the corresponding position of the memory, and when the MCU writes the data into the data memory, the working steps are repeated.
The utility model discloses broken through main control unit MCU's address line restriction, the capacity restriction of the traditional extension method of data storage has satisfied the real-time access demand of super-large capacity.
The technical features that the utility model has not been described can be realized through or adopt prior art, and no longer give unnecessary details here, and of course, the above-mentioned explanation is not right the utility model discloses a restriction, the utility model discloses also not only be limited to the above-mentioned example, ordinary skilled person in this technical field is in the utility model discloses a change, modification, interpolation or replacement made in the essential scope also should belong to the utility model discloses a protection scope.
Claims (6)
1. A data storage expansion interface system, characterized by: the device comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-bit data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with an address line of a data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gate lines of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control line of the main control unit is respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; the output end of the delay trigger is connected with the controller of the data memory.
2. The data storage expansion interface system of claim 1, wherein: and the N I/O expansion chips are 74LS373 chips.
3. The data storage expansion interface system of claim 1, wherein: the decoders all adopt 74LS138 chips.
4. The data storage expansion interface system of claim 1, wherein: the data memory adopts a ROM memory or a RAM memory.
5. The data storage expansion interface system of claim 1, wherein: the sum of the number of the high-order data lines and the number of the low-order data lines of the main control unit is more than the number of the data lines of the data memory.
6. The data storage expansion interface system of claim 1, wherein: the delay trigger adopts a 74ABT74 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922432841.0U CN211349331U (en) | 2019-12-30 | 2019-12-30 | Data storage expansion interface system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922432841.0U CN211349331U (en) | 2019-12-30 | 2019-12-30 | Data storage expansion interface system |
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| CN211349331U true CN211349331U (en) | 2020-08-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110989942A (en) * | 2019-12-30 | 2020-04-10 | 南京信息工程大学滨江学院 | Data storage expansion interface system and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110989942A (en) * | 2019-12-30 | 2020-04-10 | 南京信息工程大学滨江学院 | Data storage expansion interface system and control method thereof |
| CN110989942B (en) * | 2019-12-30 | 2024-05-14 | 南京信息工程大学滨江学院 | Data storage expansion interface system and control method thereof |
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| CF01 | Termination of patent right due to non-payment of annual fee |