CN110989942B - Data storage expansion interface system and control method thereof - Google Patents
Data storage expansion interface system and control method thereof Download PDFInfo
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- CN110989942B CN110989942B CN201911394186.2A CN201911394186A CN110989942B CN 110989942 B CN110989942 B CN 110989942B CN 201911394186 A CN201911394186 A CN 201911394186A CN 110989942 B CN110989942 B CN 110989942B
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- 238000013500 data storage Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 8
- 230000015654 memory Effects 0.000 claims abstract description 59
- 238000010276 construction Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
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Abstract
The invention particularly relates to a data storage expansion interface system and a control method thereof, belonging to the technical field of data storage. The device comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-order data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with the address line of the data memory; the address line of the main control unit is connected with the input end of the decoder. The invention breaks through the address line limit of the main control unit, the capacity limit of the traditional expansion construction of the data storage, and meets the real-time access requirement of super-large capacity.
Description
Technical Field
The invention particularly relates to a data storage expansion interface system and a control method thereof, belonging to the technical field of data storage.
Background
With the increasing popularity of computer network communications, the construction of computer data storage capacity is becoming increasingly important. The current MCU storage expansion construction comprises the following steps, firstly, the access capacity is expanded through P1 and P3 pins of a singlechip, but the storage expansion is limited by the number of P1 and P3 ports, the expansion capacity is very limited, for example, a common MCS51 singlechip can only expand 256 times and 256 memories at most, and the pins P1 and P3 of I/O ports are occupied; the second is to realize expansion by serial port expansion, for example, serial-parallel chip 74LS164 is used to convert serial port data into parallel port data and connect CS pins of each memory, but the disadvantage of this construction is that the more expansion is, the longer the serial port is sent, the poor real-time performance is, and the serial port of MCU is occupied, thus increasing difficulty and cost. The number of address pins of the MCU, however, limits the access capacity of the memory, and the use of external memory involves complex protocols and drives. Therefore, how to expand the memory of the MCU more to cope with the storage requirement of ultra-large capacity becomes a problem to be solved by the people in the technical field.
Disclosure of Invention
The invention provides a data storage expansion interface system and a control method thereof, which break through the capacity limit of the traditional expansion construction and meet the real-time access requirement of ultra-large capacity.
The invention adopts the following technical scheme to realize the aim:
A data storage expansion interface system comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-order data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends from the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with the address lines of the data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gating lines from the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control lines of the main control unit are respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; and the output end of the delay trigger is connected with a controller of the data memory.
As the preferable technical scheme of the invention, the N I/O expansion chips are 74LS373 chips.
As a preferred embodiment of the invention, the decoder adopts 74LS138 chips.
As a preferred embodiment of the present invention, the data memory is a ROM memory or a RAM memory.
As a preferable technical scheme of the invention, the sum of the number of the high bit data lines and the number of the low bit data lines of the main control unit is more than the number of the data lines of the data memory.
As a preferable technical scheme of the invention, the delay trigger adopts a 74ABT74 chip.
The control method based on the data storage expansion interface system comprises the following steps that step 1, a main control unit sends out a standard read-write time sequence, the main control unit writes address signals into a1 st I/O expansion chip to an N-1 st I/O expansion chip through a high-order data line, and writes data into the 1 st I/O expansion chip to the N-1 st I/O expansion chip through a low-order data line; step 2, the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the address signals to the output end, namely the address signals reach the address lines of the data memory; the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the data to the output end, namely the data reaches the data line of the data memory; step 3, selecting all I/O chips by address lines of the main control unit through a decoder; step 4, decoding the control signals of the control line of the main control unit and the address line of the main control unit, then passing through an AND gate phase, and then delaying by a delay trigger and then sending to the control line of the data memory; and step 5, the data memory receives the address signals, the control signals and the data and obtains the correct time sequence.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention utilizes redundant data lines, obtains huge addressing space, breaks through the address line limit of the main control unit, and meets the real-time access requirement of super-large capacity due to the capacity limit of the traditional expansion construction of data storage.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
Fig. 2 is a schematic diagram of the workflow of the present invention.
Detailed Description
In order to clearly illustrate the technical characteristics of the technical scheme, the scheme is explained by a specific embodiment.
Referring to fig. 1, a data storage expansion interface system includes a main control unit, a decoder, an and gate circuit, a delay trigger, N I/O expansion chips, and a data storage; the low-order data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with the address line of the data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gating lines from the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control line of the main control unit is respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; the output end of the delay trigger is connected with the controller of the data memory.
The N I/O expansion chips are 74LS373 chips. The decoder uses 74LS138 chips. The data memory is a ROM memory or a RAM memory. The sum of the number of the high-order data lines and the number of the low-order data lines of the main control unit is more than the number of the data lines of the data memory. The delay flip-flop employs a 74ABT74 chip. Step 1, a main control unit sends out a standard read-write time sequence, the main control unit writes address signals into a1 st I/O expansion chip to an N-1 st I/O expansion chip through a high-order data line, and writes data into the 1 st I/O expansion chip to the N-1 st I/O expansion chip through a low-order data line; step 2, the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the address signals to the output end, namely the address signals reach the address lines of the data memory; the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the data to the output end, namely the data reaches the data line of the data memory; step 3, selecting all I/O chips by address lines of the main control unit through a decoder; step 4, decoding the control signals of the control line of the main control unit and the address line of the main control unit, then passing through an AND gate phase, and then delaying by a delay trigger and then sending to the control line of the data memory; and step 5, the data memory receives the address signals, the control signals and the data and obtains the correct time sequence.
As shown in fig. 2, in a specific operation, the main control unit MCU writes data information into a certain data memory address by spreading; the MCU data lines are higher than the number of the memory data lines. Wherein the upper bits of the MCU data line are address signals of the memory, and the lower bits of the MCU data line are data signals of the memory. The address line of the main control unit is connected with part of the address line of the data memory, and the high-order data line of the main control unit is connected with part of the address line of the data memory through the I/O expansion chip.
When the MCU writes data to the data memory, the high-order data is used as an address, and the low-order data is used as data.
The MCU sends out standard read-write time sequence, the MCU writes the (data line-high, actual memory address) address into the 1 st I/O expansion chip to the N-1 st I/O expansion chip, the 1 st I/O expansion chip to the N-1 st I/O expansion chip latches the address to the output end, namely the address signal reaches the address line of the memory. The 1 st to N-1 st I/O expansion chips latch the address signals to the output terminals, i.e., the address signals arrive at the address lines of the data memory. Both the upper and lower addresses are given to the address lines of the data memory.
The Nth I/O expansion chip is a data line connected to the memory. The address line of the main control unit selects all I/O chips through the decoder, the control signal of the control line of the MCU and the address line of the MCU are decoded and then are subjected to AND gate phase, and the control signal of the control line of the MCU is delayed by the delay trigger and then is sent to the control line of the data memory. The data memory receives the address signal, the control signal and the data, and obtains the correct time sequence, the MCU can store the data in the corresponding position of the memory, and the MCU repeats the working steps when writing the data into the data memory.
The invention breaks through the address line limit of the main control unit, the capacity limit of the traditional expansion method of data storage, and meets the real-time access requirement of super-large capacity.
The technical features of the present invention that are not described in the present invention may be implemented by or using the prior art, and are not described in detail herein, but the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, but is also intended to be within the scope of the present invention by those skilled in the art.
Claims (1)
1. A control method based on a data storage expansion interface system is characterized in that: step 1, a main control unit sends out a standard read-write time sequence, the main control unit writes address signals into a 1 st I/O expansion chip to an N-1 st I/O expansion chip through a high-bit data line, and writes data into the 1 st I/O expansion chip to the N-1 st I/O expansion chip through a low-bit data line; step 2, the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the address signals to the output end, namely the address signals reach the address lines of the data memory; the 1 st I/O expansion chip to the N-1 st I/O expansion chip latch the data to the output end, namely the data reaches the data line of the data memory; step 3, selecting all I/O chips by address lines of the main control unit through a decoder; step 4, decoding the control signals of the control line of the main control unit and the address line of the main control unit, then passing through an AND gate phase, and then delaying by a delay trigger and then sending to the control line of the data memory; step 5, the data memory receives the address signal, the control signal and the data and obtains the correct time sequence;
The data storage expansion interface system comprises a main control unit, a decoder, an AND gate circuit, a delay trigger, N I/O expansion chips and a data memory; the low-order data line of the main control unit is connected with the data input end of the Nth I/O expansion chip; the data output end of the Nth I/O expansion chip is connected with a data line of the data memory; the high-order data line of the main control unit is respectively connected with the data input ends from the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the data output ends of the 1 st I/O expansion chip to the N-1 st I/O expansion chip are respectively connected with the address lines of the data memory; the address line of the main control unit is connected with the input end of the decoder; the output end of the decoder is respectively connected with the gating lines from the 1 st I/O expansion chip to the N-1 st I/O expansion chip; the output end of the decoder is connected with the first input end of the AND gate circuit; the control lines of the main control unit are respectively connected with the control lines of the N I/O expansion chips and the second input end of the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the delay trigger; the output end of the delay trigger is connected with the controller of the data memory;
The N I/O expansion chips adopt 74LS373 chips;
The decoder adopts 74LS138 chips;
The data memory adopts a ROM memory or a RAM memory;
the sum of the number of the high-order data lines and the number of the low-order data lines of the main control unit is more than the number of the data lines of the data memory;
the delay trigger adopts a 74ABT74 chip.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202904557U (en) * | 2012-11-08 | 2013-04-24 | 广西工学院 | Output data refreshing, read-write and time sequence controller of programmable logical controller (PLC) |
| CN103219037A (en) * | 2013-04-22 | 2013-07-24 | 中国科学院半导体研究所 | In-chip memory with multi-port read-write |
| CN105930287A (en) * | 2016-04-22 | 2016-09-07 | 南京信息工程大学 | Single chip extra-large data external memory extension system and control method thereof |
| CN211349331U (en) * | 2019-12-30 | 2020-08-25 | 南京信息工程大学滨江学院 | Data storage expansion interface system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4083944B2 (en) * | 1999-12-13 | 2008-04-30 | 東芝マイクロエレクトロニクス株式会社 | Semiconductor memory device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202904557U (en) * | 2012-11-08 | 2013-04-24 | 广西工学院 | Output data refreshing, read-write and time sequence controller of programmable logical controller (PLC) |
| CN103219037A (en) * | 2013-04-22 | 2013-07-24 | 中国科学院半导体研究所 | In-chip memory with multi-port read-write |
| CN105930287A (en) * | 2016-04-22 | 2016-09-07 | 南京信息工程大学 | Single chip extra-large data external memory extension system and control method thereof |
| CN211349331U (en) * | 2019-12-30 | 2020-08-25 | 南京信息工程大学滨江学院 | Data storage expansion interface system |
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