CN105930287A - Single chip extra-large data external memory extension system and control method thereof - Google Patents

Single chip extra-large data external memory extension system and control method thereof Download PDF

Info

Publication number
CN105930287A
CN105930287A CN201610254749.8A CN201610254749A CN105930287A CN 105930287 A CN105930287 A CN 105930287A CN 201610254749 A CN201610254749 A CN 201610254749A CN 105930287 A CN105930287 A CN 105930287A
Authority
CN
China
Prior art keywords
chip
expansion
mouth
chip microcomputer
memorizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610254749.8A
Other languages
Chinese (zh)
Other versions
CN105930287B (en
Inventor
朱节中
郭萍
梅永
顾文亚
孟祥瑞
郑玉
吉哲嘉
李凌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Heyuan Data Port Technology Co ltd
Nanjing Lifeng Intellectual Property Agency Special General Partnership Suzhou Branch
Original Assignee
Nanjing University of Information Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University of Information Science and Technology filed Critical Nanjing University of Information Science and Technology
Priority to CN201610254749.8A priority Critical patent/CN105930287B/en
Publication of CN105930287A publication Critical patent/CN105930287A/en
Application granted granted Critical
Publication of CN105930287B publication Critical patent/CN105930287B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus

Abstract

The invention discloses a single chip extra-large data external memory extension system and a control method thereof. The system comprises a single chip, a plurality of first decoders, a plurality of extended I/O port chips, a plurality of second decoders and a plurality of memories, wherein each of the memories is connected with address, data and control buses of the single chip; an input end of each of the first decoders is connected with the address bus of the single chip and an output end of each of the first decoders is connected with an enabling end of each of the extended I/O port chips; an input end of each of the extended I/O port chips is connected with the data bus of the single chip; the extended I/O port chips correspond to the second decoders one to one; an input end of each of the second decoders is connected with an output end of the corresponding extended I/O port chip; an output end of each of the second decoders is connected with a chip selection port of each of the memories. According to the single chip extra-large data external memory extension system and the control method thereof, the capacity limit of the traditional extension method is broken through, and the real-time access demand of ultra-large capacity is satisfied.

Description

A kind of single-chip microcomputer super large data external memory extension system and control method thereof
Technical field
The invention belongs to single-chip microcomputer technical field of memory, particularly to a kind of single-chip microcomputer super large data external memory extension system and control method thereof.
Background technology
Along with becoming increasingly popular of computer network communication, the structure of computer data memory capacity is more and more important.And the address pins number of MCU limits the access capability of memorizer.Therefore, how can more extend the memorizer of MCU to deal with the storage demand of vast capacity, become the problem that the people of this technical field earnestly needs to solve.
Current existing MCU storage extended method is roughly divided into two kinds:
One, extending access capability by P1, P3 pin of single-chip microcomputer, but this method is by P1, P3 mouth number quantitative limitation, the capacity of extension is extremely limited, the most common MCS51 single-chip microcomputer, at most can only extend 256*256 memorizer (fully decoded);And occupy I/O mouth P1, P3 pin;
Two, serial ports expansion is passed through, such as use string to turn and chip 74LS164 is converted into parallel port data serial data, connect the CS(sheet choosing of each memorizer) pin, thus realize extension, but the drawback of this method is the most of extension, and the time that serial ports sends is the longest, and real-time is bad, and take the serial ports of MCU, add difficulty and cost..
Summary of the invention
In order to solve the technical problem that above-mentioned background technology proposes, it is desirable to provide a kind of single-chip microcomputer super large data external memory extension system and control method thereof, break through the capacity limit of conventional Extension method, meet the real time access demand of vast capacity.
In order to realize above-mentioned technical purpose, the technical scheme is that
A kind of single-chip microcomputer super large data external memory extension system, including 1 single-chip microcomputer, multiple first decoders, multiple expansion I/O mouth chips, multiple second decoders and multiple memorizer, each memorizer all with the address of single-chip microcomputer, DCB is connected, the input of each first decoder connects the address bus of single-chip microcomputer, the outfan of the first decoder connects the Enable Pin of each expansion I/O mouth chip, the input of each expansion I/O mouth chip is connected with the data/address bus of single-chip microcomputer, each expansion I/O mouth chip and each second decoder one_to_one corresponding, the input of each second decoder is connected with the outfan of corresponding expansion I/O mouth chip, the outfan of each second decoder sheet with each memorizer respectively selects port to be connected.
Wherein, described expansion I/O mouth chip uses 74LS373 chip.
Wherein, described first decoder, the second decoder all use 74LS138 chip.
Wherein, described memorizer can be ROM, it is also possible to for RAM.
Present invention additionally comprises control method based on above-mentioned single-chip microcomputer super large data external memory extension system, comprise the following steps:
(1) single-chip microcomputer enables each expansion I/O mouth chip by the first decoder;
(2) single-chip microcomputer is to the expansion I/O mouth chip write data enabled;
(3) using the output data of expansion I/O mouth chip as high address, after the second decoder carries out fully decoded, the output data of expansion I/O mouth chip are converted into the chip selection signal of each memorizer, thus gate respective memory;
(4) single-chip microcomputer carries out data access by the instruction of standard access external memory storage to the memorizer of gating;
(5) at next storage cycle, if the memorizer carrying out accessing is constant, the most directly perform step (4), when changing memorizer, then return step (1) and again enable expansion I/O mouth chip.
The beneficial effect that employing technique scheme is brought:
(1) present invention carrys out extension storage capacity by increasing I/O mouth extended chip, determines the memory capacity of extension according to the I/O mouth quantity of extension, breaches the capacity limit (256) utilizing the P1 mouth of common 51 single-chip microcomputers to be extended;
(2) present invention is compared with serial ports expansion, need not take the serial ports of single-chip microcomputer, the real-time of serial ports expansion can reduce along with the increase of extension, and the present invention switches selected memorizer by write instruction, when memorizer is constant, need not again write instruction to select memorizer, be directly accessed, improve the efficiency of access;
(3) using the external memory extended method of the present invention, I/O address and each memorizer of extension are overlapping, when choosing the I/O of each extension, choose the appropriate address of each memorizer the most simultaneously.If memorizer is RAM, overlapping space cannot be used for depositing data, wastes point space, and whole storage space is discontinuous;If memorizer is ROM, being read-only, and the I/O extended only writes, be independent of each other mutually, this space that partly overlaps is to use, can't wasting space, but whole storage space remains discontinuous.The theory of the present invention is exactly to sacrifice few overlapping space, and exchanges huge memory space for, is particularly suited for need not Coutinuous store space but to the highest field of storage capacity requirement and occasion.
Accompanying drawing explanation
Fig. 1 is the block diagram of system of the present invention.
Detailed description of the invention
Below with reference to accompanying drawing, technical scheme is described in detail.
The block diagram of system of the present invention as shown in Figure 1, a kind of single-chip microcomputer super large data external memory extension system, including 1 single-chip microcomputer, multiple first decoders, multiple expansion I/O mouth chips, multiple second decoders and multiple memorizer, each memorizer all with the address of single-chip microcomputer, DCB is connected, the input of each first decoder connects the address bus of single-chip microcomputer, the outfan of the first decoder connects the Enable Pin of each expansion I/O mouth chip, the input of each expansion I/O mouth chip is connected with the data/address bus of single-chip microcomputer, each expansion I/O mouth chip and each second decoder one_to_one corresponding, the input of each second decoder is connected with the outfan of corresponding expansion I/O mouth chip, the outfan of each second decoder sheet with each memorizer respectively selects port to be connected.
In the present embodiment, described expansion I/O mouth chip uses 74LS373 chip.
In the present embodiment, described first decoder, the second decoder all use 74LS138 chip.Wherein the first decoder is used for extending multiple I/O mouth, determines the address of the I/O of extension, and the second decoder is for carrying out fully decoded by the data that the I/O mouth of extension exports, it is achieved the sheet choosing of memorizer.
In the present embodiment, described memorizer can be ROM, it is also possible to for RAM.
Present invention additionally comprises control method based on above-mentioned single-chip microcomputer super large data external memory extension system, comprise the following steps:
(1) single-chip microcomputer enables each expansion I/O mouth chip by the first decoder;
(2) single-chip microcomputer is to the expansion I/O mouth chip write data enabled;
(3) using the output data of expansion I/O mouth chip as high address, after the second decoder carries out fully decoded, the output data of expansion I/O mouth chip are converted into the chip selection signal of each memorizer, thus gate respective memory;
(4) single-chip microcomputer carries out data access by the instruction of standard access external memory storage to the memorizer of gating;
(5) at next storage cycle, if the memorizer carrying out accessing is constant, the most directly perform step (4), when changing memorizer, then return step (1) and again enable expansion I/O mouth chip.
Above example is only the technological thought that the present invention is described, it is impossible to limiting protection scope of the present invention with this, every technological thought proposed according to the present invention, any change done on the basis of technical scheme, within each falling within scope.

Claims (5)

1. a single-chip microcomputer super large data external memory extension system, it is characterized in that: include 1 single-chip microcomputer, multiple first decoders, multiple expansion I/O mouth chips, multiple second decoders and multiple memorizer, each memorizer all with the address of single-chip microcomputer, DCB is connected, the input of each first decoder connects the address bus of single-chip microcomputer, the outfan of the first decoder connects the Enable Pin of each expansion I/O mouth chip, the input of each expansion I/O mouth chip is connected with the data/address bus of single-chip microcomputer, each expansion I/O mouth chip and each second decoder one_to_one corresponding, the input of each second decoder is connected with the outfan of corresponding expansion I/O mouth chip, the outfan of each second decoder sheet with each memorizer respectively selects port to be connected.
A kind of single-chip microcomputer super large data external memory extension system, it is characterised in that: described expansion I/O mouth chip uses 74LS373 chip.
A kind of single-chip microcomputer super large data external memory extension system, it is characterised in that: described first decoder, the second decoder all use 74LS138 chip.
A kind of single-chip microcomputer super large data external memory extension system, it is characterised in that: the type of described memorizer is ROM or RAM.
5. based on the control method of single-chip microcomputer super large data external memory extension system described in claim 1, it is characterised in that comprise the following steps:
(1) single-chip microcomputer enables each expansion I/O mouth chip by the first decoder;
(2) single-chip microcomputer is to the expansion I/O mouth chip write data enabled;
(3) using the output data of expansion I/O mouth chip as high address, after the second decoder carries out fully decoded, the output data of expansion I/O mouth chip are converted into the chip selection signal of each memorizer, thus gate respective memory;
(4) single-chip microcomputer carries out data access by the instruction of standard access external memory storage to the memorizer of gating;
(5) at next storage cycle, if the memorizer carrying out accessing is constant, the most directly perform step (4), when changing memorizer, then return step (1) and again enable expansion I/O mouth chip.
CN201610254749.8A 2016-04-22 2016-04-22 A kind of microcontroller super large data external memory expansion system and its control method Active CN105930287B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610254749.8A CN105930287B (en) 2016-04-22 2016-04-22 A kind of microcontroller super large data external memory expansion system and its control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610254749.8A CN105930287B (en) 2016-04-22 2016-04-22 A kind of microcontroller super large data external memory expansion system and its control method

Publications (2)

Publication Number Publication Date
CN105930287A true CN105930287A (en) 2016-09-07
CN105930287B CN105930287B (en) 2018-07-24

Family

ID=56838691

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610254749.8A Active CN105930287B (en) 2016-04-22 2016-04-22 A kind of microcontroller super large data external memory expansion system and its control method

Country Status (1)

Country Link
CN (1) CN105930287B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110989942A (en) * 2019-12-30 2020-04-10 南京信息工程大学滨江学院 Data storage expansion interface system and control method thereof
CN111444127A (en) * 2020-02-26 2020-07-24 中国电子科技集团公司第二十八研究所 Data external memory expansion interface
CN110989942B (en) * 2019-12-30 2024-05-14 南京信息工程大学滨江学院 Data storage expansion interface system and control method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2189763Y (en) * 1994-03-22 1995-02-15 张家跃 Fire alarm monitored by monolithic processor
CN1289984A (en) * 2000-11-08 2001-04-04 叶建华 Bank CPU card POS
CN2873718Y (en) * 2006-02-14 2007-02-28 中国矿业大学 Anti-falling device brake performance detector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2189763Y (en) * 1994-03-22 1995-02-15 张家跃 Fire alarm monitored by monolithic processor
CN1289984A (en) * 2000-11-08 2001-04-04 叶建华 Bank CPU card POS
CN2873718Y (en) * 2006-02-14 2007-02-28 中国矿业大学 Anti-falling device brake performance detector

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
邹燕秋等: "MCS-51单片机扩展大量高速并行接口的低成本实现", 《中国科技信息》 *
马巨峰等: "8031单片机I/O接口的扩展方法", 《工业仪表与自动化装置》 *
麻伟忠等: "单片机多I/O口线的实用扩展电路", 《电子世界》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110989942A (en) * 2019-12-30 2020-04-10 南京信息工程大学滨江学院 Data storage expansion interface system and control method thereof
CN110989942B (en) * 2019-12-30 2024-05-14 南京信息工程大学滨江学院 Data storage expansion interface system and control method thereof
CN111444127A (en) * 2020-02-26 2020-07-24 中国电子科技集团公司第二十八研究所 Data external memory expansion interface

Also Published As

Publication number Publication date
CN105930287B (en) 2018-07-24

Similar Documents

Publication Publication Date Title
JP5893632B2 (en) Memory controller, system, and method for applying page management policy based on stream transaction information
CN102866865B (en) Multi-version code stream storage circuit architecture for configuration memory dedicated for FPGA (Field Programmable Gate Array)
CN104679681B (en) Ahb bus accesses the high speed Biodge device and its method of work of SRAM on piece
CN110069443B (en) UFS storage array system based on FPGA control and data transmission method
CN102981801B (en) A kind of conversion method of local bus data bit width and device
EP3846036A1 (en) Matrix storage method, matrix access method, apparatus and electronic device
CN103412823A (en) Chip architecture based on ultra-wide buses and data access method of chip architecture
CN103778086A (en) Coarse-grained dynamic reconfigurable system based multi-mode data access device and method
CN110415163A (en) Data matrix transposition method and device for SAR imaging
CN103514140B (en) For realizing the reconfigurable controller of configuration information multi-emitting in reconfigurable system
CN105930287A (en) Single chip extra-large data external memory extension system and control method thereof
CN105955919A (en) Implementation method of reading-writing NANDFlash by multiple MCUs based on FPGA (Field Programmable Gate Array)
CN101071624A (en) Storage unit chip with extensible input/output interface
CN102760045B (en) Intelligent storage device and data processing method thereof
CN104572519A (en) Multiport access and storage controller for multiprocessor and control method thereof
CN201218944Y (en) Structure for implementing flash memory controller caching by double-port RAM
CN203909724U (en) BLOCK RAM cascade realizing structure
CN103678164B (en) A kind of storage level linked method and device
CN109871337A (en) A kind of SSD storaging medium switching method and its system
CN106502923B (en) Storage accesses ranks two-stage switched circuit in cluster in array processor
CN106571156B (en) A kind of interface circuit and method of high-speed read-write RAM
CN106776394B (en) A kind of hardware system and memory of data conversion
CN106445879A (en) SoC architecture with high cost performance
CN211349331U (en) Data storage expansion interface system
CN113778333A (en) Combined chip, storage device and operation method for storage object

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210419

Address after: 215000 a3-206, Xijiao science and Technology Innovation Park, 99 Ren'ai Road, Suzhou Industrial Park, Jiangsu Province

Patentee after: Nanjing Lifeng Intellectual Property Agency (special general partnership) Suzhou Branch

Address before: 210044 Nanjing City, Pukou Province, Nanjing Road, No. 219, No. six, No.

Patentee before: Nanjing University of Information Science and Technology

Effective date of registration: 20210419

Address after: 517000 Alibaba Guangdong cloud computing data center, Puqian Town, Yuancheng District, Heyuan City, Guangzhou City, Guangdong Province

Patentee after: Heyuan data port Technology Co.,Ltd.

Address before: 215000 a3-206, Xijiao science and Technology Innovation Park, 99 Ren'ai Road, Suzhou Industrial Park, Jiangsu Province

Patentee before: Nanjing Lifeng Intellectual Property Agency (special general partnership) Suzhou Branch

TR01 Transfer of patent right