CN115346571A - Command control circuit and method, command decoding circuit and device - Google Patents

Abstract

The disclosure relates to a command control circuit, a command control method, a command decoding circuit and electronic equipment, and relates to the technical field of integrated circuits. The command control circuit includes: a first latch for latching a first periodic signal at a first clock; and the command control module is used for controlling the latching function of the second periodic signal to be opened or closed according to the chip selection signal under the second clock and the latched first periodic signal. The present disclosure provides a method for reducing resource waste during command decoding.

Description

Command control circuit and method, command decoding circuit and device

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a command control circuit, a command control method, a command decoding circuit, and an electronic device.

Background

A fifth generation Double Data Rate-generation Synchronous Random Access Memory (DDR 5 SDRAM) is a high bandwidth computer Memory.

Two types of commands are typically included in DDR 5: single cycle commands and double cycle commands. The decoding structure is suitable for the double-period command, and for the single-period command, the decoding still can be carried out under the condition that no command exists in the second period, so that the resource waste is caused.

It should be noted that the signals disclosed in the above background section are only for enhancement of understanding of the background of the present disclosure and may therefore comprise signals which do not constitute prior art known to a person skilled in the art.

Disclosure of Invention

The present disclosure is directed to a command control circuit, a command control method, a command decoding circuit, and an electronic device, so as to provide a method for reducing resource waste during command decoding.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to a first aspect of the present disclosure, there is provided a command control circuit comprising:

a first latch for latching a first periodic signal at a first clock;

and the command control module is used for controlling the latching function of the second periodic signal to be opened or closed according to the chip selection signal under the second clock and the latched first periodic signal.

In some embodiments of the present disclosure, the command control module is configured to turn off a latch function of the second periodic signal at the second clock in case of a one-cycle command; in the case of a two cycle command, at the second clock, the latching function of the second periodic signal is turned on.

In some embodiments of the present disclosure, the latched first periodic signal comprises: a chip select latch signal, a first bus latch signal, and a second bus latch signal.

In some embodiments of the present disclosure, the command control module is configured to turn off the latch function of the second periodic signal when the chip select latch signal is at a low level and the first bus latch signal and the second bus latch signal are at a high level.

In some embodiments of the present disclosure, the command control module is configured to turn on the latch function of the second periodic signal when the chip select latch signal, the first bus latch signal, and the second bus latch signal are all at a low level.

In some embodiments of the present disclosure, the command control module is configured to turn on the latch function of the second periodic signal when the chip select latch signal and the first bus latch signal are at a low level and the second bus latch signal is at a high level.

In some embodiments of the present disclosure, the command control module is configured to turn on the latch function of the second periodic signal when the chip select latch signal is at a low level, the first bus latch signal is at a high level, and the second bus latch signal is at a low level.

In some embodiments of the present disclosure, the command control module comprises an and gate, a nand gate, and a not gate; wherein,

the input end of the AND gate is accessed to the chip selection latch signal, the first bus latch signal and the second bus latch signal, and the NOT gate is arranged on a line accessed to the chip selection latch signal;

the input end of the NAND gate is connected with the output end of the AND gate and a chip selection signal under the current clock, and the output end of the NAND gate is connected with the second latch.

In some embodiments of the present disclosure, the second latch is the first latch.

In some embodiments of the present disclosure, the second latch is one or more of an address latch, a command latch, and an array latch.

According to a second aspect of the present disclosure, there is provided a command control method including:

latching a first periodic signal at a first clock;

and controlling the latch function of the second periodic signal to be switched on or switched off according to the chip selection signal under the second clock and the latched first periodic signal.

In some embodiments of the present disclosure, controlling the latching function of the second periodic signal to be turned on or off according to the chip select signal at the second clock and the latched first periodic signal comprises:

under the condition of a single-cycle command, closing the latching function of the second periodic signal at the second clock;

in the case of a two cycle command, at the second clock, the latching function of the second periodic signal is turned on.

In some embodiments of the present disclosure, the latched first periodic signal comprises: a chip select latch signal, a first bus latch signal, and a second bus latch signal.

According to a third aspect of the present disclosure, there is provided a command decoding circuit comprising the above-mentioned command control circuit and command decoder; wherein,

the output end of the first latch of the command control circuit is connected with the input end of the command decoder.

According to a fourth aspect of the present disclosure, there is provided an electronic device including the above-described command control circuit.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

the command control circuit provided by the exemplary embodiment of the present disclosure is configured to turn off a latch function of a second periodic signal at a second clock in case of a one-cycle command according to a chip select signal at the second clock and the latched first periodic signal; and in the case of a double-period command, starting a latch function of the second period signal at the second clock. Therefore, the functions of continuously executing latch and subsequent decoding and the like in the second clock for the double-period command can be achieved; in addition, the latch function can be closed when the second clock is used for the single-cycle command, so that unnecessary waste can be avoided when the single-cycle command is executed, and the purposes of saving cost and reducing energy consumption can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a command truth table for a DDR5 in accordance with an exemplary embodiment of the present disclosure;

FIG. 2 schematically illustrates a block diagram of a command control circuit according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a structural diagram of a command control module in a command control circuit according to an exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a structural schematic of a command control circuit according to an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a flow chart of a command control method according to an exemplary embodiment of the present disclosure;

fig. 6 schematically shows a structural diagram of a command decoding circuit according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

DDR5 is the abbreviation of the fifth generation DDR SDRAM, DDR SDRAM is the abbreviation of English Double Data Rate SDRAM, chinese is translated into Double Rate SDRAM, SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, is translated into Synchronous Dynamic Random Access Memory, and the Synchronous object is the system clock frequency. Thus, in combination, DDR5 means the fifth generation DDR SDRAM.

DDR5 is a CA bus which synthesizes command and address signals for the first time in the memory technology history, and compared with the independent characteristics of DDR4 and the command and address signal pins in previous memory products, the DDR5 analysis mode has great difference. In particular, in DDR4 and previous memory products, when the chip select signal is active, the DRAM command receiver samples all command signals to resolve the current command and samples the address signal as needed to obtain the address signal when the rising edge is imminent, which means that all operations can be completed in one clock cycle. Because DDR5 adopts the CA bus, many commands can be completed only by two clock cycles, namely when the first rising edge comes, the CA signal is sampled to analyze the command, and when the second rising edge comes, the other CA signal is sampled to analyze the address.

Referring to FIG. 1, a command truth table for DDR5 (which is taken from DDR5 Full Spec Draft Rev0.1) is shown, where a double cycle command is shown in region one 101 and a single cycle command is shown in region two 102. For DDR5, the bus Pins CA Pins total 14: CA0-CA13, where CA0 and CA1 are used to distinguish between first and second periodic commands. As can be seen, the commands for CA0 and CA1, both high H, are single cycle commands, and the other cases are double cycle commands.

In fig. 1, CS _ n represents a chip select signal, and for a two-cycle command, when CS _ n is at a low level L, the command is resolved, i.e., the first cycle command is completed; when CS _ n is high H, the address is resolved, i.e. the second cycle instruction is completed. For the one-cycle command, the parsing completes all commands only when CS _ n is at low level L, and the Deselect command is executed when CS _ n is at high level H, i.e. no parsing operation is performed.

Based on this, the exemplary embodiments of the present disclosure provide a command control circuit, which can be used for two types of commands, namely, a single-cycle command and a double-cycle command, and can also achieve the purpose of reducing power consumption, it should be noted that the command control circuit provided by the exemplary embodiments of the present disclosure is not only suitable for DDR5 memories, but also can be used in other memories having a single-cycle command and/or a double-cycle command, and the specific use range of the exemplary embodiments of the present disclosure is not particularly limited.

Referring to fig. 2, the command control circuit 200 includes: a first latch 220 and a command control module 240; wherein,

a first latch 220 for latching a first periodic signal at a first clock;

and a command control module 240 for controlling the latch function of the second periodic signal to be turned on or off according to the chip select signal in the second clock and the latched first periodic signal.

In practical application, decoding of the command is usually started when latching the signal in the command, and the signal in the command is latched at the first clock; at the second clock, the latched signal is decoded. Therefore, in the exemplary embodiment of the disclosure, the first clock latches the signal in the command to obtain the first periodic signal.

For the two-cycle command, the first cycle signal is a signal obtained when CS _ n is at a low level L in fig. 1; for the one-cycle command, the first cycle signal is the signal obtained when CS _ n is at low level L in fig. 1, and is the signal in the one-cycle command.

In practical applications, the first latch is a command latch, and mainly latches signals in a command, where the latched signals include a chip select latch signal CS _ n _ d, a plurality of bus latch signals, and the like.

In the exemplary embodiment of the present disclosure, the latched first periodic signal mainly includes a chip select latch signal CS _ n _ d, a first bus latch signal CA0_ d, and a second bus latch signal CA1_ d.

Under the second clock, the chip select signal CS _ n is a high-level H signal, and at this time, the second periodic signal of the two-period command is collected, and the select command is executed by the one-period command. The command control module 240 in the command control circuit provided in the exemplary embodiment of the present disclosure is mainly used for turning off a latch function of a second periodic signal at the second clock in case of a single-period command according to a chip selection signal at the second clock and the latched first periodic signal; in the case of a two cycle command, at the second clock, the latching function of the second periodic signal is turned on. Therefore, the functions of continuously executing latch and subsequent decoding and the like in the second clock for the double-period command can be achieved; in addition, the latch function can be closed when the second clock is used for the single-cycle command, so that unnecessary waste can be avoided when the single-cycle command is executed, and the purposes of saving cost and reducing energy consumption can be achieved.

The exemplary embodiment of the present disclosure takes the command truth table of DDR5 shown in fig. 1 as an example to describe specific signal levels as follows:

the command control module 240 is configured to, when the chip select latch signal CS _ n _ d is at a low level 0, and the first bus latch signal CA0_ d and the second bus latch signal CA1_ d are at a high level 1, indicate that the command is a single-cycle command, and then close the latch function of the second cycle signal.

The command control module 240 is configured to, when the chip select latch signal CS _ n _ d, the first bus latch signal CA0_ d, and the second bus latch signal CA1_ d are all low level 0, indicate that the command is a two-cycle command, and then start the latch function of the second cycle signal.

The command control module 240 is configured to, when the chip select latch signal CS _ n _ d and the first bus latch signal CA0_ d are at a low level 0, and the second bus latch signal CA1_ d is at a high level 1, indicate that the command is a two-cycle command, and then start the latch function of the second cycle signal.

The command control module 240 is further configured to, when the chip select latch signal CS _ n _ d is at a low level 0, the first bus latch signal CA0_ d is at a high level 1, and the second bus latch signal CA1_ d is at a low level 0, indicate that the command is a double-cycle command, and then start the latch function of the second cycle signal. The latch function of the second periodic signal refers to the latch function under the second clock. The latch function at the second clock includes one or more of a command latch function, an address latch function, and an array latch function.

It should be noted that, as products develop, the command truth table may change, and therefore, whether the chip select latch signal CS _ n _ d, the first bus latch signal CA0_ d and the second bus latch signal CA1_ d are at a low level 0 or a high level 1 needs to be adjusted and changed according to the actual command truth table, which is not limited in the exemplary embodiment of the present disclosure.

The exemplary embodiment of the present disclosure determines the command control module with a circuit structure shown in fig. 3, in practical applications, the implementation of the command control module is not limited to the structure shown in fig. 3, and any implementation that can implement the above functions falls within the scope of the present disclosure.

Referring to fig. 3, the command control module 240 provided in the exemplary embodiment of the present disclosure includes an and gate 301, a nand gate 303, and a not gate 305; the command control module 240 is a structure of the latch and the decoder in a high-enable scenario, and the structure in a low-enable scenario may be referred to and set, which is not described herein any more.

The input end of the AND gate 301 is connected to a chip selection latch signal CS _ n _ d, a first bus latch signal CA0_ d and a second bus latch signal CA1_ d; the not gate 305 is provided on a line connected to the chip select latch signal CS _ n _ d, and is configured to negate the chip select latch signal CS _ n _ d.

The input end of the nand gate 303 is connected with the output end of the and gate 301 and a chip selection signal CS _ n under the current clock, and the output end of the nand gate 303 is connected with the second latch.

In practical application, if the chip select latch signal CS _ n _ d is at a low level 0 and is at a high level 1 after negation, the first bus latch signal CA0_ d and the second bus latch signal CA1_ d are at a high level 1, at this time, these three signals pass through the and gate 301 and then output a high level 1, if the current clock is the first clock, the chip select signal CS _ n under the first clock is at a low level 0, the high level 1 output by the and gate 301 and the low level 0 of the chip select signal CS _ n under the first clock pass through the nand gate 303 and obtain a high level 1, and in case of enabling the high level, at this time, the first cycle signal can be normally obtained.

If the current clock is the second clock, the chip select signal CS _ n under the second clock is at the high level 1, and the high level 1 output by the and gate 301 and the high level 1 of the chip select signal CS _ n under the second clock pass through the nand gate 303 to obtain the low level 0.

In practical applications, if the chip select latch signal CS _ n _ d is at a low level 0 and is at a high level 1 after negation, the first bus latch signal CA0_ d and the second bus latch signal CA1_ d are at a low level 0, at this time, these three signals pass through the and gate 301 and then output a low level 0, if the current clock is the first clock, the chip select signal CS _ n under the first clock is at a low level 0, the low level 0 output by the and gate 301 and the low level 0 of the chip select signal CS _ n under the first clock pass through the nand gate 303 and then obtain a high level 1, and in a case of enabling the high level, at this time, the first cycle signal can be normally obtained.

If the current clock is the second clock, the chip select signal CS _ n under the second clock is at the high level 1, and the low level 0 output by the and gate 301 and the high level 1 of the chip select signal CS _ n under the second clock pass through the nand gate 303 to obtain the high level 1.

In practical applications, if the chip select latch signal CS _ n _ d is at a low level 0 and is at a high level 1 after negation, the first bus latch signal CA0_ d is at a low level 0, and the second bus latch signal CA1_ d is at a high level 1, at this time, these three signals pass through the and gate 301 and then output a low level 0, if the current clock is the first clock, the chip select signal CS _ n under the first clock is at a low level 0, the low level 0 output by the and gate 301 and the low level 0 of the chip select signal CS _ n under the first clock pass through the nand gate 303 to obtain a high level 1, and in a case of enabling the high level, the first cycle signal can be normally obtained.

If the current clock is the second clock, the chip select signal CS _ n under the second clock is at the high level 1, and the low level 0 output by the and gate 301 and the high level 1 of the chip select signal CS _ n under the second clock pass through the nand gate 303 to obtain the high level 1.

In practical application, if the chip select latch signal CS _ n _ d is at a low level 0, and is at a high level 1 after negation, the first bus latch signal CA0_ d is at a high level 1, and the second bus latch signal CA1_ d is at a low level 0, at this time, these three signals pass through the and gate 301 and then output a low level 0, if the current clock is the first clock, the chip select signal CS _ n under the first clock is at a low level 0, the low level 0 output by the and gate 301 and the low level 0 of the chip select signal CS _ n under the first clock pass through the nand gate 303 to obtain a high level 1, and under the condition of enabling the high level, at this time, the first cycle signal can be normally obtained.

If the current clock is the second clock, the chip selection signal CS _ n under the second clock is at high level 1, the low level 0 output by the and gate 301 and the high level 1 of the chip selection signal CS _ n under the second clock pass through the nand gate 303 to obtain high level 1, and under the condition of high level enabling, the latch function of the second periodic signal can be started at this time, and the method is suitable for the double-period command.

It can be seen that the command control module 240 provided in the exemplary embodiment of the present disclosure satisfies the requirement of turning off or turning on the latch function of the second periodic signal according to the single-period command and the double-period command in the high-enable situation, and can achieve the purpose of turning off the latch function of the second periodic signal in the single-period command in the present disclosure, and has the effects of saving power consumption and saving resources.

Referring to fig. 4, a schematic structural diagram of a command control circuit provided in an exemplary embodiment of the present disclosure is shown, wherein an output terminal of the command control module 240 is connected to an enable terminal of the second latch, and is used for controlling the second latch to be opened or closed.

In actual practice, the second latch may be one or more of command latch 411, array latch 412, and address latch 413. In addition, the second latch may also be the first latch 220, that is, at the time of the first clock, the command control module 240 is configured to obtain the first periodic signal from the first latch 220, and at the time of the second clock, the command control module 240 controls the first latch 220 to be turned on or off. The first latch 220 here is a command latch.

The disclosed exemplary embodiment also provides a command control method. Referring to fig. 5, the command control method may specifically include the following steps:

step S52, latching a first periodic signal during a first clock;

and S54, controlling the latch function of the second periodic signal to be turned on or off according to the chip selection signal under the second clock and the latched first periodic signal.

In some embodiments of the present disclosure, controlling the latch function of the second periodic signal to be turned on or off according to the chip select signal at the second clock and the latched first periodic signal comprises: under the condition of a single-cycle command, closing the latching function of the second periodic signal at the second clock; and in the case of a double-period command, starting a latch function of the second period signal at the second clock.

In some embodiments of the present disclosure, the latched first periodic signal includes: a chip select latch signal, a first bus latch signal, and a second bus latch signal.

The command control method provided by the exemplary embodiment of the present disclosure may determine the single-period command and the double-period command through the latched first period signal, and then control the latch function of the second period signal to be turned on or off in combination with the chip selection signal under the second clock, so as to achieve the purpose of turning on the latch function of the second period signal when the double-period command is executed, and turning off the latch function of the second period signal when the single-period command is executed. Therefore, the power consumption can be saved when the single-cycle command is executed, unnecessary resource waste is reduced, and the utilization rate of resources is improved.

The specific details of each step in the command control method have been described in detail in the corresponding command control circuit, and therefore are not described herein again.

Referring to fig. 6, the exemplary embodiments of the present disclosure also provide a command decoding circuit, which includes a command decoder 610 and the above-mentioned command control circuit, in which an output terminal of the first latch is connected to an input terminal of the command decoder, and the command decoder is configured to decode an address signal output from the first latch.

In the exemplary embodiments of the present disclosure, the specific structural form of the command control circuit in the command decoding circuit has been described in detail in the above embodiments, and thus is not described in detail here.

The exemplary embodiments of the present disclosure further provide an electronic device, which includes the above command control circuit, wherein details of the specific structure of the command control circuit have been described in detail in the above embodiments, and are not described herein again.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the disclosure are all or partially effected when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or can comprise one or more data storage devices, such as a server, a data center, etc., that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others. In the embodiment of the present disclosure, the computer may include the aforementioned apparatus.

While the disclosure has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the disclosure has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the disclosure. Accordingly, the specification and drawings are merely illustrative of the present disclosure as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the disclosure. It will be apparent to those skilled in the art that various changes and modifications may be made to the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.

Claims (15)

1. A command control circuit, comprising:

a first latch for latching a first periodic signal at a first clock;

and the command control module is used for controlling the latching function of the second periodic signal to be opened or closed according to the chip selection signal under the second clock and the latched first periodic signal.

2. The command control circuit of claim 1, wherein the command control module is configured to disable the latching function of the second periodic signal at the second clock in the case of a one-cycle command; and in the case of a double-period command, starting a latch function of the second period signal at the second clock.

3. The command control circuit of claim 2, wherein the latched first periodic signal comprises: a chip select latch signal, a first bus latch signal, and a second bus latch signal.

4. The command control circuit of claim 3, wherein the command control module is configured to disable the latching function of the second periodic signal when the chip select latch signal is low and the first bus latch signal and the second bus latch signal are high.

5. The command control circuit of claim 3, wherein the command control module is configured to enable the latching of the second periodic signal when the chip select latch signal, the first bus latch signal, and the second bus latch signal are all low.

6. The command control circuit of claim 3, wherein the command control module is configured to enable the latching of the second periodic signal when the chip select latch signal and the first bus latch signal are low and the second bus latch signal is high.

7. The command control circuit of claim 3, wherein the command control module is configured to enable the latching function of the second periodic signal when the chip select latch signal is low, the first bus latch signal is high, and the second bus latch signal is low.

8. The command control circuit of any one of claims 3-7, wherein the command control module comprises an AND gate, a NAND gate, and a NOT gate; wherein,

the input end of the AND gate is accessed to the chip selection latch signal, the first bus latch signal and the second bus latch signal, and the NOT gate is arranged on a line accessed to the chip selection latch signal;

the input end of the NAND gate is connected with the output end of the AND gate and a chip selection signal under the current clock, and the output end of the NAND gate is connected with the second latch.

9. The command control circuit of claim 8, wherein the second latch is the first latch.

10. The command control circuit of claim 9, wherein the second latch is one or more of an address latch, a command latch, and an array latch.

11. A command control method, comprising:

latching a first periodic signal at a first clock;

and controlling the latch function of the second periodic signal to be switched on or switched off according to the chip selection signal under the second clock and the latched first periodic signal.

12. The method of claim 11, wherein controlling the latching function of the second periodic signal to turn on or off according to the chip select signal at the second clock and the latched first periodic signal comprises:

under the condition of a single-cycle command, closing the latching function of the second periodic signal at the second clock;

in the case of a two cycle command, at the second clock, the latching function of the second periodic signal is turned on.

13. The command control method according to claim 11 or 12, wherein the latched first periodic signal includes: a chip select latch signal, a first bus latch signal, and a second bus latch signal.

14. A command decoding circuit comprising the command control circuit and the command decoder according to any one of claims 1 to 10; wherein,

the output end of the first latch of the command control circuit is connected with the input end of the command decoder.

15. An electronic device characterized by comprising a command control circuit according to any one of claims 1-10.

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