CN210924901U - Communication circuit of cascaded power unit of high-voltage frequency converter - Google Patents
Communication circuit of cascaded power unit of high-voltage frequency converter Download PDFInfo
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- CN210924901U CN210924901U CN201922462790.6U CN201922462790U CN210924901U CN 210924901 U CN210924901 U CN 210924901U CN 201922462790 U CN201922462790 U CN 201922462790U CN 210924901 U CN210924901 U CN 210924901U
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Abstract
The utility model discloses a communication circuit of a cascade power unit of a high-voltage frequency converter, which comprises a main circuit and a control circuit, wherein the main circuit comprises three voltage output modules which are connected in a star or triangle shape; the voltage output module comprises a plurality of power units which are connected in series, the control circuit comprises a main control board, a voltage and current acquisition board and a data conversion board, the voltage output module comprises a data acquisition board, and the data acquisition board is in communication connection with the power units of the voltage output module; the main control board is respectively in communication connection with the data conversion board and the data acquisition board; the data conversion board is in communication connection with the data acquisition board and the voltage and current acquisition board of each voltage output module. The utility model discloses under the condition that the master control board is redesigned, the communication ability and the analog signal processing ability of master control board have been expanded.
Description
[ technical field ]
The utility model relates to a high-voltage inverter especially relates to a high-voltage inverter cascade type power unit's communication circuit.
[ background art ]
Ground and mining cascade connection formula high-voltage inverter, because power unit is many, the semaphore is big, and real-time control response requires highly, and the main control board uses ordinary singlechip to do communication control, and first is the resource limited, and the serial ports is few, and second serial ports communication needs to occupy CPU time to it is timesharing multiplexing, the performance is not enough during real-time data processing, and communication capacity is relatively poor.
[ contents of utility model ]
The to-be-solved technical problem of the utility model is to provide a high-voltage inverter cascade type power unit's that communication ability is strong communication circuit.
In order to solve the technical problem, the utility model adopts the technical scheme that the communication circuit of the cascade power unit of the high-voltage frequency converter comprises a main circuit and a control circuit, wherein the main circuit comprises three voltage output modules which are connected in a star or triangle; the voltage output module comprises a plurality of power units which are connected in series, the control circuit comprises a main control board, a voltage and current acquisition board and a data conversion board, the voltage output module comprises a data acquisition board, and the data acquisition board is in communication connection with the power units of the voltage output module; the main control board is respectively in communication connection with the data conversion board and the data acquisition board; the data conversion board is in communication connection with the data acquisition board and the voltage and current acquisition board of each voltage output module.
In the communication circuit, the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP; the data acquisition board comprises an FPGA processor, a plurality of optical fiber interfaces, a plurality of main board interfaces and a third 485 interface, wherein the plurality of optical fiber interfaces, the plurality of main board interfaces and the third 485 interface are respectively connected with the FPGA processor; the first 485 interface of the data conversion board is in communication connection with the third 485 interfaces of all the data acquisition boards, and the second 485 interface is in communication connection with the 485 interface of the main control board and the PLC controller of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board.
In the communication circuit, the voltage output module comprises two data acquisition boards, and each data acquisition board comprises 5 optical fiber interfaces and 5 main board interfaces; the power units in the voltage output module are divided into two groups and are respectively connected with the two data acquisition boards.
In the communication circuit, after the optical fiber interface receives data, an analog quantity signal, a switching quantity signal and a real-time control signal are screened out, wherein the analog quantity signal and the switching quantity signal are sent to a data cache of the FPGA processor of the data acquisition board, and the real-time control signal is sent to the interface of the main control board.
The utility model discloses under the condition that the master control board is redesigned, the communication ability and the analog signal processing ability of master control board have been expanded.
[ description of the drawings ]
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a communication circuit block diagram of a cascaded power unit of a high-voltage inverter according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a data conversion board according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a data acquisition board according to an embodiment of the present invention.
Fig. 4 is a flowchart of a communication circuit of a cascaded power unit of a high-voltage inverter according to an embodiment of the present invention.
Fig. 5 is a flow chart of the serial port algorithm of the data acquisition board of the embodiment of the present invention.
[ detailed description of the invention ]
As shown in fig. 1, the embodiment of the utility model provides a high-voltage inverter includes main circuit and control circuit, and the main circuit includes U looks voltage output module, V looks voltage output module and W looks voltage output module, and three voltage output module can be star or triangular connection, and every voltage output module is including 9 high voltage power unit and two data acquisition boards that concatenate, and 9 high voltage power unit divide into two sets ofly, respectively with two data acquisition board communication connection.
The control circuit comprises a main control board, a voltage and current (analog quantity) acquisition board and a data conversion board, wherein the main control board is respectively in communication connection with the data conversion board and the data acquisition board. The data conversion board is in communication connection with the data acquisition board and the voltage and current (analog quantity) acquisition board of each voltage output module.
As shown in fig. 3, the data conversion board includes a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface. The analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP processor.
As shown in fig. 2 and fig. 1, the data acquisition board includes an FPGA processor, 5 optical fiber interfaces, a motherboard interface, and a 485 interface, and the 5 optical fiber interfaces, the motherboard interface, and the 485 interface are respectively connected to the FPGA processor. The first 485 interfaces of the data conversion board are in communication connection with the 485 interfaces of all the data acquisition boards, and the second 485 interfaces of the data conversion board are in communication connection with the 485 interfaces of the main control board and the PLC of the high-voltage frequency converter. The analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface of the data conversion board is in communication connection with the voltage and current acquisition board.
As shown in fig. 4, 6 serial ports (5 fiber interfaces and 485 interfaces) of the data acquisition board are programmed by using the FPGA processor, and real-time reception and data decoding of 27 paths of 2MBPS serial fiber signals are completed by the joint work of the 6 FPGA processors, and the FPGA caches the high-resolution real-time data signals for 15 seconds.
The optical fiber interface comprises a 2Mbps serial communication interface module, and 5 optical fiber interfaces form 52 Mbps serial ports.
The 485 interface of the data acquisition board comprises 1 115200Bps communication module, and 1 115200Bps communication serial port is formed.
The FPGA processor comprises a data decoding module, a data screening module and a baud rate generation/baud rate clock capturing module.
The FPGA processor comprises a 15-second first-in first-out data caching module. The 15-second first-in first-out data caching module is used by an 115200Bps serial port and used for caching high-speed data streams, and high-resolution running data before and after a fault can be recorded.
The FPGA processor contains an address selection program to use multiple hardware carriers in parallel.
The FPGA processor comprises a data checking module and a digital anti-interference module which are respectively used for 6 serial ports.
Fig. 4 includes 6 communication serial ports, where serial ports 1 to 5 are 2M baud rate communication serial ports, and correspond to 5 optical fiber interfaces of the data acquisition board, and they use the same hardware logic code, and belong to hardware logic replication; the serial port 6 is a low-speed communication serial port with a rate of 115200 baud and corresponds to a 485 interface of the data acquisition board.
After receiving the data, the serial ports 1-5 screen out analog quantity signals, switching quantity signals and real-time control signals, wherein the analog quantity signals and the switching quantity signals are sent to a data cache of the FPGA processor, and the real-time control signals are sent to a main control board interface.
The data cache is divided into a real-time cache and a fault cache in the FPGA, the real-time cache only records currently received data, and the data are refreshed after each group of new data is received; the failure cache is to cache data 10 seconds before failure (500 sets) and data 5 seconds after failure (250 sets), the data is stored in a first-in first-out mode, and the cache resolution is 20 milliseconds. The fault cache uses the RAM block of the FPGA processor to construct an annular data buffer area, and when a fault command sent by the data conversion plate is received by the serial port 6 (485 interface of the data acquisition plate), the annular data buffer area stops updating, and fault cache data can be read.
The serial port 6 (485 interface of the data acquisition board) is used as a bridge for accessing the cache of the data acquisition board by external equipment, and the serial port 6 (485 interface of the data acquisition board) is connected with the data conversion board; the serial port 6 (485 interface of the data acquisition board) only accesses the real-time cache in the normal operation state, reads the real-time operation data and transmits the real-time operation data to the data conversion board, and after the serial port 6 receives a fault command transmitted by the data conversion board, the serial port 6 accesses the fault data cache, reads the data of 10 seconds before the fault and 5 seconds after the fault and transmits the data to the data conversion board.
And (3) skipping from the normal work of the high-voltage frequency converter to the fault state:
1. under a normal working state, the main control board sends a control signal to the high-voltage power unit through the optical fiber to control the high-voltage power unit to work, the high-voltage power unit sends data to the data acquisition board through the optical fiber, and the data acquisition board distributes a signal back to the main control board and the data conversion board;
2. the fault detection has a plurality of detection points, including that a high-voltage power unit reports faults, a main control board reports faults and a data conversion board reports faults, the faults are finally collected and sent to the data conversion board, the data conversion board sends a fault command to the data acquisition board in real time through a 485 interface, the refreshing of a fault cache is stopped, and fault data of 5 seconds before and after the fault is sent to the data conversion board, so that a worker can conveniently find out the faults.
FIG. 5 is the basic hardware logic of the serial port in the algorithm of FIG. 4:
serial signals are input through an IO port, firstly, oscillation pulses of rising edges and falling edges are cut off through digital anti-interference filtering, and the signals are guaranteed to be clean;
the filtered signals enter a baud rate clock edge capturing and baud rate clock synchronizing module, wherein baud rate clock alignment is carried out once every time a frame of signals is received, and serial port communication clock error accumulation is eliminated;
completing receiving through byte counting and data frame counting, and waiting for the arrival of a next frame signal;
signals received by the serial port are stored in a cache, the serial port logic reads the cache and checks/judges data in the cache, and if a fault command exists, the real-time cache and the fault cache are classified
The serial port works in a half-duplex mode, returns a frame of signal as a response when receiving a frame of signal, and does not send data when receiving the frame of signal;
the serial port finishes the transmission of one frame through byte counting and data frame counting in a transmission state.
The utility model discloses the data conversion board of above embodiment is the replenishment to the main control board function, under the condition that the main control board is not redesigned, has expanded the communication ability and the analog signal processing ability of main control board.
The utility model discloses communication circuit of above embodiment has solved the difficult problem of high-voltage inverter real-time data signal acquisition. The method comprises the following steps of (1) using 6 data acquisition boards consisting of 6 FPGA processors to acquire real-time state data of 27 three-phase cascade units, wherein star connection or triangular connection can be adopted, and the communication rate is 78 microseconds and the delay rate is 2 Mbps; the built-in digital filter/data cache has strong anti-interference capability and achieves higher communication quality with lower cost.
The utility model discloses the multi-serial ports real-time communication circuit based on FPGA technique of above embodiment can look over each high-voltage power unit's running state on line through PLC's touch-sensitive screen, and the system is more intelligent, has greatly improved work efficiency, has alleviateed field work personnel's burden.
Claims (3)
1. A communication circuit of a cascaded power unit of a high-voltage frequency converter comprises a main circuit and a control circuit, wherein the main circuit comprises three voltage output modules which are connected in a star or triangle manner; the voltage output module comprises a plurality of power units which are connected in series, and the control circuit comprises a main control board and a voltage and current acquisition board and is characterized in that the control circuit comprises a data conversion board, the voltage output module comprises a data acquisition board, and the data acquisition board is in communication connection with the power units of the voltage output module; the main control board is respectively in communication connection with the data conversion board and the data acquisition board; the data conversion board is in communication connection with the data acquisition board and the voltage and current acquisition board of each voltage output module.
2. The communication circuit according to claim 1, wherein the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP; the data acquisition board comprises an FPGA processor, a plurality of optical fiber interfaces, a plurality of main board interfaces and a third 485 interface, wherein the plurality of optical fiber interfaces, the main board interfaces and the third 485 interface are respectively connected with the FPGA processor; the first 485 interface of the data conversion board is in communication connection with the third 485 interfaces of all the data acquisition boards, and the second 485 interface is in communication connection with the 485 interface of the main control board and the PLC controller of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board.
3. The communication circuit of claim 2, wherein the voltage output module comprises two of said data acquisition boards, the data acquisition boards comprising 5 of said fiber optic interfaces; the power units in the voltage output module are divided into two groups and are respectively connected with the two data acquisition boards.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922462790.6U CN210924901U (en) | 2019-12-31 | 2019-12-31 | Communication circuit of cascaded power unit of high-voltage frequency converter |
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| CN201922462790.6U CN210924901U (en) | 2019-12-31 | 2019-12-31 | Communication circuit of cascaded power unit of high-voltage frequency converter |
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| CN210924901U true CN210924901U (en) | 2020-07-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111145529A (en) * | 2019-12-31 | 2020-05-12 | 深圳市库马克新技术股份有限公司 | Communication method of cascaded power unit of high-voltage frequency converter |
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2019
- 2019-12-31 CN CN201922462790.6U patent/CN210924901U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111145529A (en) * | 2019-12-31 | 2020-05-12 | 深圳市库马克新技术股份有限公司 | Communication method of cascaded power unit of high-voltage frequency converter |
| CN111145529B (en) * | 2019-12-31 | 2023-10-13 | 深圳库马克科技有限公司 | Communication method of cascade power unit of high-voltage frequency converter |
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Effective date of registration: 20230120 Address after: 518000 3F, kumak building, Dongzhou community, Guangming Street, Guangming District, Shenzhen, Guangdong Patentee after: Shenzhen kumak Technology Co.,Ltd. Address before: 518000 706, North block, Tairan Cangsong building, Tairan 6th Road, Shatou street, Futian District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Cumark New Technology Co.,Ltd. |
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