CN210955476U - Communication circuit of high-voltage frequency converter power unit - Google Patents
Communication circuit of high-voltage frequency converter power unit Download PDFInfo
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- CN210955476U CN210955476U CN201922472468.1U CN201922472468U CN210955476U CN 210955476 U CN210955476 U CN 210955476U CN 201922472468 U CN201922472468 U CN 201922472468U CN 210955476 U CN210955476 U CN 210955476U
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Abstract
The utility model discloses a communication circuit of high-voltage inverter power unit, which comprises a main control board and a plurality of unit control boards of power units, wherein each unit control board comprises a PWM core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives a control signal of the main control board; the data acquisition device comprises a data conversion board and a data acquisition board, wherein a main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control panel is connected with the optical fiber input interface of the data acquisition panel. The utility model discloses a communication speed is fast, and data transmission gauge height to the communication ability and the analog signal processing ability of main control board have been expanded.
Description
[ technical field ]
The utility model relates to a high-voltage inverter especially relates to a high-voltage inverter power unit's communication circuit.
[ background art ]
The cascade high-voltage frequency converter has the advantages that due to the fact that the number of power units is large, the operating voltage is high, the requirement on insulation is high, the safety requirement cannot be met in the traditional communication mode, and the communication speed is low and the quality is poor in the high-voltage strong interference environment.
The bus type optical fiber communication is used for connecting a power unit and a main control board of the high-voltage frequency converter and transmitting a control signal and a feedback signal, and although the anti-interference problem is solved, the bus type communication optical fiber communication speed is low and the data transmission quantity is low; and when the system has operation faults, the tracking record cannot be carried out, so that inconvenience is brought to troubleshooting. The bus type optical fiber communication system comprises a main control board and a plurality of power units, wherein a group of optical fibers are connected in series to form a linear network, the plurality of units are multiplexed in a time-sharing manner, the performance is insufficient during real-time data processing, and the communication capacity is poor.
[ summary of the invention ]
The to-be-solved technical problem of the utility model is to provide a high-voltage inverter power unit's that communication ability is strong communication circuit.
In order to solve the technical problem, the utility model adopts the technical scheme that a communication circuit of a high-voltage inverter power unit comprises a main control board and a plurality of unit control boards of the power unit, wherein each unit control board comprises a PWM (pulse width modulation) core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface, and the driving and feedback circuit, the information acquisition circuit, the optical fiber input interface and the optical fiber output interface are respectively connected with the PWM core circuit; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives a control signal of the main control board; the data acquisition device comprises a data conversion board and a data acquisition board, wherein a main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control panel is connected with the optical fiber input interface of the data acquisition panel.
In the communication circuit, the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP; the data acquisition board comprises an FPGA processor, a plurality of optical fiber input interfaces, a plurality of optical fiber output interfaces, a main board interface and a third 485 interface, wherein the optical fiber input interfaces, the main board interface and the third 485 interface are respectively connected with the FPGA processor; the optical fiber output interface is internally connected with a control signal switching pin of the mainboard interface and is externally connected with an optical fiber input interface of the unit control panel; the first 485 interface of the data conversion board is in communication connection with the third 485 interface of the data acquisition board, and the second 485 interface is in communication connection with the 485 interface of the main control board and the PLC of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board of the high-voltage frequency converter.
The utility model adopts a high-speed communication circuit and a high-speed optical fiber interface for the output of the unit control panel, which has fast communication speed and high data transmission quantity; the data conversion board is a supplement to the functions of the main control board, and under the condition that the main control board is not redesigned, the communication capability and the analog signal processing capability of the main control board are expanded.
[ description of the drawings ]
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a communication circuit block diagram of a cascaded power unit of a high-voltage inverter according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a data conversion board according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a data acquisition board according to an embodiment of the present invention.
Fig. 4 is a schematic block diagram of a unit control board according to an embodiment of the present invention.
Fig. 5 is a flowchart of a communication circuit of a cascaded power unit of a high-voltage inverter according to an embodiment of the present invention.
Fig. 6 is a flow chart of the serial port algorithm of the data acquisition board of the embodiment of the present invention.
[ detailed description of the invention ]
As shown in fig. 1, the embodiment of the present invention provides a high-voltage inverter including a main circuit and a control circuit.
The main circuit comprises a U-phase voltage output module, a V-phase voltage output module and a W-phase voltage output module, the three voltage output modules can be in star or triangular connection, each voltage output module comprises 9 high-voltage power units and two data acquisition boards which are connected in series, and the 9 high-voltage power units are divided into two groups and are respectively in communication connection with the two data acquisition boards.
As shown in fig. 4, the unit control board is built in the high-voltage power unit, and includes a PWM core circuit using a CPLD processor, a high-speed communication circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface, and an optical fiber output interface. The driving and feedback circuit, the information acquisition circuit and the optical fiber input interface are respectively connected with the PWM core circuit. The optical fiber output interface is a high-speed optical fiber interface, the optical fiber output interface is connected with the PWM core circuit through a high-speed communication circuit, the high-speed communication circuit adopts an STM32 single chip microcomputer, an STM32 single chip microcomputer serial port, and the highest communication speed of 4MBPS can be achieved. In this embodiment, the communication rate is 2MBPS, with data refreshed every 76 microseconds. The information acquisition circuit comprises a voltage acquisition circuit, a temperature acquisition circuit and a fault signal acquisition circuit.
The control circuit comprises a main control board, a voltage and current (analog quantity) acquisition board and a data conversion board, wherein the main control board is respectively in communication connection with the data conversion board and the data acquisition board. The data conversion board is in communication connection with the data acquisition board and the voltage and current (analog quantity) acquisition board of each voltage output module.
As shown in fig. 3, the data conversion board includes a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface. The analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP processor.
As shown in fig. 2 and fig. 1, the data acquisition board includes an FPGA processor, 5 optical fiber input interfaces, 5 optical fiber output interfaces, a motherboard interface, and a 485 interface, and the 5 optical fiber input interfaces, the motherboard interface, and the 485 interface are respectively connected to the FPGA processor. The first 485 interfaces of the data conversion board are in communication connection with the 485 interfaces of all the data acquisition boards, and the second 485 interfaces of the data conversion board are in communication connection with the 485 interfaces of the main control board and the PLC of the high-voltage frequency converter. The analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface of the data conversion board is in communication connection with the voltage and current acquisition board. The 5 optical fiber output interfaces of the data acquisition board are internally connected with the control signal switching pins of the main board interface and externally connected with the optical fiber input interfaces of the unit control board, and control signals of the power unit, which are sent by the main control board, are forwarded to the unit control board.
As shown in fig. 5, 6 serial ports (5 fiber input interfaces and 485 interfaces) of the data acquisition board are programmed by using the FPGA processor, and real-time reception and data decoding of 27 paths of 2MBPS serial fiber signals are completed by the joint work of the 6 FPGA processors, and the FPGA caches the high-resolution real-time data signals for 15 seconds.
The optical fiber input interface comprises a 2Mbps serial communication interface module, and 5 optical fiber input interfaces form 52 Mbps serial ports.
The 485 interface of the data acquisition board comprises 1 115200Bps communication module, and 1 115200Bps communication serial port is formed.
The FPGA processor comprises a data decoding module, a data screening module and a baud rate generation/baud rate clock capturing module.
The FPGA processor comprises a 15-second first-in first-out data caching module. The 15-second first-in first-out data caching module is used by an 115200Bps serial port and used for caching high-speed data streams, and high-resolution running data before and after a fault can be recorded.
The FPGA processor contains an address selection program to use multiple hardware carriers in parallel.
The FPGA processor comprises a data checking module and a digital anti-interference module which are respectively used for 6 serial ports.
Fig. 5 includes 6 communication serial ports, where serial ports 1 to 5 are 2M baud rate communication serial ports, and correspond to 5 optical fiber input interfaces of the data acquisition board, and they use the same hardware logic code, and belong to hardware logic replication; the serial port 6 is a low-speed communication serial port with a rate of 115200 baud and corresponds to a 485 interface of the data acquisition board.
After receiving the data, the serial ports 1-5 screen out analog quantity signals, switching quantity signals and real-time control signals, wherein the analog quantity signals and the switching quantity signals are sent to a data cache of the FPGA processor, and the real-time control signals are sent to a main control board interface.
The data cache is divided into a real-time cache and a fault cache in the FPGA, the real-time cache only records currently received data, and the data are refreshed after each group of new data is received; the failure cache is to cache data 10 seconds before failure (500 sets) and data 5 seconds after failure (250 sets), the data is stored in a first-in first-out mode, and the cache resolution is 20 milliseconds. The fault cache uses the RAM block of the FPGA processor to construct an annular data buffer area, and when a fault command sent by the data conversion plate is received by the serial port 6 (485 interface of the data acquisition plate), the annular data buffer area stops updating, and fault cache data can be read.
The serial port 6 (485 interface of the data acquisition board) is used as a bridge for accessing the cache of the data acquisition board by external equipment, and the serial port 6 (485 interface of the data acquisition board) is connected with the data conversion board; the serial port 6 (485 interface of the data acquisition board) only accesses the real-time cache in the normal operation state, reads the real-time operation data and transmits the real-time operation data to the data conversion board, and after the serial port 6 receives a fault command transmitted by the data conversion board, the serial port 6 accesses the fault data cache, reads the data of 10 seconds before the fault and 5 seconds after the fault and transmits the data to the data conversion board.
And (3) skipping from the normal work of the high-voltage frequency converter to the fault state:
1. under a normal working state, the main control board sends a control signal to the high-voltage power unit to control the high-voltage power unit to work, the high-voltage power unit sends data to the data acquisition board through the optical fiber, and the data acquisition board sends a signal back to the main control board and the data conversion board;
2. the fault detection has a plurality of detection points, including unit control board reporting fault, main control board reporting fault and data conversion board reporting fault, these faults are collected and sent to the data conversion board finally, the data conversion board sends fault command to the data acquisition board through 485 interface in real time, and stops the refreshing of fault cache, and sends fault data of 5 seconds after 10 seconds before the fault to the data conversion board, and it is convenient for the staff to troubleshoot the fault.
FIG. 6 is the basic hardware logic of the serial port in the algorithm of FIG. 5:
serial signals are input through an IO port, firstly, oscillation pulses of rising edges and falling edges are cut off through digital anti-interference filtering, and the signals are guaranteed to be clean;
the filtered signals enter a baud rate clock edge capturing and baud rate clock synchronizing module, wherein baud rate clock alignment is carried out once every time a frame of signals is received, and serial port communication clock error accumulation is eliminated;
completing receiving through byte counting and data frame counting, and waiting for the arrival of a next frame signal;
signals received by the serial port are stored in a cache, the serial port logic reads the cache and checks/judges data in the cache, and if a fault command exists, the real-time cache and the fault cache are classified
The serial port works in a half-duplex mode, returns a frame of signal as a response when receiving a frame of signal, and does not send data when receiving the frame of signal;
the serial port finishes the transmission of one frame through byte counting and data frame counting in a transmission state.
The output of the unit control board of the above embodiment of the present invention adopts a high-speed communication circuit and a high-speed optical fiber interface, the communication speed is fast, and the data transmission amount is high; the data conversion board is a supplement to the functions of the main control board, and under the condition that the main control board is not redesigned, the communication capability and the analog signal processing capability of the main control board are expanded.
The utility model discloses communication circuit of above embodiment has solved the difficult problem of high-voltage inverter real-time data signal acquisition. The method comprises the following steps of (1) using 6 data acquisition boards consisting of 6 FPGA processors to acquire real-time state data of 27 three-phase cascade units, wherein star connection or triangular connection can be adopted, and the communication rate is 78 microseconds and the delay rate is 2 Mbps; the built-in digital filter/data cache has strong anti-interference capability and achieves higher communication quality with lower cost.
The utility model discloses the multi-serial ports real-time communication circuit based on FPGA technique of above embodiment can look over each high-voltage power unit's running state on line through PLC's touch-sensitive screen, and the system is more intelligent, has greatly improved work efficiency, has alleviateed field work personnel's burden.
Claims (2)
1. A communication circuit of a power unit of a high-voltage frequency converter comprises a main control board and a plurality of unit control boards of the power unit, wherein each unit control board comprises a PWM (pulse-width modulation) core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface, and the driving and feedback circuit, the information acquisition circuit, the optical fiber input interface and the optical fiber output interface are respectively connected with the PWM core circuit; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives a control signal of the main control board; the device is characterized by comprising a data conversion board and a data acquisition board, wherein the main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control panel is connected with the optical fiber input interface of the data acquisition panel.
2. The communication circuit according to claim 1, wherein the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP; the data acquisition board comprises an FPGA processor, a plurality of optical fiber input interfaces, a plurality of optical fiber output interfaces, a main board interface and a third 485 interface, wherein the optical fiber input interfaces, the main board interface and the third 485 interface are respectively connected with the FPGA processor; the optical fiber output interface is internally connected with a control signal switching pin of the mainboard interface and is externally connected with an optical fiber input interface of the unit control panel; the first 485 interface of the data conversion board is in communication connection with the third 485 interface of the data acquisition board, and the second 485 interface is in communication connection with the 485 interface of the main control board and the PLC of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog quantity input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board of the high-voltage frequency converter.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922472468.1U CN210955476U (en) | 2019-12-31 | 2019-12-31 | Communication circuit of high-voltage frequency converter power unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922472468.1U CN210955476U (en) | 2019-12-31 | 2019-12-31 | Communication circuit of high-voltage frequency converter power unit |
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| CN210955476U true CN210955476U (en) | 2020-07-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111145530A (en) * | 2019-12-31 | 2020-05-12 | 深圳市库马克新技术股份有限公司 | Communication method of high-voltage frequency converter power unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111145530A (en) * | 2019-12-31 | 2020-05-12 | 深圳市库马克新技术股份有限公司 | Communication method of high-voltage frequency converter power unit |
| CN111145530B (en) * | 2019-12-31 | 2023-10-13 | 深圳库马克科技有限公司 | Communication method of high-voltage frequency converter power unit |
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Effective date of registration: 20230118 Address after: 518000 3F, kumak building, Dongzhou community, Guangming Street, Guangming District, Shenzhen, Guangdong Patentee after: Shenzhen kumak Technology Co.,Ltd. Address before: 518000 706, North block, Tairan Cangsong building, Tairan 6th Road, Shatou street, Futian District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Cumark New Technology Co.,Ltd. |
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