CN111145530B - Communication method of high-voltage frequency converter power unit - Google Patents
Communication method of high-voltage frequency converter power unit Download PDFInfo
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- CN111145530B CN111145530B CN201911407695.4A CN201911407695A CN111145530B CN 111145530 B CN111145530 B CN 111145530B CN 201911407695 A CN201911407695 A CN 201911407695A CN 111145530 B CN111145530 B CN 111145530B
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C23/00—Non-electrical signal transmission systems, e.g. optical systems
- G08C23/06—Non-electrical signal transmission systems, e.g. optical systems through light guides, e.g. optical fibres
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
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- Optical Communication System (AREA)
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Abstract
The invention discloses a communication method of a power unit of a high-voltage frequency converter, which comprises a main control board and a unit control board of a plurality of power units, wherein the unit control board comprises a PWM core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives control signals of the main control board; the system comprises a data conversion board and a data acquisition board, wherein the main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control board is connected with the optical fiber input interface of the data acquisition board. The invention has the advantages of high communication speed and high data transmission quantity, and expands the communication capacity and analog signal processing capacity of the main control board.
Description
[ technical field ]
The invention relates to a high-voltage frequency converter, in particular to a communication method of a power unit of the high-voltage frequency converter.
[ background Art ]
The cascade high-voltage frequency converter has the advantages that the number of power units is large, the operation voltage is high, the insulation requirement is high, the traditional communication mode is difficult to reach the safety requirement, and the communication speed is low and the quality is poor under the high-pressure interference environment.
The bus type optical fiber communication is used for connecting the power unit of the high-voltage frequency converter with the main control board and transmitting control signals and feedback signals, and the bus type optical fiber communication has the advantages that although the anti-interference problem is solved, the bus type optical fiber communication speed is low, and the data transmission quantity is low; and when the system has operation faults, the record cannot be tracked, and inconvenience is brought to fault investigation. The bus type optical fiber communication, the main control board and the plurality of power units are connected in series to form a linear network through a group of optical fibers, the plurality of units are multiplexed in a time-sharing mode, the performance is insufficient during real-time data processing, and the communication capability is poor.
[ summary of the invention ]
The technical problem to be solved by the invention is to provide a communication method of a high-voltage frequency converter power unit with strong communication capability.
In order to solve the technical problem, the technical scheme adopted by the invention is that the communication method of the high-voltage frequency converter power unit comprises a main control board and a unit control board of a plurality of power units, wherein the unit control board comprises a PWM core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface, and the driving and feedback circuit, the information acquisition circuit, the optical fiber input interface and the optical fiber output interface are respectively connected with the PWM core circuit; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives control signals of the main control board; the system comprises a data conversion board and a data acquisition board, wherein the main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control board is connected with the optical fiber input interface of the data acquisition board.
In the communication method, in the working state, the main control board sends a control signal to the unit control board to control the power unit to work, the unit control board sends data to the data acquisition board, and the data acquisition board distributes signals to the main control board and the data conversion board; under the fault state, no matter whether the unit control board reports the fault, the main control board reports the fault or the data conversion board reports the fault, the information of the reported fault is gathered to the data conversion board, the data conversion board sends a fault command to the data acquisition board in real time, and the data acquisition board is controlled to carry out fault processing.
In the communication method, the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP processor; the data acquisition board comprises an FPGA processor, a plurality of optical fiber input interfaces, a plurality of optical fiber output interfaces, a main board interface and a third 485 interface, wherein the optical fiber input interfaces, the main board interface and the third 485 interface are respectively connected with the FPGA processor; the optical fiber output interface is connected with a control signal transfer pin of the main board interface in an inscription manner, and is externally connected with an optical fiber input interface of the unit control board; the first 485 interface of the data conversion plate is in communication connection with the third 485 interface of the data acquisition plate, and the second 485 interface is in communication connection with the 485 interface of the main control plate and the PLC controller of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board of the high-voltage frequency converter.
According to the communication method, the FPGA processor of the data acquisition board comprises a real-time data buffer and a fault data buffer, after the third 485 interface of the data acquisition board receives a fault command sent by the data conversion board, the fault data buffer stops updating, and the third 485 interface reads data before and after the fault and forwards the fault data to the data conversion board.
According to the communication method, after the optical fiber input interface of the data acquisition board receives data, analog signals, switching value signals and real-time control signals are screened out, wherein the analog signals and the switching value signals are sent to the data cache of the FPGA processor of the data acquisition board, and the real-time control signals are sent to the interface of the main control board.
According to the communication method, the optical fiber input interface of the data acquisition board is used as a serial port, and the working process comprises the following steps:
601 The serial signal is input through the IO port, and the oscillation pulses of the rising edge and the falling edge are sheared off through digital anti-interference filtering, so that the signal is ensured to be clean;
602 The filtered signals enter a baud rate clock edge capturing and baud rate clock synchronizing module, and once baud rate clock alignment is carried out on each frame of signals received, so that error accumulation of serial communication clocks is eliminated;
603 After byte counting and data frame counting, waiting for the arrival of the next frame signal;
604 The serial port logic reads the cache and checks/judges the data in the cache, if the command fails, the real-time cache and the fault cache are classified;
605 The serial port works in a half duplex mode, and returns a frame of signal as a response when the serial port receives a frame of signal, and data is not transmitted when the serial port receives the frame of signal;
606 The serial port finishes the transmission of one frame after the byte count and the data frame count in the transmission state.
The output of the unit control board adopts a high-speed communication circuit and a high-speed optical fiber interface, so that the communication speed is high, and the data transmission quantity is high; the data conversion board is a supplement to the function of the main control board, and the communication capacity and the analog signal processing capacity of the main control board are expanded under the condition that the main control board is not redesigned.
[ description of the drawings ]
The invention will be described in further detail with reference to the drawings and the detailed description.
Fig. 1 is a block diagram of a communication circuit of a cascaded power cell of a high voltage inverter according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a data conversion board according to an embodiment of the invention.
Fig. 3 is a functional block diagram of a data acquisition board according to an embodiment of the present invention.
Fig. 4 is a schematic block diagram of a unit control board according to an embodiment of the present invention.
Fig. 5 is a flow chart of a communication method of a cascaded power cell of a high voltage inverter according to an embodiment of the present invention.
Fig. 6 is a flowchart of a serial port algorithm of a data acquisition board according to an embodiment of the present invention.
Detailed description of the preferred embodiments
As shown in fig. 1, the high-voltage frequency converter according to the embodiment of the invention comprises a main circuit and a control circuit.
The main circuit comprises a U-phase voltage output module, a V-phase voltage output module and a W-phase voltage output module, wherein the three voltage output modules can be in star-shaped or triangle-shaped connection, each voltage output module comprises 9 high-voltage power units and two data acquisition boards which are connected in series, and the 9 high-voltage power units are divided into two groups and are respectively in communication connection with the two data acquisition boards.
The high-voltage power unit is built in with a unit control board, as shown in fig. 4, and the unit control board comprises a PWM core circuit adopting a CPLD processor, a high-speed communication circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface. The driving and feedback circuit, the information acquisition circuit and the optical fiber input interface are respectively connected with the PWM core circuit. The optical fiber output interface is a high-speed optical fiber interface, the optical fiber output interface is connected with the PWM core circuit through a high-speed communication circuit, the high-speed communication circuit adopts an STM32 singlechip, and the serial port of the STM32 singlechip can reach 4MBPS communication rate at most. In this embodiment, the communication rate is 2MBPS, with data refreshed every 76 microseconds. The information acquisition circuit is provided with a voltage acquisition circuit, a temperature acquisition circuit and a fault signal acquisition circuit.
The control circuit comprises a main control board, a voltage and current (analog quantity) acquisition board and a data conversion board, wherein the main control board is respectively in communication connection with the data conversion board and the data acquisition board. The data conversion board is in communication connection with the data acquisition board and the voltage and current (analog quantity) acquisition board of each voltage output module.
As shown in fig. 3, the data conversion board includes a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface. The analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP processor.
As shown in fig. 2 and fig. 1, the data acquisition board includes an FPGA processor, 5 optical fiber input interfaces, 5 optical fiber output interfaces, a motherboard interface, and a 485 interface, where the 5 optical fiber input interfaces, the motherboard interface, and the 485 interface are respectively connected to the FPGA processor. The first 485 interface of the data conversion plate is in communication connection with the 485 interfaces of all the data acquisition plates, and the second 485 interface of the data conversion plate is in communication connection with the 485 interface of the main control plate and the PLC controller of the high-voltage frequency converter. The analog signal output interface of the data conversion board is in communication connection with the analog input interface of the main control board, and the analog signal acquisition interface of the data conversion board is in communication connection with the voltage and current acquisition board. The control signal transfer pins of the main board interface are connected in the 5 optical fiber output interfaces of the data acquisition board, the optical fiber input interfaces of the external unit control board transfer the control signals of the power unit sent by the main control board to the unit control board.
As shown in fig. 5, 6 serial ports (5 optical fiber input interfaces and 485 interfaces) of the data acquisition board are written by using the FPGA processor, and the real-time receiving and data decoding of 27 2MBPS serial optical fiber signals are completed by the joint work of the 6 FPGA processors, and the FPGA caches high-resolution real-time data signals for 15 seconds.
The optical fiber input interface comprises a 2Mbps serial communication port module, and 5 optical fiber input interfaces form 52 Mbps serial ports.
The 485 interface of the data acquisition board comprises 1 115200Bps communication module, and 1 115200Bps communication serial port is formed.
The FPGA processor comprises a data decoding module, a data screening module and a baud rate generation/baud rate clock capturing module.
The FPGA processor includes a 15 second first-in first-out data buffer module. The 15 second first-in first-out data buffer module is used for 115200Bps serial port to buffer high-speed data stream, and can record high-resolution operation data before and after failure.
The FPGA processor contains an address selection program to use multiple hardware carriers in parallel.
The FPGA processor comprises a data checking module and a digital anti-interference module which are respectively used for 6 paths of serial ports.
Fig. 5 includes 6 communication serial ports, wherein serial ports 1 to 5 are 2M baud rate communication serial ports, and correspond to 5 optical fiber input interfaces of the data acquisition board, which use the same hardware logic code and belong to hardware logic replication; the serial port 6 is a low-speed communication serial port with 115200 baud rate and corresponds to a 485 interface of the data acquisition board.
After the serial ports 1-5 receive the data, analog quantity signals, switching value signals and real-time control signals are screened out, wherein the analog quantity signals and the switching value signals are sent to a data buffer of an FPGA processor, and the real-time control signals are sent to a main control board interface.
The data cache is divided into a real-time cache and a fault cache in the FPGA, wherein the real-time cache only records currently received data, and the data is refreshed once a group of new data is received; the fault cache is to cache 10 seconds (500 groups) of data before the fault and 5 seconds (250 groups) of data after the fault, the data is stored in a first-in first-out mode, and the cache resolution is 20 milliseconds. The fault buffer uses RAM blocks of the FPGA processor to construct a ring data buffer, and when the fault command sent by the data conversion board is received by the serial port 6 (485 interface of the data acquisition board), the ring data buffer stops updating and can read the fault buffer data.
The serial port 6 (485 interface of the data acquisition board) is used as a bridge for external equipment to access the cache of the data acquisition board, and the serial port 6 (485 interface of the data acquisition board) is connected with the data conversion board; under the normal operation state, the serial port 6 (485 interface of the data acquisition board) only accesses the real-time buffer, reads real-time operation data and sends the real-time operation data to the data conversion board, and when the serial port 6 receives a fault command sent by the data conversion board, the serial port 6 accesses the fault data buffer, reads data 10 seconds before the fault and 5 seconds after the fault, and forwards the data to the data conversion board.
Jump of normal operation of the high voltage frequency converter to fault state:
1. in a normal working state, the main control board sends a control signal to the high-voltage power unit to control the high-voltage power unit to work, the high-voltage power unit sends data to the data acquisition board through the optical fiber, and the data acquisition board distributes signals to the main control board and the data conversion board;
2. the fault detection has a plurality of detection points, including unit control board fault report, main control board fault report and data conversion board fault report, these faults are finally collected and sent to the data conversion board, and the data conversion board sends the fault command to the data acquisition board through 485 interface in real time to stop the refreshing of fault buffer memory, send the fault data of 10 seconds before the fault and 5 seconds after the fault to the data conversion board, make things convenient for staff's troubleshooting.
FIG. 6 is the basic hardware logic of the serial port in the algorithm of FIG. 5:
serial signals are input through an IO port, and the oscillation pulses of the rising edge and the falling edge are sheared off through digital anti-interference filtering, so that the cleanliness of the signals is ensured;
the filtered signals enter a baud rate clock edge capturing and baud rate clock synchronizing module, and baud rate clock alignment is carried out once every time a frame of signals is received, so that error accumulation of a serial port communication clock is eliminated;
the receiving is completed through byte counting and data frame counting, and the next frame signal arrives;
the serial port logic reads the buffer memory and checks/command judges the data in the buffer memory, if the command fails, the real-time buffer memory and the fault buffer memory are classified
The serial port works in a half duplex mode, and returns a frame of signal as a response when the serial port receives a frame of signal, and data is not transmitted when the serial port receives the frame of signal;
and the serial port finishes the transmission of one frame after byte counting and data frame counting in the transmission state.
The output of the unit control board of the embodiment of the invention adopts a high-speed communication circuit and a high-speed optical fiber interface, so that the communication speed is high and the data transmission quantity is high; the data conversion board is a supplement to the function of the main control board, and the communication capacity and the analog signal processing capacity of the main control board are expanded under the condition that the main control board is not redesigned.
The communication method of the embodiment of the invention solves the difficult problem of real-time data signal acquisition of the high-voltage frequency converter. The three-phase cascade control system comprises a three-phase cascade control unit, a three-phase cascade control unit and a three-phase cascade control unit, wherein the three-phase cascade control unit is provided with a data acquisition board consisting of 6 FPGA processors, and the three-phase cascade control unit is used for acquiring real-time state data of 27 cascade control units, and can adopt star connection or triangle connection, and 78 microseconds low-delay 2Mbps communication rate; the built-in digital filter/data buffer has strong anti-interference capability, and achieves higher communication quality with lower cost.
According to the multi-serial port real-time communication method based on the FPGA technology, which is disclosed by the embodiment of the invention, the running state of each high-voltage power unit can be checked on line through the touch screen of the PLC, so that the system is more intelligent, the working efficiency is greatly improved, and the burden of on-site workers is reduced.
Claims (4)
1. The communication method of the power unit of the high-voltage frequency converter comprises a main control board and unit control boards of a plurality of power units, wherein the unit control boards comprise a PWM core circuit, a driving and feedback circuit, an information acquisition circuit, an optical fiber input interface and an optical fiber output interface, and the driving and feedback circuit, the information acquisition circuit, the optical fiber input interface and the optical fiber output interface are respectively connected with the PWM core circuit; the unit control board is in communication connection with the main control board through an optical fiber input interface and receives control signals of the main control board; the device is characterized by comprising a data conversion board and a data acquisition board, wherein the main control board is in communication connection with the data conversion board; the data conversion board is in communication connection with the data acquisition board; the unit control board comprises a high-speed communication circuit, the optical fiber output interface is a high-speed optical fiber interface, and the optical fiber output interface is connected with the PWM core circuit through the high-speed communication circuit; the optical fiber output interface of the unit control board is connected with the optical fiber input interface of the data acquisition board; in the working state, the main control board sends a control signal to the unit control board to control the power unit to work, the unit control board sends data to the data acquisition board, and the data acquisition board distributes signals to the main control board and the data conversion board; under the fault state, no matter whether the unit control board reports the fault, the main control board reports the fault or the data conversion board reports the fault, the information of the reported fault is gathered to the data conversion board, the data conversion board sends a fault command to the data acquisition board in real time, and the data acquisition board is controlled to perform fault processing; the data acquisition board includes a plurality of optical fiber input interface, the optical fiber input interface of data acquisition board is as the serial ports, and the during operation includes following steps:
101 The serial signal is input through the IO port, and the oscillation pulses of the rising edge and the falling edge are sheared off through digital anti-interference filtering, so that the signal is ensured to be clean;
102 The filtered signals enter a baud rate clock edge capturing and baud rate clock synchronizing module, and once baud rate clock alignment is carried out on each frame of signals received, so that error accumulation of serial communication clocks is eliminated;
103 After byte counting and data frame counting, waiting for the arrival of the next frame signal;
104 The serial port logic reads the cache and checks/judges the data in the cache, if the command fails, the real-time cache and the fault cache are classified;
105 The serial port works in a half duplex mode, and returns a frame of signal as a response when the serial port receives a frame of signal, and data is not transmitted when the serial port receives the frame of signal;
106 The serial port finishes the transmission of one frame after the byte count and the data frame count in the transmission state.
2. The communication method of claim 1, wherein the data conversion board comprises a DSP processor, an analog signal acquisition interface, an analog signal output interface, a first 485 interface, and a second 485 interface; the analog signal acquisition interface, the analog signal output interface, the first 485 interface and the second 485 interface are respectively connected with the DSP processor; the data acquisition board comprises an FPGA processor, a plurality of optical fiber output interfaces, a main board interface and a third 485 interface, wherein the optical fiber input interface, the main board interface and the third 485 interface are respectively connected with the FPGA processor; the optical fiber output interface is connected with a control signal transfer pin of the main board interface in an inscription manner, and is externally connected with an optical fiber input interface of the unit control board; the first 485 interface of the data conversion plate is in communication connection with the third 485 interface of the data acquisition plate, and the second 485 interface is in communication connection with the 485 interface of the main control plate and the PLC controller of the high-voltage frequency converter; the analog signal output interface of the data conversion board is in communication connection with the analog input interface of the main control board, and the analog signal acquisition interface is in communication connection with the voltage and current acquisition board of the high-voltage frequency converter.
3. The communication method according to claim 2, wherein the FPGA processor of the data acquisition board includes a real-time data buffer and a fault data buffer, the fault data buffer stops updating after the third 485 interface of the data acquisition board receives the fault command sent from the data conversion board, and the third 485 interface reads the data before and after the fault and forwards the fault data to the data conversion board.
4. The communication method according to claim 2, wherein after the optical fiber input interface of the data acquisition board receives the data, analog signals, switching value signals and real-time control signals are screened out, wherein the analog signals and the switching value signals are sent to the data cache of the FPGA processor of the data acquisition board, and the real-time control signals are sent to the interface of the main control board.
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