CN205249231U - Realize criss -cross cross board of synchronous digital hierarchy high -order - Google Patents

Abstract

The utility model relates to a realize criss -cross cross board of synchronous digital hierarchy high -order, including power module, clock module, maintenance and management module, professional processing module, control module and communication module, power module is for the device power supply and monitor the voltage electric current state of each power, and communication module receiving host machine's intersection order is handed down to control module after analytic, control module receive alternately instruction and the judgement whether correct, carry out the cross processing if correctly will issue professional processing module to information alternately, the clock module is duplicated to 4 the tunnel after with the received clock multiplier, provides required reference clock, and maintenance and management module acquire the voltage current information of integrated circuit board, if any reporting the host computer unusually to close this board power, simultaneously this module still reports verison imformation, the information such as chip temperature and FPGA temperature alternately of this board to the host computer, and technological effect is, the high -order of having realized 640G intersection capacity and 40G 20G alternately, easy operation, it is accurate, real -time, steadily alternately to switch over.

Description

A kind of cross board of realizing SDH high-order intersection

Technical field

The utility model relates to a kind of fiber optic communication cross board, particularly a kind of cross board of realizing SDH high-order intersection.

Background technology

Fiber optic communication is because transmission capacity is large, loss is little, lightweight, volume is little, anti-electromagnetic interference capability is strong and the advantage such as good confidentiality, in an increasingly wide range of applications in communication, not only backbone network, Metropolitan Area Network (MAN) all adopt optical fibre transmission, and Access Network also generally adopts optical fiber realization to converge. The problem brought is thus, vast as the open sea optical-fiber network information carried out to the difficulty that technology intercepts and scout increasing, especially the in the situation that of large capacity access, realize while intersection, and be very large challenge to hardware circuit design.

Summary of the invention

In view of the problem of present technology existence, the utility model provides a kind of cross board that SDH high-order intersects of realizing, utilize cross chips to realize the cross-capacity of 640G × 640G, and the high-order that utilizes FPGA to realize 40G × 20G intersects, concrete technical scheme is, a kind of cross board of realizing SDH high-order intersection, comprise supply module, clock module, safeguard and administration module, Service Processing Module, six functional modules of control module and communication module, it is characterized in that: hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module is connected by parallel port is two-way with control module, control module is connected by I2C interface is two-way with communication module, control module is connected by serial ports is two-way with maintenance and administration module, maintenance and administration module are connected with communication module is two-way by SPI interface, also by 485 interfaces, 12C interface is connected with ZD connector is two-way, communication module is connected with ZD connector is two-way by LVDS interface, ZD connector sends 19.44M clock to clock module, and be connected by differential lines and Service Processing Module are two-way, described supply module comprises optically-coupled chip, DC/DC power module, digital power module, power supply chip, first business supply module uses DC/DC power module to obtain 12V power rail, re-use digital power module and obtain each required power rail of board, this digital power is supported the setting of electric sequence and power down order, and can the electric current and voltage state reporting of power supply be given and be safeguarded and administration module by PMBUS bus,

Power supply chip TPS74401 produces the power rail that does not need to configure power on and off order simultaneously, described communication module is made up of FPGA and FLASH, FLASH is the configuring chip of FPAG, be connected with FPGA is two-way by spi bus, FPGA receives the intersection instruction that host computer issues, after parsing, issue control module by I2C bus, also monitor communications status and the crossing condition of LVDS simultaneously, and to safeguarding and administration module real-time report monitoring state, described clock module is mainly composed in series by three chips, the 19.44M differential clocks being entered by ZD connector drives the single-ended clock of chip output 19.44M to second chip through first MLVDS, second chip is mainly responsible for filtering, debounce and the frequency multiplication of clock, the differential clocks of output 155.52M is given the 3rd chip, the clock of 155.52M is copied into 4 tunnels by the 3rd chip, 1 tunnel to the FPGA of communication module as with reference to clock, 3 tunnels to the FPGA of Service Processing Module as with reference to clock, the chip that described control module adopts is single-chip microcomputer, external interface has I2C interface, serial ports and parallel interface, single chip control module is communicated by letter with communication module by I2C interface, the interleaving route information that received communication module issues and balanced preemphasis information, communicate by letter with business module by parallel interface, the routing iinformation receiving and balanced preemphasis information configuration are arrived to Service Processing Module, and read the crossing condition of current business processing module by this port, communicate by letter with maintenance and administration module by serial ports, the monitor messages such as intersection errors number and cross chips temperature are reported and safeguarded and administration module, the chip that described maintenance and administration module adopt is ARM7, main external interface has I2C interface, RS485 interface and PMBUS interface, communicate by letter with supply module by PMBUS interface, read the electric current and voltage information of whole plate, control the power on and off order of each digital power module, be connected with ZD connector by I2C interface, in the time that cross chips excess Temperature or power module break down, warning information is reported to host computer, be connected with communication module by SPI interface, read the monitor message such as LVDS bus state and optical module luminous power that communication module reports, be connected with ZD connector by 485 buses, by its version information, the information reportings such as optical module luminous power and cross chips temperature are to host computer, described Service Processing Module comprises cross chips, FPGA, 2 × SFP+ optical module, 2 × sub-miniature A connector, cross chips is connected with control module by parallel interface, receive the intersection order that control module issues, after being received to 128 road 5G signal cross, ZD connector beams back ZD connector, and copy 8 road 5G signals wherein to FPGA, for poll, FPGA is connected with cross chips by 8 road SERDES, receive the 8 road 5G signals that copy from cross chips, intersect through high-order, again synthesize the SDH signal of two-way 10G and send by 2 road SFP+ optical modules,

High speed signal is by signal quality meeting variation after ZD connector, pass through parallel interface, control module can arrange equilibrium and the pre-emphasis parameters of cross chips, with conditioning signal quality, and is connected to high-speed oscilloscope and is checked the eye pattern of current demand signal by 2 road sub-miniature A connectors.

Technique effect of the present utility model is, realized the cross-capacity of 640G × 640G and the high-order of 40G × 20G and intersected, to complete intersection poll, simple to operate, intersect switch accurately, in real time, stable.

Brief description of the drawings

Fig. 1. be system module circuit block diagram of the present utility model.

Fig. 2. be supply module circuit block diagram of the present utility model.

Fig. 3. be communication module circuit block diagram of the present utility model.

Fig. 4 is clock module circuit block diagram of the present utility model.

Fig. 5. be Service Processing Module circuit block diagram of the present utility model.

Detailed description of the invention

As shown in Figure 1, system function division is six functional modules, supply module, communication module, control module, Service Processing Module, clock module and maintenance and administration module. hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module is connected by parallel port is two-way with control module, control module is connected by I2C interface is two-way with communication module, control module is connected by serial ports is two-way with maintenance and administration module, maintenance and administration module are connected with communication module is two-way by SPI interface, also by 485 interfaces, 12C interface is connected with ZD connector is two-way, communication module is connected with ZD connector is two-way by LVDS interface, ZD connector sends 19.44M clock to clock module, and be connected by differential lines and Service Processing Module are two-way,

System works main-process stream is that supply module is the electric current and voltage state that all power supplys were powered and monitored to all devices of board, to ensure the normal operation of board. Communication module receives by LVDS bus the intersection order that host computer issues, after parsing, be handed down to control module by I2C bus, control module first checks whether order is correct after receiving intersection instruction, if correctly carry out cross processing by parallel port configuration service processing module. Clock module is by the 19.44M line clock frequency multiplication receiving to 155.52M and copy as 4 tunnels, and 1 tunnel is to communication module, and 3 tunnels are to Service Processing Module, for they provide needed reference clock, to ensure the clock synchronous of system. Maintenance and administration module obtain the electric current and voltage information of whole plate power supply by PMBUS bus, report host computer, and close this plate power supply if electric current and voltage has extremely by I2C bus. This module also reports version information, cross chips temperature information and the FPGA temperature information etc. of this plate to host computer by 485 buses simultaneously.

As shown in Figure 2, described supply module comprises optically-coupled chip, DC/DC power module, digital power module, power supply chip, the unidirectional connection of optically-coupled chip DC/DC power module, 7 digital power modules of the unidirectional connection of DC/DC power module, obtain 7 required power rails of board, wherein 3.3V power rail connects the power rails that 2 two of power supply chips generations do not need to configure power on and off order. Supply module major function is that this plate is by 48V Power supply for board provides various required Voltage rails, supports hot plug, supports the real-time monitoring of voltage, electric current, can control the power on and off order of power supply. What hot plug was used is the PIM4328 hot plug module of Ericsson, except output 48V Voltage rails, the Voltage rails of 3.3V is also provided separately, other power supplys that ensured maintenance and administration module and board are isolated completely, even if the supply module of board breaks down like this, maintenance and administration module also can normally move, and read the electric current and voltage information of each power supply of board by PMBUS bus, after gathering, report host computer by IC2 bus, to locate fast fault, by controlling optocoupler TLP291, business supply module is turn-offed simultaneously. First business supply module uses the DC/DC power module EBVW020A0B641Z of GE to obtain 12V Voltage rails, the digital power module BMR464 and the BMR461 that re-use Ericsson obtain each required Voltage rails of board, this digital power module is supported the setting of electric sequence and power down order, and can the electric current and voltage state reporting of power supply be given and be safeguarded and administration module by PMBUS bus. In order to reduce the cost of board, used the LDO power supply chip TPS74401 generation of TI not need to configure power on and off order and the less Voltage rails of power consumption simultaneously.

As shown in Figure 3, described communication module is made up of FPGA and FLASH, with the two-way connection of configuration bus, the major function of communication module is to be handed down to control module after the intersection instruction of reception host computer is resolved, and reports the information such as communications status and crossing condition to maintenance and administration module simultaneously. The model of FPGA is the XC6SLX25 of XILINX, and the model of FLASH is M25P128, and configuration bus is spi bus. The reference clock that XC6SLX25 uses is from clock module, ensure the clock synchronous of system, XC6SLX25 receives the intersection instruction from host computer by LVDS bus, is handed down to control module, and reads the crossing condition after configuration by I2C bus after parsing by I2C bus. XC6SLX25 also monitors the communications status of LVDS simultaneously, and the intersection information that is issued and read back by contrast, judges that whether intersection is successful. The monitor messages such as LVDS communications status and crossing condition are reported and are safeguarded and administration module by spi bus.

As shown in Figure 4, described clock module is serially connected and is formed by DS176, SI5322 and tri-chips of SI5330, and clock module is mainly responsible for the FPGA of business module and the FPGA of communication module provides reference clock, to ensure the clock synchronous of system. The workflow of clock module is that the 19.44M differential clocks that backboard ZD connector enters drives the single-ended clock of chip DS176 output 19.44M to SI5322 chip through MLVDS, and SI5322 chip is mainly responsible for filtering, debounce and the frequency multiplication of clock. Clock is exported the differential clocks of 155.52M to clock chip SI5330 after SI5322 frequency multiplication, and the clock of 155.52M is copied into 4 tunnels by SI5330,1 tunnel to the FPGA of communication module as with reference to clock, 3 tunnels to the FPGA of Service Processing Module as with reference to clock.

The chip that control module adopts is single-chip microcomputer, and model is C8051F020, and main external interface is I2C interface, serial ports and parallel interface. The function that single chip control module mainly completes: communicate by letter with communication module by I2C interface (1), the interleaving route information that received communication module issues and balanced preemphasis information. (2) communicate by letter with Service Processing Module by parallel interface, after the routing iinformation receiving is resolved, be handed down to Service Processing Module, and read the crossing condition of current business processing module by this port. (3) communicate by letter with maintenance and administration module by serial ports, the monitor messages such as intersection errors number and cross chips temperature are reported and safeguarded and administration module.

The chip that maintenance and administration module adopt is ARM7, and model is LPC2378, and main external interface is I2C interface, RS485 interface, SPI interface and PMBUS interface. Safeguard and the power supply of administration module is independently, with other isolated from power, even like this other module for power supply it also can normally be worked extremely, and by PMBUS bus, abnormal information is read, be convenient to investigate fault. The function that ARM safeguards and administration module mainly completes: communicate by letter with power module by PMBUS interface (1), reads the electric current and voltage information of each power module, and by electric sequence and the power down order of this each power module of interface control. (2) be connected with backboard ZD connector by I2C interface, in the time that the cross chips excess Temperature of board or power module break down, by I2C interface, warning information reported to host computer. (3) communicate by letter with communication module by SPI interface, read the monitor message such as LVDS bus state and optical module luminous power that communication module reports. (4) be connected with backboard ZD connector by 485 interfaces, by information reportings such as the version information of board, optical module luminous power and cross chips temperature to host computer.

As shown in Figure 5, described Service Processing Module comprises cross chips, FPGA, SFP+ optical module, sub-miniature A connector, cross chips is connected with ZD connector is unidirectional by input port, cross chips is connected by parallel interface and control module are two-way, cross chips by delivery outlet with ZD connector, FPGA, sub-miniature A connector is unidirectional is connected, FPGA is connected with SFP+ optical module is unidirectional by SERDES. Cross chips model is VSC3144, FPGA model is XC7K325T, the function that Service Processing Module specifically completes is as follows: (1) cross chips (VSC3144) is connected with control module by parallel interface, receive the intersection order that control module issues, after being received to 128 road 5G signal cross, ZD connector beams back ZD connector, copy 8 road 5G signals wherein to FPGA, for poll simultaneously. (2) FPGA(XC7K325T) be connected with cross chips by SERDES, receive the 8 road 5G signals that copy from cross chips, intersect through high-order, again synthesize the signal of two-way 10G and send by SFP+ optical module. (3) high speed signal is by signal quality meeting variation after ZD connector, pass through parallel interface, control module can arrange equilibrium and the pre-emphasis parameters of cross chips, with conditioning signal quality, and is connected to high-speed oscilloscope and is checked the eye pattern of current demand signal by sub-miniature A connector.

Claims (1)

1. realize the cross board that SDH high-order intersects for one kind, comprise supply module, clock module, safeguard and administration module, Service Processing Module, six functional modules of control module and communication module, it is characterized in that: hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module is connected by parallel port is two-way with control module, control module is connected by I2C interface is two-way with communication module, control module is connected by serial ports is two-way with maintenance and administration module, maintenance and administration module are connected with communication module is two-way by SPI interface, also by 485 interfaces, 12C interface is connected with ZD connector is two-way, communication module is connected with ZD connector is two-way by LVDS interface, ZD connector sends 19.44M clock to clock module, and be connected by differential lines and Service Processing Module are two-way, described supply module comprises optically-coupled chip, DC/DC power module, digital power module, power supply chip, first business supply module uses DC/DC power module to obtain 12V power rail, re-use digital power module and obtain each required power rail of board, this digital power is supported the setting of electric sequence and power down order, and can the electric current and voltage state reporting of power supply be given and be safeguarded and administration module by PMBUS bus,

Power supply chip TPS74401 produces the power rail that does not need to configure power on and off order simultaneously, described communication module is made up of FPGA and FLASH, FLASH is the configuring chip of FPAG, be connected with FPGA is two-way by spi bus, FPGA receives the intersection instruction that host computer issues, after parsing, issue control module by I2C bus, also monitor communications status and the crossing condition of LVDS simultaneously, and to safeguarding and administration module real-time report monitoring state, described clock module is mainly composed in series by three chips, the 19.44M differential clocks being entered by ZD connector drives the single-ended clock of chip output 19.44M to second chip through first MLVDS, second chip is mainly responsible for filtering, debounce and the frequency multiplication of clock, the differential clocks of output 155.52M is given the 3rd chip, the clock of 155.52M is copied into 4 tunnels by the 3rd chip, 1 tunnel to the FPGA of communication module as with reference to clock, 3 tunnels to the FPGA of Service Processing Module as with reference to clock, the chip that described control module adopts is single-chip microcomputer, external interface has I2C interface, serial ports and parallel interface, single chip control module is communicated by letter with communication module by I2C interface, the interleaving route information that received communication module issues and balanced preemphasis information, communicate by letter with business module by parallel interface, the routing iinformation receiving and balanced preemphasis information configuration are arrived to Service Processing Module, and read the crossing condition of current business processing module by this port, communicate by letter with maintenance and administration module by serial ports, the monitor messages such as intersection errors number and cross chips temperature are reported and safeguarded and administration module, the chip that described maintenance and administration module adopt is ARM7, main external interface has I2C interface, RS485 interface and PMBUS interface, communicate by letter with supply module by PMBUS interface, read the electric current and voltage information of whole plate, control the power on and off order of each digital power module, be connected with ZD connector by I2C interface, in the time that cross chips excess Temperature or power module break down, warning information is reported to host computer, be connected with communication module by SPI interface, read the monitor message such as LVDS bus state and optical module luminous power that communication module reports, be connected with ZD connector by 485 buses, by its version information, the information reportings such as optical module luminous power and cross chips temperature are to host computer, described Service Processing Module comprises cross chips, FPGA, 2 × SFP+ optical module, 2 × sub-miniature A connector, cross chips is connected with control module by parallel interface, receive the intersection order that control module issues, after being received to 128 road 5G signal cross, ZD connector beams back ZD connector, and copy 8 road 5G signals wherein to FPGA, for poll, FPGA is connected with cross chips by 8 road SERDES, receive the 8 road 5G signals that copy from cross chips, intersect through high-order, again synthesize the SDH signal of two-way 10G and send by 2 road SFP+ optical modules,

High speed signal is by signal quality meeting variation after ZD connector, pass through parallel interface, control module can arrange equilibrium and the pre-emphasis parameters of cross chips, with conditioning signal quality, and is connected to high-speed oscilloscope and is checked the eye pattern of current demand signal by 2 road sub-miniature A connectors.