CN210669996U

CN210669996U - CMOS device

Info

Publication number: CN210669996U
Application number: CN201921267509.7U
Authority: CN
Inventors: 赵旭旭; 张薇; 邢康伟; 朱恒宇
Original assignee: Beijing Ruidaxin Integrated Circuit Design Co ltd
Current assignee: Beijing Ruidaxin Integrated Circuit Design Co ltd
Priority date: 2019-08-07
Filing date: 2019-08-07
Publication date: 2020-06-02
Anticipated expiration: 2029-08-07

Abstract

The utility model discloses a CMOS device, including first order single tube amplifier, second level single tube amplifier and phase inverter, wherein, grid among first order single tube amplifier and the second level single tube amplifier is eight corner ring shape bars structure and surrounds the drain electrode, source electrode among first order single tube amplifier and the second level single tube amplifier is located the grid is peripheral. The utility model discloses two single tube amplifiers all adopt the ring grid structure, can avoid the field completely, can eliminate the parasitic electric leakage of device field marginal radiation, and do not influence the characteristic of device subthreshold region, are fit for the characteristic of investigation material, reduce electric stress, have strengthened the anti total dose radiation ability; the inverter is connected behind the two single-tube amplifiers, so that the input and the output of the whole structure are in the same phase, and the function of widening the voltage input is achieved.

Description

CMOS device

Technical Field

The utility model relates to a microelectronics technical field. And more particularly, to a CMOS device.

Background

With the rapid development of science and technology, more and more electronic components and electronic equipment need to be used in a radiation environment. Some components in the electronic equipment receive the influence of factors such as radiation of external environment, illumination, form single event effect: a radiation effect of abnormal change of device state caused by single high-energy particles passing through a sensitive region of a microelectronic device comprises single event upset, single event locking, single event burnout, single event gate breakdown and the like, which cause some electrical parameters to change, and in severe cases may cause some electronic components to fail in function, so that the electronic equipment cannot normally work and operate.

CMOS circuits are widely applied to radiation environments such as satellite warfare, are particularly sensitive to radiation, are not reinforced, and have the total dose radiation resistance lower than 1 x 10⁴rad (Si) can cause damage to components if the dosage exceeds the dosage, so that the components can not work normally, and when the long-life satellite runs along the orbit, the total radiation dosage can reach 5 multiplied by 10⁵rad (si), obviously, the CMOS circuit without radiation hardening cannot meet the use requirements of long-life satellites and nuclear radiation environments, and therefore, the CMOS circuit must be radiation hardened.

Therefore, it is desirable to provide a CMOS device.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a CMOS device is enlargied for the single tube amplifier of eight star ring shape bars structure by two grids, and a phase inverter that connects afterwards can widen voltage input, has very strong radiation resistance simultaneously.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a CMOS device comprises a first-stage single-tube amplifier, a second-stage single-tube amplifier and a phase inverter, wherein grid electrodes in the first-stage single-tube amplifier and the second-stage single-tube amplifier are both of octagonal ring-shaped grid structures and surround drain electrodes, and source electrodes in the first-stage single-tube amplifier and the second-stage single-tube amplifier are located on the periphery of the grid electrodes.

Furthermore, the first-stage single-tube amplifier is an NMOS tube amplifier, and the second-stage single-tube amplifier is a PMOS tube amplifier.

Further, the octagonal ring-shaped grid structure comprises a long edge, a short edge and a bevel edge.

Further, the source electrode of the first-stage single-tube amplifier is connected with the grid electrode of the second-stage single-tube amplifier.

Further, the inverter is connected with the drain electrode of the second-stage single-tube amplifier.

Furthermore, the included angle between the bevel edge of the octagonal annular grid structure and the horizontal plane is 45 degrees.

Further, the grid is a polysilicon grid.

The utility model has the advantages as follows:

in the technical scheme of the utility model, two single tube amplifiers all adopt a ring grid structure, so that the field area can be completely avoided, the parasitic electric leakage of the edge radiation of the field area of the device can be eliminated, the characteristic of the subthreshold area of the device is not influenced, the characteristic of the material is suitable for investigation, the electric stress is reduced, and the total radiation resistance is enhanced; the input common source single-tube amplifier has high gain, the input and the output are in opposite phase, the output common drain single-tube amplifier has gain of about 1, the input and the output are in the same phase, and the inverter is connected at the back, so that the input and the output of the whole structure are in the same phase, and the function of widening voltage input is achieved.

Drawings

The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings;

fig. 1 is a schematic circuit diagram of a CMOS device according to the present invention;

fig. 2 is an exemplary layout of a single-transistor amplifier in a CMOS device according to the present invention.

Detailed Description

In order to explain the present invention more clearly, the present invention will be further described with reference to the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

As shown in fig. 1, the utility model discloses a CMOS device, including first order single tube amplifier 1, second level single tube amplifier 2 and phase inverter 3, wherein, the grid among first order single tube amplifier 1 and the second level single tube amplifier 2 is octagonal ring shape bars structure and surrounds the drain electrode, source in first order single tube amplifier 1 and the second level single tube amplifier 2 is located the grid is peripheral.

Specifically, the first-stage single-tube amplifier 1 is a common-source single-tube amplifier and consists of a current source 4 and an NMOS tube 5, the current source 4 is connected with a source electrode of the NMOS tube 5, the second-stage single-tube amplifier 2 is a common-drain single-tube amplifier and consists of a current source 7 and a PMOS tube 6, the current source 7 is connected with a drain electrode of the PMOS tube 6, the source electrode of the NMOS tube 5 is also connected with a grid electrode of the PMOS tube 6, the drain electrode of the PMOS tube 6 is connected with a phase inverter 3, when the voltage of the input first-stage single-tube amplifier 1 is high during working, the NMOS tube 5 is in a working state, is divided into partial voltage with the current source 4; at this time, for the second-stage single-tube amplifier 2 connected with the output end of the first-stage single-tube amplifier 1, the input is low, the PMOS tube 6 is started and is in a working state, the voltage is divided by the current source 7, the output is low, the input and the output are in phase, the inverter 3 is connected behind, the integral output is high, the input and the output of the whole structure are in phase, and the effect of widening the voltage input is achieved. The first-stage single-tube amplifier 1 amplifies the upper limit of the voltage, and the second-stage single-tube amplifier 2 pulls the lower limit of the voltage down, so that the upper limit and the lower limit of the input voltage can be widened on the premise that the voltage of the middle point is basically unchanged, and the wide-voltage input effect is achieved.

In this embodiment, the gates of the NMOS transistor 5 and the PMOS transistor 6 are both octagonal ring-shaped gate structures and surround the drain, and the source is located at the periphery of the gates. For a CMOS circuit, a single high-energy particle is incident to a source drain region of an MOS tube to generate high-density electron-hole pairs, and when the energy contained in the electron-hole pairs reaches a certain degree, the electron-hole pairs can affect the current component and components connected with the current component, so that some tubes which are supposed to be in a closed state are conducted, even absorbed by some sensitive PN junctions, and then some reverse-biased PN junctions can be conducted, so that the output error of an analog device is increased, or the conduction of a parasitic structure is induced to cause the permanent structure damage of the device. As the size of the transistor in the CMOS circuit is smaller and smaller, the turn-on voltage and the withstand voltage are lower, which also results in that the energy generated by the incidence of the high-energy particles has an increasing influence on the circuit. The gate-all-around structure is a CMOS device structure with a drain electrode completely surrounded by a gate, the structure can completely avoid a field region, can eliminate parasitic leakage on the edge radiation of the field region of the device, does not influence the characteristic of subthreshold removal of the device, and is more suitable for inspecting the characteristic of a material. Reducing electrical stress. The ring gate structure can improve the total radiation resistance of the MOS transistor, increase the area of the transistor and reduce the integration level of the layout. The level of total radiation resistance and single event effect resistance of the chip produced by the structural design can meet the requirements of the space design field at the present stage.

As shown in fig. 2, the octagonal ring-shaped gate used in the present invention includes a gate 11, a source 12, a drain 13, and a substrate 14, wherein the gate 11 is an octagonal ring-shaped gate structure. In addition, a gate connecting wire 15 is also included in the layout to lead out the gate 11 to be integrated with other MOS devices, and metal connection is led out through a lead hole 16. The octagonal ring-shaped grid structure comprises a long edge, a short edge and a bevel edge. The bevel edge angle of the octagonal annular grid is unified to 45 degrees, so that the drawing of the layout is facilitated, the manufacturing of the process is facilitated, and the process flow is unified and simplified.

The octagonal ring-shaped grid has the advantages that: compared with a square annular grid, the square annular grid has an internal angle of 90 degrees at a horizontal joint and a vertical joint, when electric charges flow on the grid, the electric field at the inflection point is strong due to the fact that the equipotential surface distribution is concentrated at the tip of the inflection point, so that the charge density at the tip is high, the current is uneven, and the performance of a CMOS device is easily influenced. In addition, compared with the square shape, the octagonal ring-shaped grid can increase the stress release of the ring grid in the process aspect, reduce the deformation and eliminate the problem of stress concentration. Compared with a simple rectangular ring, the octagonal ring-shaped grid structure is more accurate in manufacturing, and the rectangular ring cannot guarantee the consistency of the shape of a device because the rectangle is not easy to manufacture accurately in the manufacturing process. In addition, one of the considerations in determining the device index is the equivalent gate length of the device, and the equivalent gate lengths of the rectangular rings which cannot guarantee consistency cannot be consistent. And the adoption of the octagonal ring-shaped gate structure can reliably grasp the consistency of the device. The advantages are particularly obvious for digital gate circuits with high application integration level.

In the embodiment, in order to eliminate the source-drain current at the edge of the field region inside a single MOS device after radiation, the radiation protection reinforcing function is performed, the gate surrounds the drain, and the source is located at the periphery of the gate. Those skilled in the art will understand that in such a layout, the distance between the inner ring and the outer ring of the octagonal annular gate is the gate length, preferably 5 μm, the gate length of 5 μm can be adopted to lengthen the channel length, the turn-on speed of the MOS device is properly reduced, the pulse width of the voltage peak generated when a single particle enters the active region of the MOS device is smaller, and the gate length with increased length makes the voltage peak generated by the incident single particle not enough to turn on the MOS device to be normal. In the embodiment of the application, the grid electrode can be made of a polysilicon material, and compared with the traditional aluminum grid electrode, the grid electrode made of the polysilicon can enable the grid oxide layer to be manufactured into the grid oxide layer

The overall performance of the circuit is not affected.

Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for those skilled in the art to make other variations or changes based on the above descriptions, and all the embodiments cannot be exhausted here, and all the obvious variations or changes that belong to the technical solutions of the present invention are still in the protection scope of the present invention.

Claims

1. A CMOS device is characterized by comprising a first-stage single-tube amplifier, a second-stage single-tube amplifier and a phase inverter, wherein the first-stage single-tube amplifier consists of a current source and an NMOS tube, and the current source of the first-stage single-tube amplifier is connected with the source electrode of the NMOS tube; the second-stage single-tube amplifier consists of a current source and a PMOS (P-channel metal oxide semiconductor) tube, and the current source of the second-stage single-tube amplifier is connected with the drain electrode of the PMOS tube; the source electrode of the NMOS tube is connected with the grid electrode of the PMOS tube; the drain electrode of the PMOS tube is connected with the phase inverter;

the grid electrodes in the first-stage single-tube amplifier and the second-stage single-tube amplifier are both of octagonal ring-shaped grid structures and surround the drain electrodes, and the source electrodes in the first-stage single-tube amplifier and the second-stage single-tube amplifier are located on the periphery of the grid electrodes.

2. The CMOS device of claim 1, wherein the octagonal ring-shaped gate structure comprises a long side, a short side, and a beveled side.

3. The CMOS device of claim 2 wherein the angled sides of the octagonal ring-shaped gate structure are angled at 45 degrees from horizontal.

4. The CMOS device of claim 1, wherein the gate is a polysilicon gate.