CN210628287U

CN210628287U - Fan-out type wafer level packaging structure

Info

Publication number: CN210628287U
Application number: CN201921967024.9U
Authority: CN
Inventors: 杨宝亮
Original assignee: Shenzhen Lanke Semiconductor Technology Co Ltd
Current assignee: Shenzhen Lanke Semiconductor Technology Co Ltd
Priority date: 2019-11-14
Filing date: 2019-11-14
Publication date: 2020-05-26
Anticipated expiration: 2029-11-14

Abstract

The utility model discloses a fan-out type wafer level packaging structure, including chip, protective layer sheetmetal, solder ball and plastic envelope layer, the protective layer coats in the top of chip, the top fixed connection of sheetmetal and chip, be equipped with the opening that corresponds with the sheetmetal on the protective layer, the bottom fixed connection of solder ball and chip, the top of protective layer is equipped with the plastic envelope layer, the protective layer is including first adhesive linkage and the second adhesive linkage that the symmetry set up, be equipped with the first insulation layer and the second insulating layer that the symmetry set up between first adhesive linkage and the second adhesive linkage. The utility model discloses a multilayer structure's setting has strengthened packaging structure's wear-resisting and corrosion protection ability to the packaging effect of chip has been promoted.

Description

Fan-out type wafer level packaging structure

Technical Field

The utility model relates to a chip package technical field especially relates to a fan-out type wafer level packaging structure.

Background

The fan-out type wafer level package is an embedded package processed at a wafer level and is one of the main advanced packages with a large I/O number and good integration flexibility. Fan-out wafer level packaging techniques typically employ individual microchips cut from a wafer and then embedded on a new "man-made" wafer. In embedding, a sufficiently large spacing must be left between the microchips for fan-out rewiring.

However, the existing fan-out type wafer level packaging structure of the chip is simple, and the wear-resisting and corrosion-resisting capability of the protective layer composition structure of the packaging structure is weak, so that the packaging effect of the chip is influenced.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving among the prior art chip fan-out type wafer level packaging structure comparatively simple, packaging structure's protective layer component structure's wear-resisting and the less strong problem of corrosion protection ability, and the fan-out type wafer level packaging structure who proposes.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a fan-out wafer level package structure comprises a chip, a passivation metal plate, solder balls and a molding layer, the protective layer is coated on the top of the chip, the metal sheet is fixedly connected with the top of the chip, the protective layer is provided with an opening corresponding to the metal sheet, the solder balls are fixedly connected with the bottom of the chip, the top of the protective layer is provided with a plastic packaging layer, the protective layer comprises a first adhesive layer and a second adhesive layer which are symmetrically arranged, a first insulating layer and a second insulating layer which are symmetrically arranged are arranged between the first bonding layer and the second bonding layer, the first insulating layer and the second insulating layer are bonded with the first bonding layer and the second bonding layer through the wear-resistant layer, and a first anti-corrosion layer is arranged on one side, away from the first bonding layer, of the first insulating layer, a second anti-corrosion layer is arranged on one side, away from the second bonding layer, of the second insulating layer, and an anti-folding layer is arranged between the first anti-corrosion layer and the second anti-corrosion layer.

Preferably, the first insulating layer and the second insulating layer are both silicon nitride layers.

Preferably, the wear-resistant layer is a Cr/CrO multilayer coating consisting of Cr layers and CrO layers which are alternately arranged.

Preferably, the first and second corrosion protection layers are both ATO layers.

Preferably, the anti-folding layer is a metal mesh layer.

Preferably, the first adhesive layer and the second adhesive layer are both silica gel layers.

The utility model discloses in, the setting of wearing layer has strengthened packaging structure's wear resistance, and the setting of the Cr/CrO multilayer coating that Cr layer and CrO layer constitute in turn has strengthened the wear-resisting effect of wearing layer, and the setting of first anti-corrosion coating and second anti-corrosion coating has strengthened packaging structure's corrosion resistance, and the setting on ATO layer has strengthened anti-corrosion coating's corrosion protection ability simultaneously, and the toughness of packaging structure has been strengthened to the setting on anti-corrosion coating simultaneously. The utility model discloses a multilayer structure's setting has strengthened packaging structure's wear-resisting and corrosion protection ability to the packaging effect of chip has been promoted.

Drawings

Fig. 1 is a schematic structural diagram of a fan-out wafer level package structure according to the present invention;

fig. 2 is a schematic side view of the fan-out wafer level package structure according to the present invention.

In the figure: 1 chip, 2 protective layers, 201 first adhesive layers, 202 second adhesive layers, 203 first insulating layers, 204 second insulating layers, 205 wear-resistant layers, 206 first anti-corrosion layers, 207 second anti-corrosion layers, 208 anti-folding layers, 3 metal sheets, 4 solder balls and 5 plastic package layers.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Referring to fig. 1-2, a fan-out wafer level package structure includes a chip 1, a protective layer 2, a metal sheet 3, a solder ball 4 and a molding layer 5, the protective layer 2 is coated on the top of the chip 1, the metal sheet 3 is fixedly connected with the top of the chip 1, the protective layer 2 is provided with an opening corresponding to the metal sheet 3, the solder ball 4 is fixedly connected with the bottom of the chip 1, the top of the protective layer 2 is provided with the molding layer 5, the protective layer 2 includes a first adhesive layer 201 and a second adhesive layer 202 which are symmetrically arranged, a first insulating layer 203 and a second insulating layer 204 which are symmetrically arranged are arranged between the first adhesive layer 201 and the second adhesive layer 202 and used for enhancing the insulating property of the package structure, the first insulating layer 203 and the second insulating layer 204 are both adhered to the first adhesive layer 201 and the second adhesive layer 202 through a wear-resistant layer 205 and used for the wear-resistant ability of the package structure, a first anti-corrosion layer 206 is arranged on one side of the first insulating layer, the second anti-corrosion layer 207 is arranged on the side, away from the second adhesive layer 202, of the second insulating layer 204 and used for enhancing the anti-corrosion performance of the packaging structure, and the anti-folding layer 208 is arranged between the first anti-corrosion layer 206 and the second anti-corrosion layer 207 and used for enhancing the toughness of the packaging structure.

The utility model discloses in, first insulating layer 203 and second insulating layer 204 are the silicon nitride layer, an insulating ability for the reinforcing insulating layer, wearing layer 205 is the Cr/CrO multilayer coating that Cr layer and CrO layer constitute in turn, the wearing resistance of reinforcing wearing layer 205, first anti-corrosion layer 206 and second anti-corrosion layer 207 are the ATO layer, an ability of anticorrosion for the reinforcing anti-corrosion layer, anti-folding layer 208 is the metal mesh layer, the intensity of reinforcing anti-folding layer 208, first adhesive linkage 201 and second adhesive linkage 202 are the silica gel layer, the adhesive linkage of reinforcing adhesive linkage.

The utility model discloses in, wearing layer 205's setting has strengthened packaging structure's wear resistance, Cr/CrO multilayer coating's that Cr layer and CrO layer constitute in turn setting, the wear-resisting effect of wearing layer 205 has been strengthened, first anti-corrosion coating 206 and second anti-corrosion coating 207's setting has strengthened packaging structure's corrosion protection performance, ATO layer's setting has strengthened anti-corrosion coating's corrosion protection ability simultaneously, anti-folding layer 208's setting has strengthened packaging structure's toughness simultaneously.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims

1. The utility model provides a fan-out type wafer level packaging structure, includes chip (1), protective layer (2) sheetmetal (3), solder ball (4) and plastic envelope (5), a serial communication port, protective layer (2) coats in the top of chip (1), the top fixed connection of sheetmetal (3) and chip (1), be equipped with the opening that corresponds with sheetmetal (3) on protective layer (2), the bottom fixed connection of solder ball (4) and chip (1), the top of protective layer (2) is equipped with plastic envelope (5), protective layer (2) are including first adhesive linkage (201) and second adhesive linkage (202) that the symmetry set up, be equipped with first insulating layer (203) and second insulating layer (204) that the symmetry set up between first adhesive linkage (201) and second adhesive linkage (202), all through wearing layer (205) between first insulating layer (203) and second insulating layer (204) and first adhesive linkage (201) and second adhesive linkage (202) And bonding, wherein a first anti-corrosion layer (206) is arranged on one side, away from the first bonding layer (201), of the first insulating layer (203), a second anti-corrosion layer (207) is arranged on one side, away from the second bonding layer (202), of the second insulating layer (204), and an anti-folding layer (208) is arranged between the first anti-corrosion layer (206) and the second anti-corrosion layer (207).

2. The fan-out wafer level package structure of claim 1, wherein the first insulating layer (203) and the second insulating layer (204) are both silicon nitride layers.

3. The fan-out wafer level package structure of claim 1, wherein the wear layer (205) is a Cr/CrO multilayer coating comprising alternating Cr and CrO layers.

4. The fan-out wafer level package structure of claim 1, wherein the first corrosion protection layer (206) and the second corrosion protection layer (207) are both ATO layers.

5. The fan-out wafer level package structure of claim 1, wherein the anti-folding layer (208) is a metal mesh layer.

6. The fan-out wafer level package structure of claim 1, wherein the first adhesive layer (201) and the second adhesive layer (202) are silicone layers.