CN201681828U - Wafer bump structure - Google Patents
Wafer bump structure Download PDFInfo
- Publication number
- CN201681828U CN201681828U CN 201020192404 CN201020192404U CN201681828U CN 201681828 U CN201681828 U CN 201681828U CN 201020192404 CN201020192404 CN 201020192404 CN 201020192404 U CN201020192404 U CN 201020192404U CN 201681828 U CN201681828 U CN 201681828U
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- CN
- China
- Prior art keywords
- layer
- protective layer
- plating
- silicon wafer
- chip
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
A water bump structure comprises a wafer state semi-conductor chip, a front processing layer, a first chemical plating protective layer and a plurality of columnar bumps. The semi-conductor chip comprises a chip pad and a protective layer provided with an opening, the front processing layer is stacked on an exposed surface of the chip pad of the semi-conductor chip, the first chemical plating protective layer is stacked on the front treatment layer, the opened side wall of the protective layer and the surface outside the opening of the protective layer, the columnar bumps are stacked on the first chemical plating protective layer and portions of the surface of the protective layer, and each columnar bump consists of a molded conducting metal layer with the height meeting visual requirements and a second chemical plating protective layer which is coated on the outer peripheral edge of the conducting metal layer in a tight combination form, thereby being favorable for effectively reducing cost while increasing solderability of the wafer bump structure combined with corresponding components in subsequent operation.
Description
Technical field
The utility model relates to a kind of silicon wafer projection structure, relate in particular to a kind of with zinc impregnation processing (Zincating) and electroless plating nickel/gold (Electroless Nickel/Immersion Gold, ENIG) processing procedure replaces under-bump metallization (Under Bump Metallization, UBM) processing procedure, and the column-like projection block (Pillar Bump) that uses mode of printing to form conductive metal paste (Metal Paste) replaces the formed golden projection of electrogilding processing procedure.
Background technology
See also shown in Figure 2ly, be the existing silicon wafer projection structure schematic diagram that constitutes with the under-bump metallization processing procedure.As shown in the figure, a kind of known wafer projection cube structure 5 comprises that semiconductor chip 50, a projection lower metal layer 60 and a column-like projection block 70 form.Wherein the surface 501 of this semiconductor chip has several chip mats (Die Pad) 51; and on this surface 501 and this chip mat 51, has a protective layer (Passivation Layer) 52; this protective layer 52 has the perforate of corresponding each chip mat 51, with the part surface 501 that appears this chip mat 51.
Above-mentioned silicon wafer projection structure 5 uses the under-bump metallization processing procedures to protect its chip mat 51, but this processing procedure not only price is higher, and yield is also lower; Moreover, this silicon wafer projection structure 5 is to form this column-like projection block 70 with the electrogilding processing procedure behind above-mentioned processing procedure, therefore these column-like projection block 70 overall structures are all gold, be to be a gold medal projection, this is the higher precious metal material of cost based on relative other metal materials of metal, and under current price of gold long-term trend make progress, more cause the manufacturing cost of known silicon wafer projection structure 5 to climb successively.Therefore, because now the price of gold faces high awkward situation, known technology is with the golden projection of electrogilding processing procedure gained, the material cost of its high price is real to be difficult to meet the dealer with a large amount of productions, and then effectively force down the demand that the overall operation cost is a target, so it is required when reality is used to meet the user.
Summary of the invention
Technical problem to be solved in the utility model is: at above-mentioned the deficiencies in the prior art, provide a kind of silicon wafer projection structure that more can effectively reduce cost when being beneficial to the solderability that increases follow-up and corresponding assembly binding.
In order to solve the problems of the technologies described above, the technical scheme that the utility model adopted is: a kind of silicon wafer projection structure, comprise wafer state semiconductor chip and several column-like projection blocks, the surface of this semiconductor chip has several chip mats, and on this surface and this chip mat, has protective layer, this protective layer has the perforate of corresponding each chip mat, to appear the part surface of this chip mat; Be characterized in: also comprise the preprocessing layer and the first change plating, this preprocessing layer is stacked on the exposed surface of this chip mat; This first changes that plating is stacked on this preprocessing layer, the perforate sidewall of this protective layer and this protective layer be on the surface of this perforate outside; Described column-like projection block is stacked on this first change plating and on this protective layer part surface; wherein, the conductive metal layer that is shaped by visual demand height of each column-like projection block, and be the second change plating that the shape of combining closely coats with these conductive metal layer outer peripheral edges and formed.
By this, can the zinc impregnation processing and electroless plating nickel/golden processing procedure make preprocessing layer and change plating, replace the structure sheaf of the lower and former under-bump metallization processing procedure that price is higher of output, and can further look user's demand and have the characteristic that to prolong with former under-bump metallization processing procedure; More use conductive metal paste with mode of printing and be aided with the second Dow Chemical electronickelling/golden processing procedure or processing procedure that other can make solderability increase constitutes the column-like projection block of demand height, replace the formed golden projection of electrogilding processing procedure that output is lower and price is higher, be beneficial to increase the solderability while that follow-up and corresponding assembly links more can effectively reduce cost.
Description of drawings:
Fig. 1 is the structural profile schematic diagram of the utility model one preferred embodiment.
Fig. 2 is the known silicon wafer projection structure schematic diagram that constitutes with the under-bump metallization processing procedure.
Label declaration:
Silicon wafer projection structure 1,5 semiconductor chips 10,50
Surface 101,501 chip mats 11,51
Surface 111,121 protective layers 12,52
Preprocessing layer 20 first is changed plating 30
Column- like projection block 40,70 conductive metal layers 41
Second changes plating 42 gold medal layers 44
Projection lower metal layer 60
Embodiment:
See also shown in Figure 1ly, be the structural profile schematic diagram of the utility model one preferred embodiment.As shown in the figure: the utility model is a kind of silicon wafer projection structure 1, mainly comprises a wafer state semiconductor chip 10, a preprocessing layer 20, one first change plating 30 and 40 formations of several column-like projection blocks (Pillar Bump).
The surface 101 of this semiconductor chip has several chip mats (Die Pad) 11; and on this surface 101 and this chip mat 11, has a protective layer (Passivation Layer) 12; this protective layer 12 has the perforate of corresponding each chip mat 11, with the part surface 111 that appears this chip mat 11.
This preprocessing layer 20 is stacked on the exposed surface 111 of this chip mat 11, for handling the layer that prevents to corrode deterioration that (Zincating) constituted by zinc impregnation.
This first changes that plating 30 is stacked on this preprocessing layer 20, the perforate sidewall of this protective layer 12 and this protective layer 12 be on the surface 121 of this perforate outside; for by electroless plating nickel/gold (Electroless Nickel/Immersion Gold; ENIG) layer that prevents to corrode deterioration that is constituted, it comprises a nickel dam 31 and a gold medal layer 32.
Those column-like projection blocks 40 are stacked on this first change plating 30 and on these protective layer 12 part surfaces 121, and each column-like projection block 40 comprises the conductive metal layer 41 by printing formation demand height, and by electroless plating nickel/gold or include help scolding tin soak into formed second the change plating 42, this second change plating 42 is coated on this conductive metal layer 41 outer peripheral edges with the shape of combining closely, be beneficial to increase the solderability that follow-up and corresponding assembly links, wherein, this conductive metal layer 41 be included in this first change on plating 30 and on these protective layer 12 part surfaces 121 by conducting electricity silver paste or comprise the layer that prevents to connect airtight the power deterioration that the conductive metal paste (Metal Paste) of metallic conductor is constituted; This second is changed plating 42 and is included on these conductive metal layer 41 peripheries and this protective layer 12 part surfaces 121 by nickel/gold copper-base alloy or includes and help the layer that prevents to corrode deterioration that material constituted that scolding tin soaks into, and this second change plating 42 can be the composition that comprises a nickel dam 43 and a gold medal layer 44.The above constitutes a brand-new silicon wafer projection structure 1.
When the utility model in when preparation, whether visual above-mentioned these semiconductor chip 10 surfaces 101 have this protective layer 12 determines whether implementing and applies this protective layer 12, if there is then this structure can omit this road processing procedure, close chat earlier bright.In a preferred embodiment, this structure 1 is can use zinc impregnation processing and electroless plating nickel/golden processing procedure to form on the exposed surface 111 of this chip mat 11 can change plating 30 for the preprocessing layer 20 and first of this chip mat 11 of protection; Continue it, use conductive metal paste to form the conductive metal layer 41 of demand height with mode of printing; At last, the processing procedure that can use electroless plating nickel/golden processing procedure or other to help scolding tin to soak into forms the second change plating 42 that solderability is increased, and constitutes this column-like projection block 40 with this conductive metal layer 41 and this second change plating 42.In wherein; the utility model is protected this chip mat except using above-mentioned zinc impregnation processing and electroless plating nickel/golden processing procedure; (Under Bump Metallization, UBM) the formed multiple layer metal thin layer of processing procedure removes to protect this chip mat also can to prolong the usefulness under-bump metallization.
By this, the utility model can the zinc impregnation processing and the preprocessing layer of electroless plating nickel/golden processing procedure gained with change plating, replace the formed multiple layer metal thin layer of former under-bump metallization processing procedure that output is lower and price is higher, and can further look user's demand and have the characteristic that to prolong with former under-bump metallization processing procedure; Moreover; the utility model more uses conductive metal paste with mode of printing and be aided with the second Dow Chemical electronickelling/golden processing procedure or processing procedure that other helps scolding tin to soak into forms the protective layer that solderability is increased; and then the column-like projection block of formation demand height, to replace the formed golden projection of electrogilding processing procedure that output is lower and price is higher.
In sum, the utility model is a kind of silicon wafer projection structure, can effectively improve the various shortcoming of prior art, can the zinc impregnation processing and electroless plating nickel/golden processing procedure replace the former under-bump metallization processing procedure that output is lower and price is higher, more use conductive metal paste with mode of printing and be aided with the second Dow Chemical electronickelling/golden processing procedure or processing procedure that other can make solderability increase constitutes the column-like projection block of demand height, replace the formed golden projection of electrogilding processing procedure that output is lower and price is higher, to reach the purpose that effectively reduces cost.
Claims (9)
1. silicon wafer projection structure, comprise wafer state semiconductor chip and several column-like projection blocks, the surface of this semiconductor chip has several chip mats, and has protective layer on this surface and this chip mat, this protective layer has the perforate of corresponding each chip mat, to appear the part surface of this chip mat; It is characterized in that: also comprise the preprocessing layer and the first change plating, this preprocessing layer is stacked on the exposed surface of this chip mat; This first changes that plating is stacked on this preprocessing layer, the perforate sidewall of this protective layer and this protective layer be on the surface of this perforate outside; Described column-like projection block is stacked on this first change plating and on this protective layer part surface; wherein, the conductive metal layer that is shaped by visual demand height of each column-like projection block, and be the second change plating that the shape of combining closely coats with these conductive metal layer outer peripheral edges and formed.
2. silicon wafer projection structure as claimed in claim 1 is characterized in that: described preprocessing layer is for preventing to corrode the layer of deterioration.
3. silicon wafer projection structure as claimed in claim 1 is characterized in that: described first changes plating for preventing to corrode the layer of deterioration.
4. silicon wafer projection structure as claimed in claim 1 is characterized in that: described first changes plating is made up of nickel dam and gold layer.
5. silicon wafer projection structure as claimed in claim 1 is characterized in that: described column-like projection block comprises conductive metal layer, reaches the second change plating.
6. silicon wafer projection structure as claimed in claim 1; it is characterized in that: described conductive metal layer is arranged on this and first changes on plating and on this protective layer part surface, the conduction silver paste or comprise the layer that prevents to connect airtight the power deterioration that conductive metal paste constituted of metallic conductor of serving as reasons.
7. silicon wafer projection structure as claimed in claim 1 is characterized in that: described second changes plating for preventing to corrode the layer of deterioration, is arranged on this conductive metal layer periphery and this protective layer part surface.
8. silicon wafer projection structure as claimed in claim 1 is characterized in that: described second changes plating is made up of nickel dam and gold layer.
9. silicon wafer projection structure as claimed in claim 1 is characterized in that: the multiple layer metal thin layer that is formed with this chip mat of protection on the exposed surface of described chip mat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020192404 CN201681828U (en) | 2010-05-17 | 2010-05-17 | Wafer bump structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020192404 CN201681828U (en) | 2010-05-17 | 2010-05-17 | Wafer bump structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681828U true CN201681828U (en) | 2010-12-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201020192404 Expired - Lifetime CN201681828U (en) | 2010-05-17 | 2010-05-17 | Wafer bump structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN201681828U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543930A (en) * | 2012-02-03 | 2012-07-04 | 昆山美微电子科技有限公司 | Electroforming wafer bump |
| CN102593017A (en) * | 2011-01-12 | 2012-07-18 | 颀邦科技股份有限公司 | Process for producing antioxidative metal layers on side surfaces of connecting parts on support plates |
| WO2014005246A1 (en) * | 2012-07-05 | 2014-01-09 | 璩泽明 | Chemical nickel plating bump structure of wafer soldering pad and manufacturing method therefor |
| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
-
2010
- 2010-05-17 CN CN 201020192404 patent/CN201681828U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593017A (en) * | 2011-01-12 | 2012-07-18 | 颀邦科技股份有限公司 | Process for producing antioxidative metal layers on side surfaces of connecting parts on support plates |
| CN102593017B (en) * | 2011-01-12 | 2015-03-25 | 颀邦科技股份有限公司 | Process for producing antioxidative metal layers on side surfaces of connecting parts on support plates |
| CN102543930A (en) * | 2012-02-03 | 2012-07-04 | 昆山美微电子科技有限公司 | Electroforming wafer bump |
| WO2014005246A1 (en) * | 2012-07-05 | 2014-01-09 | 璩泽明 | Chemical nickel plating bump structure of wafer soldering pad and manufacturing method therefor |
| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JIYI TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: MAO BANG ELECTRONIC CO., LTD. Effective date: 20110921 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20110921 Address after: China Taiwan Taoyuan County Patentee after: Aflash Technology Co., Ltd. Address before: Chinese Taiwan Taoyuan Luju Nanshan Road three lane 17 No. 11 6 floor Patentee before: Mao Bang Electronic Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191129 Address after: 11, Lane 17, section 3, Nanshan Road, Luzhu Township, Taoyuan County, Taiwan, China Co-patentee after: XIAMEN MINGSHENG XINBANG TECHNOLOGY CO., LTD. Patentee after: Aflash Technology Co., Ltd. Address before: Taoyuan County, Taiwan, China Patentee before: Aflash Technology Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |