CN210628283U - Wafer-level chip size packaging structure - Google Patents

Abstract

The utility model discloses a wafer level chip size packaging structure, including chip, protective layer and pad, the protective layer coats in the top of chip, the top fixed connection of pad and chip, be equipped with the opening that corresponds with the pad on the protective layer, first wearing layer and the second wearing layer that the protective layer set up including the symmetry, be equipped with the first insulation layer and the second insulating layer that the symmetry set up between first wearing layer and the second wearing layer, all bond through the glue film between first insulation layer and second insulating layer and first wearing layer and the second wearing layer, one side that first wearing layer was kept away from on the first insulation layer is equipped with first anticorrosion coating. The utility model discloses a multilayer structure's setting has strengthened packaging structure's wear-resisting and corrosion protection ability to the packaging effect of chip has been promoted.

Description

Wafer-level chip size packaging structure

Technical Field

The utility model relates to a chip package technical field especially relates to a wafer level chip size packaging structure.

Background

The wafer level chip scale package technology is a technology for obtaining a single chip by cutting after a whole wafer is subjected to a package test. Generally, the wafer level chip scale package is a large number of solder balls distributed in a planar array on the peripheral pads of a semiconductor chip by redistribution process, or the solder balls are called solder bumps.

However, the existing chip size packaging structure is simple, and the wear-resisting and corrosion-resisting capability of the protective layer composition structure of the packaging structure is weak, so that the packaging effect of the chip is influenced.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the problem that chip size packaging structure is comparatively simple among the prior art, packaging structure's protective layer component structure's wear-resisting and corrosion protection ability is more weak, and the wafer level chip size packaging structure who provides.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a wafer level chip size packaging structure, includes chip, protective layer and pad, the protective layer coats in the top of chip, the top fixed connection of pad and chip, be equipped with the opening that corresponds with the pad on the protective layer, first wearing layer and the second wearing layer that the protective layer set up including the symmetry, be equipped with first insulating layer and the second insulating layer that the symmetry set up between first wearing layer and the second wearing layer, all bond through the glue film between first insulating layer and second insulating layer and first wearing layer and the second wearing layer, one side that first wearing layer was kept away from on the first insulating layer is equipped with first anti-corrosion coating, one side that second wearing layer was kept away from to the second insulating layer is equipped with second anti-corrosion coating, be equipped with anti-folding layer between first anti-corrosion coating and the second anti-corrosion coating.

Preferably, the first insulating layer and the second insulating layer are both silicon nitride layers.

Preferably, the glue layer is a bio-hotmelt glue layer.

Preferably, the first and second corrosion protection layers are both epoxy zinc-rich layers.

Preferably, the anti-folding layer is a metal mesh layer.

Preferably, the first wear-resistant layer and the second wear-resistant layer are both epoxy resin layers.

The utility model discloses in, the insulating properties of packaging structure has been strengthened in the setting of first insulating layer and second insulating layer, and the insulating effect of insulating layer has been strengthened in the setting of silicon nitride layer, and the setting of first anti-corrosion coating and second anti-corrosion coating has strengthened packaging structure's corrosion resistance, and the setting on the rich zinc layer of epoxy has strengthened anti-corrosion coating's corrosion protection ability simultaneously, and the toughness of packaging structure has been strengthened in the setting on anti-folding layer simultaneously. The utility model discloses a multilayer structure's setting has strengthened packaging structure's wear-resisting and corrosion protection ability to the packaging effect of chip has been promoted.

Drawings

Fig. 1 is a schematic structural diagram of a wafer level chip scale package structure according to the present invention;

fig. 2 is a schematic side view of a wafer level chip scale package structure according to the present invention.

In the figure: 1 chip, 2 protective layers, 201 a first wear-resistant layer, 202 a second wear-resistant layer, 203 a first insulating layer, 204 a second insulating layer, 205 an adhesive layer, 206 a first anti-corrosion layer, 207 a second anti-corrosion layer, 208 an anti-folding layer and 3 bonding pads.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Referring to fig. 1-2, a wafer-level chip size package structure includes a chip 1, a protection layer 2 and a pad 3, the protection layer 2 is coated on the top of the chip 1, the pad 3 is fixedly connected to the top of the chip 1, the protection layer 2 is provided with an opening corresponding to the pad 3, the protection layer 2 includes a first wear-resistant layer 201 and a second wear-resistant layer 202 which are symmetrically arranged, a first insulation layer 203 and a second insulation layer 204 which are symmetrically arranged are arranged between the first wear-resistant layer 201 and the second wear-resistant layer 202 for enhancing the insulation performance of the package structure, the first insulation layer 203 and the second insulation layer 204 are bonded with the first wear-resistant layer 201 and the second wear-resistant layer 202 through a glue layer 205 for enhancing the stability between the insulation layers and the wear-resistant layers, a first anti-corrosion layer 206 is arranged on a side of the first insulation layer 203 away from the first wear-resistant layer 201 for enhancing the anti-corrosion performance of the package structure, a second anti-corrosion layer 207 is arranged on a side, and the anti-folding layer 208 is arranged between the first anti-corrosion layer 206 and the second anti-corrosion layer 207 and is used for enhancing the toughness of the packaging structure.

The utility model discloses in, first insulating layer 203 and second insulating layer 204 are the silicon nitride layer for the insulating ability of reinforcing insulating layer, glue film 205 is biological hot melt adhesive layer, first anti-corrosion coating 206 and second anti-corrosion coating 207 are the rich zinc layer of epoxy, a corrosion protection ability for reinforcing anti-corrosion coating, anti folded layer 208 is the metal mesh layer, the intensity of reinforcing anti folded layer 208, first wearing layer 201 and second wearing layer 202 are the epoxy layer, the wearing feature of reinforcing wearing layer.

The utility model discloses in, the insulating properties of packaging structure has been strengthened in the setting of first insulating layer 203 and second insulating layer 204, and the insulating effect of insulating layer has been strengthened in the setting of silicon nitride layer simultaneously, and the setting of first anti-corrosion coating 206 and second anti-corrosion coating 207 has strengthened packaging structure's corrosion protection, and the setting on the rich zinc layer of epoxy has strengthened anti-corrosion coating's corrosion protection ability simultaneously, and anti folded layer 208's setting has strengthened packaging structure's toughness simultaneously.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims (6)

1. The utility model provides a wafer level chip size packaging structure, includes chip (1), protective layer (2) and pad (3), its characterized in that, protective layer (2) coats in the top of chip (1), the top fixed connection of pad (3) and chip (1), be equipped with the opening that corresponds with pad (3) on protective layer (2), protective layer (2) are including first wearing layer (201) and second wearing layer (202) that the symmetry set up, be equipped with first insulating layer (203) and second insulating layer (204) that the symmetry set up between first wearing layer (201) and second wearing layer (202), all bond through glue film (205) between first insulating layer (203) and second insulating layer (204) and first wearing layer (201) and second wearing layer (202), one side that first wearing layer (201) was kept away from in first insulating layer (203) is equipped with first anticorrosion layer (206), and a second anti-corrosion layer (207) is arranged on one side, away from the second wear-resistant layer (202), of the second insulating layer (204), and an anti-folding layer (208) is arranged between the first anti-corrosion layer (206) and the second anti-corrosion layer (207).

2. The wafer-level chip scale package structure of claim 1, wherein the first insulating layer (203) and the second insulating layer (204) are both silicon nitride layers.

3. The wafer-level chip scale package structure of claim 1, wherein the adhesive layer (205) is a bio-thermo-melt adhesive layer.

4. The wafer-level chip scale package structure of claim 1, wherein the first corrosion protection layer (206) and the second corrosion protection layer (207) are both epoxy zinc-rich layers.

5. The wafer-level chip scale package structure of claim 1, wherein the anti-folding layer (208) is a metal mesh layer.

6. The wafer-level chip scale package structure of claim 1, wherein the first abrasion resistant layer (201) and the second abrasion resistant layer (202) are both epoxy layers.

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