CN213124422U - Packaging structure of chip - Google Patents
Packaging structure of chip Download PDFInfo
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- CN213124422U CN213124422U CN202022739364.5U CN202022739364U CN213124422U CN 213124422 U CN213124422 U CN 213124422U CN 202022739364 U CN202022739364 U CN 202022739364U CN 213124422 U CN213124422 U CN 213124422U
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Abstract
The utility model discloses a packaging structure of chip belongs to semiconductor packaging technology field. Be provided with chip electrode (113), passivation layer I (210), insulating layer I (310) on chip unit body (10) of its first plastic-sealed body, set up metal connecting piece I in I (311) of insulating layer I opening, plastic-sealed material I (510) carry out the plastic envelope with metal connecting piece I, the first plastic-sealed body of plastic-sealed material II (610) cladding forms the second plastic-sealed body, it sets up in second plastic-sealed body top to lay wire metal layer (710) again, it sets up passivation layer II (810) and metal connecting piece II (900) to lay wire metal layer (710) top again. The utility model discloses can protect the chip openly effectively, improve the reliability of product.
Description
Technical Field
The utility model relates to a packaging structure of chip belongs to semiconductor chip package technical field.
Background
A conventional fan-out package product is shown in fig. 1, and includes a chip unit body 100 having an active surface, where the active surface of the chip unit body 100 is provided with a chip electrode 101, the active surface of the chip unit body 100 and an upper surface of the chip electrode 101 are provided with a protection layer 200, the protection layer 200 is provided with a protection layer opening above the chip electrode 101, a metal bump 300 is disposed in the protection layer opening, and the metal bump 300 is connected to the chip electrode 101 through the protection layer opening; a back surface protection layer 600 is disposed on the back surface of the chip unit body 100. The protection of the front side of the existing chip packaging product is weaker, and the problem of chip function failure easily occurs when the stress on the front side of the chip is larger.
Disclosure of Invention
An object of the utility model is to overcome current packaging technique not enough, provide a chip packaging structure that the chip openly received the protection.
The purpose of the utility model is realized like this:
the utility model provides a chip packaging structure, which comprises a first plastic package body, a plastic package material II, a rewiring metal layer, a passivation layer II and a metal connecting piece II,
the first plastic package body comprises a chip unit body with an active surface and a plastic package material I, wherein a plurality of chip electrodes are arranged on the active surface of the chip unit body, passivation layer I and passivation layer I openings are arranged on the active surface of the chip unit body and the upper surfaces of the chip electrodes, an insulating layer I and an insulating layer I opening I are arranged in the passivation layer I opening, the insulating layer I opening I exposes the upper surface of the chip electrode, a metal connecting piece I is arranged in the insulating layer I opening I, the metal connecting piece I is connected with the chip electrodes through the insulating layer I opening I, the plastic package material I carries out plastic package on the metal connecting piece I, and the upper surface of the plastic package material I is flush with the upper surface of the metal connecting piece I;
the plastic package material II coats the periphery and the back of the first plastic package body to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the first plastic package body;
the rewiring metal layer is arranged above the second plastic package body and comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are connected selectively, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer is provided with a lower layer bonding pad, the uppermost termination layer of the rewiring metal layer is provided with an upper layer bonding pad, the lower layer bonding pad and the upper layer bonding pad are both exposed out of the insulating filling layers, and the lower layer bonding pad is connected with the upper surface of the metal connecting piece I of the first plastic package body;
a passivation layer II and a passivation layer II opening are arranged above the rewiring metal layer, and the passivation layer II opening exposes the upper-layer bonding pad of the rewiring metal layer;
and a metal connecting piece II is arranged above the passivation layer II and is connected with the upper-layer bonding pad of the rewiring metal layer.
Optionally, the metal connecting piece i is sequentially provided with an adhesion barrier layer, a metal seed layer i and a metal bump from bottom to top, wherein the adhesion barrier layer is a composite layer formed by one or two layers of materials.
Optionally, the cross-sectional shape of the metal bump includes, but is not limited to, rectangular, circular, or oval.
Optionally, the metal seed layer i and the metal bump are of an integral structure.
Optionally, the metal connector ii sequentially includes, from bottom to top, an adhesion layer, a metal seed layer ii, a metal pillar, and a solder ball.
Optionally, the metal seed layer ii and the metal pillar are of an integral structure, and the cross-sectional shape of the metal pillar includes, but is not limited to, a rectangle, a circle, or an ellipse.
Advantageous effects
1. The utility model firstly carries out the first plastic package after finishing the metal lug on the front surface of the supplied material wafer to form a first plastic package body and expose the upper surface of the metal lug to form an electrical connection surface; after the front side plastic package is completed, the periphery and the back side of the chip are subjected to plastic package to form a second plastic package body, and the reconstruction of the wafer after cutting is completed; through twice plastic packaging, a buffering effect is formed on the surface of the chip, the front surface of the chip can be effectively protected, the mechanical strength and rigidity of the front surface of the chip are improved, the damage to the surface of the chip caused by the stress of the soldering tin balls is reduced, the problem of packaging finished products of chip fragments is solved, and the reliability of the product is improved;
2. because the front surface and the back surface of the chip are both provided with the plastic packaging materials (EMC), the stress of the front surface and the back surface of the chip and the stress of the front surface and the back surface of the chip are mutually offset, and the warping problem of a product is favorably improved;
3. the utility model discloses a set up the adhesion barrier layer, prevented metal atom's such as Cu diffusion effectively, avoided the chip function inefficacy that metal atom diffusion caused effectively.
Drawings
FIG. 1 is a diagram of a conventional chip package structure;
fig. 2 is a schematic cross-sectional view of a chip package structure according to the present invention;
in the figure:
Chip electrode 113
Passivation layer I210
Passivation layer I opening 213
Insulating layer I310
Insulating layer I opening I311
Adhesion barrier 410
Plastic packaging material I510
Plastic packaging material II 610
Rewiring metal layer 710
Upper layer pad 715
Passivation layer II 810
Passivation layer II opening 813
Metal connecting piece II 900
Solder balls 950.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the accompanying drawings.
Examples
The utility model relates to a packaging structure of chip, it includes first plastic-sealed body, plastic-sealed material II 610, rewiring metal level 710, passivation layer II 810 and metal connecting piece II 900.
The first plastic package body comprises a chip unit body 10 with an active surface and a plastic package material I510, wherein the thickness of the chip unit body 10 is usually 25-150 micrometers. The active surface of chip unit body 10 is provided with a plurality of chip electrode 113, the active surface of chip unit body 10 and the upper surface of chip electrode 113 are provided with I210 of passivation layer and I opening 213 of passivation layer, set up I311 of insulating layer and I opening 311 of insulating layer in I opening 213 of passivation layer, I311 of insulating layer exposes the upper surface of chip electrode 113, set up metal connecting piece I in I opening 311 of insulating layer, metal connecting piece I is connected with chip electrode 113 through I opening 311 of insulating layer. The metal connecting piece I is sequentially provided with an adhesion barrier layer 410, a metal seed layer I and a metal bump 430 from bottom to top. The material of the metal seed layer I is Cu, Ni and the like, and the thickness of the metal seed layer I is 0.01-1 micron. The metal material of the metal bump 430 includes, but is not limited to, Ti, Cu, Ni, Sn, and Au, and the cross-sectional shape thereof includes, but is not limited to, a rectangle, a circle, or an ellipse. Preferably, the metal seed layer i and the metal bump 430 are of an integral structure. The adhesion barrier layer 410 is made of Cr, Ti, TiW, V, NiV, etc., and can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion barrier layer 410 is 0.1-3 microns. The adhesion barrier layer 410 functions to block metal atoms or other metal particles of the metal seed layer i and the metal bumps 430 from diffusing into the chip unit body 10, in addition to functioning to bond with the chip electrodes 113.
The plastic packaging material I510 is used for plastically packaging the metal connecting piece I, and the upper surface of the metal connecting piece I is flush with the upper surface of the metal connecting piece I; the plastic packaging material I510 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound i 510 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
The plastic package material II 610 covers the periphery and the back of the first plastic package body to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the first plastic package body; the plastic package material II 610 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound ii 610 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
The rewiring metal layer 710 is arranged above the second plastic package body, the rewiring metal layer 710 comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are selectively connected, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer 710 is provided with a lower bonding pad 713, the uppermost termination layer of the rewiring metal layer 710 is provided with an upper bonding pad 715, the lower bonding pad 713 and the upper bonding pad 715 are both exposed out of the insulating filling layers, and the lower bonding pad 713 is connected with the upper surface of the metal connecting piece I of the first plastic package body;
a passivation layer II 810 and a passivation layer II opening 813 are arranged above the rewiring metal layer 710, and the passivation layer II opening 813 exposes the upper-layer bonding pad 715 of the rewiring metal layer 710;
and a metal connector II 900 is arranged above the passivation layer II 810, and the metal connector II 900 is connected with the upper-layer bonding pad 715 of the rewiring metal layer 710. The metal connecting piece II 900 sequentially comprises an adhesion layer 910, a metal seed layer II, metal columns 920 and solder balls 950 from bottom to top. The material of the metal seed layer II is Cu, Ni, etc., and the thickness of the metal seed layer II is 0.01-1 micron. Usually, the metal seed layer ii and the metal pillar 920 are an integral structure, and the height of the metal pillar 920 is usually 2 to 100 micrometers. The metal material of the metal pillar 920 is generally Cu, CuNi, CuNiAu, NiAu, etc., and the cross-sectional shape thereof includes, but is not limited to, a rectangle, a circle, or an ellipse. The material of the adhesion layer 910 is Cr, Ti, TiW, V, NiV, etc., and it can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion layer 910 is 0.01-2 μm. The adhesive layer 910 may function in conjunction with the upper pad 715 of the re-wiring metal layer 710.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only a detailed description of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A chip packaging structure is characterized by comprising a first plastic packaging body, a plastic packaging material II (610), a rewiring metal layer (710), a passivation layer II (810) and a metal connecting piece II (900),
the first plastic package body comprises a chip unit body (10) with an active surface and a plastic package material I (510), the active surface of the chip unit body (10) is provided with a plurality of chip electrodes (113), the active surface of the chip unit body (10) and the upper surface of the chip electrode (113) are provided with a passivation layer I (210) and a passivation layer I opening (213), an insulating layer I (310) and an insulating layer I opening I (311) are arranged in the passivation layer I opening (213), the insulating layer I opening I (311) exposes the upper surface of the chip electrode (113), a metal connecting piece I is arranged in the opening I (311) of the insulating layer I, the metal connecting piece I is connected with the chip electrode (113) through the opening I (311) of the insulating layer I, the plastic packaging material I (510) is used for plastically packaging the metal connecting piece I, and the upper surface of the plastic packaging material I is flush with the upper surface of the metal connecting piece I;
the plastic package material II (610) covers the periphery and the back of the first plastic package body to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the first plastic package body;
the rewiring metal layer (710) is arranged above the second plastic package body, the rewiring metal layer (710) comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are selectively connected, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer (710) is provided with a lower bonding pad (713), the uppermost termination layer of the rewiring metal layer (710) is provided with an upper bonding pad (715), the lower bonding pad (713) and the upper bonding pad (715) are exposed out of the insulating filling layers, and the lower bonding pad (713) is connected with the upper surface of the metal connecting piece I of the first plastic package body;
a passivation layer II (810) and a passivation layer II opening (813) are arranged above the rewiring metal layer (710), and the passivation layer II opening (813) exposes an upper layer pad (715) of the rewiring metal layer (710);
and a metal connecting piece II (900) is arranged above the passivation layer II (810), and the metal connecting piece II (900) is connected with an upper layer bonding pad (715) of the rewiring metal layer (710).
2. The package structure of claim 1, wherein the metal connecting member I is sequentially provided with an adhesion barrier layer (410), a metal seed layer I and a metal bump (430) from bottom to top, and the adhesion barrier layer (410) is a composite layer formed by one or two layers of materials.
3. The package structure of claim 2, wherein a cross-sectional shape of the metal bump (430) includes, but is not limited to, rectangular, circular, or oval.
4. The package structure of claim 2 or 3, wherein the metal seed layer I and the metal bump (430) are a unitary structure.
5. The package structure of claim 1, wherein the metal connection member II (900) comprises an adhesion layer (910), a metal seed layer II, a metal pillar (920) and a solder ball (950) in sequence from bottom to top.
6. The package structure of claim 5, wherein the metal seed layer II and the metal pillar (920) are a unitary structure, and a cross-sectional shape of the metal pillar (920) includes but is not limited to a rectangle, a circle, or an ellipse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022739364.5U CN213124422U (en) | 2020-11-24 | 2020-11-24 | Packaging structure of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022739364.5U CN213124422U (en) | 2020-11-24 | 2020-11-24 | Packaging structure of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213124422U true CN213124422U (en) | 2021-05-04 |
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ID=75668446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022739364.5U Active CN213124422U (en) | 2020-11-24 | 2020-11-24 | Packaging structure of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213124422U (en) |
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2020
- 2020-11-24 CN CN202022739364.5U patent/CN213124422U/en active Active
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