CN211605149U

CN211605149U - Packaging structure of chip

Info

Publication number: CN211605149U
Application number: CN202020600590.2U
Authority: CN
Inventors: 陈栋; 成炎炎; 胡震; 陈锦辉; 张国栋
Original assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Current assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Priority date: 2020-04-21
Filing date: 2020-04-21
Publication date: 2020-09-29
Anticipated expiration: 2030-04-21

Abstract

The utility model discloses a packaging structure of chip belongs to semiconductor packaging technology field. The chip comprises a chip body (100), wherein a protective layer (200) is arranged on the active surface of the chip body (100) and the upper surface of a chip electrode (101), a metal bump (300) is arranged in a protective layer opening (201), an adhesion layer (601) and a seed layer (602) are sequentially arranged on the back surface of the chip body (100), and the adhesion layer (601) covers the back surface of the chip body (100); the lower surface of the seed layer (602) is sequentially provided with a back gold block (600) and a graphene layer (610), and the coating layer (700) coats the exposed surfaces of the back gold block (600) and the graphene layer (610) and extends upwards to the peripheral edge of the lower surface of the adhesive layer (601). The utility model discloses wafer warpage and piece, heat dissipation problem can be overcome effectively, the warpage that the scribing degree of difficulty, solution encapsulation finished product produced and cracked scheduling problem have been reduced.

Description

Packaging structure of chip

Technical Field

The utility model relates to a packaging structure of chip belongs to semiconductor chip package technical field.

Background

With the development of the semiconductor industry, the performance requirements for electronic products are continuously increasing. For power supply products represented by the MOSFET, the thickness of a chip needs to be continuously reduced, and the thickness of metal (back metal for short) on the back of the chip needs to be increased, so as to reduce resistance and improve product performance; the thickness of the chip of the current product is as thin as 50 microns, and the thickness of the back gold is as thick as 50 microns; with the trend of continuous reduction of product resistance, the thickness of the chip needs to be further reduced, and the thickness of the back gold needs to be further increased.

The conventional chip package structure is shown in fig. 1, in which a protection layer and a bump are disposed on a chip, and a back metal is disposed on the back surface of the chip. The packaging method comprises the following steps: forming a protective layer on the front surface of the wafer through photoetching, forming bumps through electroplating or chemical plating, grinding the back surface of the wafer, evaporating and depositing metal, and then cutting into single chips.

With the continuous reduction of the thickness of the chip and the continuous increase of the thickness of the back gold, the existing packaging method has the following problems: 1, because the wafer is very thin, the wafer can shake when being subjected to cutting force during scribing; the back metal is very thick, and when the back metal is directly scratched to be too thick, the metal can stick to a knife and cut and draw wires; this easily causes chipping of the chip, resulting in a great difficulty in dicing. 2, the back gold material often contains metals such as Cu and the like which are easy to diffuse into the chip, the thick back gold is easy to form drawn wires during scribing, and the metal wires containing Cu are easy to diffuse into the chip after contacting with the chip, so that the chip fails in function. The packaged finished product has the following problems: 1, the chip is thinner and the back gold is thicker, and due to the difference of the thermal expansion coefficients of the chip and the back gold, the chip can warp, so that cold joint is generated in SMT (surface mount technology); 2, the mechanical strength of the packaged finished product is directly related to the thickness of the chip, and along with the reduction of the thickness of the chip, the strength of the packaged finished product is reduced, so that the packaged finished product is easy to crack in subsequent use, and the reliability problem is caused.

Disclosure of Invention

An object of the utility model is to overcome current packaging technology not enough, provide one kind and can avoid the back of the body gold to spread the inside encapsulation structure that leads to the functional failure of chip, solve the encapsulation finished product and produce warpage and cracked chip.

The purpose of the utility model is realized like this:

the utility model relates to a chip packaging structure, it includes the chip body that has active surface, the active surface of chip body is provided with the chip electrode, the active surface of chip body and the upper surface of chip electrode are provided with the protective layer, the protective layer sets up the protective layer opening above the chip electrode, set up metal lug in the protective layer opening, metal lug passes through the protective layer opening and is connected with the chip electrode;

the back surface of the chip body is sequentially provided with an adhesion layer and a seed layer, and the adhesion layer covers the back surface of the chip body;

the cross section of the seed layer is smaller than that of the chip body and/or that of the adhesive layer, and the peripheral edge of the lower surface of the adhesive layer is exposed;

the lower surface of the seed layer is sequentially provided with a back gold block and a graphene layer, and the coverage areas of the back gold block and the graphene layer are equal;

the graphene adhesive further comprises a coating layer, wherein the coating layer coats the bare surfaces of the back gold blocks and the graphene layer and extends upwards to the peripheral edge of the lower surface of the adhesive layer.

Further, the metal material of the metal bump includes, but is not limited to, Ti, Cu, Ni, Sn, and Au elements.

Further, the material of the back gold block includes, but is not limited to, TiNiAg, TiNiAgNi, CrCu, CrCuCr, TiCu, TiCuTi, TiCuNi.

Further, adhesion layers include, but are not limited to, Cr, Ti, TiW, V, NiV.

Further, the thickness of the adhesion layer is 0.01-3 microns.

Further, the seed layer comprises but is not limited to Cu and Ni, and the thickness of the seed layer is 0.01-1 micron.

Further, the material of the coating layer is a thermosetting polymer material, including but not limited to epoxy resin and phenolic resin.

Advantageous effects

1. The utility model increases the rigidity of the finished product of the chip packaging structure through the composite packaging body structure formed by the chip, the back gold block, the graphene layer and the packaging layer, overcomes the warping problem of the packaged finished product, and solves the SMT rosin joint; the mechanical strength and the heat dissipation capacity of a chip packaging finished product are improved through the composite packaging body structure, the problem of fragment packaging finished products is solved, and the reliability is improved;

2. the utility model discloses an adhesion layer has ensured that seed layer and back of the body have complete diffusion barrier layer between gold and the chip body, has avoided the chip function inefficacy that metal atom diffusion caused effectively.

Drawings

FIG. 1 is a diagram of a conventional chip package structure;

fig. 2 is a schematic cross-sectional view of an embodiment of a chip package structure according to the present invention;

in the figure:

chip body 100

Chip electrode 101

Protective layer 200

Bump 300

Back gold block 600

Adhesive layer 601

Seed layer 602

Graphene layer 610

A cladding layer 700.

Detailed Description

The following describes in detail embodiments of the present invention with reference to the accompanying drawings.

Examples

The utility model relates to a chip packaging structure, as shown in figure 2; do the utility model discloses chip package structure's section schematic diagram. The chip comprises a chip body 100 with an active surface, wherein the thickness of the chip body 100 is 25-150 micrometers. The chip electrode 101 is disposed on the active surface of the chip body 100, and the protection layer 200 is disposed on the active surface of the chip and the upper surface of the chip electrode 101, where the protection layer 200 includes, but is not limited to, a passivation layer and an insulating layer. The passivation layer 200 has a passivation opening 201 above the chip electrode 101, and a metal bump 300 is disposed in the passivation opening 201. The metal bump 300 is made of a metal material containing Ti, Cu, Ni, Sn, Au elements, and the height of the metal bump 300 is usually 2 to 100 μm.

The metal bump 300 is connected to the chip electrode 101 through the protective layer opening 201. The cross-sectional shape of the metal bump 300 is designed according to actual needs, including but not limited to rectangular, circular, and oval.

The adhesive layer 601 and the seed layer 602 are sequentially disposed on the back surface of the chip body 100, and the adhesive layer 601 covers the back surface of the chip body 100. The cross section of the seed layer 602 is smaller than that of the chip body 100 and/or that of the adhesive layer 601, and the peripheral edge of the lower surface of the adhesive layer 601 is exposed; the seed layer 602 includes but is not limited to Cu and Ni, and the thickness thereof is 0.01 to 1 μm. Adhesion layer 601 includes but is not limited to Cr, Ti, TiW, V, NiV.

The lower surface of the seed layer 602 is sequentially provided with a back gold block 600 and a graphene layer 610, and the coverage areas of the back gold block and the graphene layer are equal.

The material of the back gold block 600 is generally multilayer materials such as TiNiAg, TiNiAgNi, CrCu, CrCuCr, TiCu, TiCuTi, TiCuNi and the like; the thickness of the backing gold block 600 is usually 10 to 100 μm.

The cladding layer 700 covers the exposed surfaces of the gold-backed block 600 and the graphene layer 610, and extends upward to the peripheral edge of the lower surface of the adhesive layer 601 to support and protect the same. The coating layer 700 is made of thermosetting polymer materials, including but not limited to epoxy resin and phenolic resin.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only a detailed description of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A packaging structure of a chip comprises a chip body (100) with an active surface, the active surface of the chip body (100) is provided with a chip electrode (101),

the chip structure is characterized in that a protective layer (200) is arranged on the active surface of the chip body (100) and the upper surface of the chip electrode (101), a protective layer opening (201) is formed in the protective layer (200) above the chip electrode (101), a metal bump (300) is arranged in the protective layer opening (201), and the metal bump (300) is connected with the chip electrode (101) through the protective layer opening (201);

an adhesion layer (601) and a seed layer (602) are sequentially arranged on the back surface of the chip body (100), and the adhesion layer (601) covers the back surface of the chip body (100);

the cross section of the seed layer (602) is smaller than that of the chip body (100) and/or that of the adhesive layer (601), and the peripheral edge of the lower surface of the adhesive layer (601) is exposed;

the lower surface of the seed layer (602) is sequentially provided with a back gold block (600) and a graphene layer (610), and the coverage areas of the back gold block and the graphene layer are equal;

the graphene-based graphene adhesive further comprises a coating layer (700), wherein the coating layer (700) coats the exposed surfaces of the gold-backed block (600) and the graphene layer (610) and extends upwards to the peripheral edge of the lower surface of the adhesive layer (601).

2. The chip packaging structure of claim 1, wherein the adhesive layer (601) has a thickness of 0.01-3 μm.

3. The chip package structure of claim 1, wherein the seed layer (602) has a thickness of 0.01 to 1 μm.