CN210607261U

CN210607261U - Ultra-low power semiconductor power device

Info

Publication number: CN210607261U
Application number: CN201922184725.1U
Authority: CN
Inventors: 丁磊; 侯宏伟
Original assignee: Jiangsu Xiechang Electronic Technology Co ltd; Zhangjiagang Kaicheng Software Technology Co ltd; ZHANGJIAGANG CASS SEMICONDUCTOR CO Ltd
Current assignee: Jiangsu Xiechang Electronic Technology Co ltd; Zhangjiagang Kaicheng Software Technology Co ltd; ZHANGJIAGANG CASS SEMICONDUCTOR CO Ltd
Priority date: 2019-12-09
Filing date: 2019-12-09
Publication date: 2020-05-22
Anticipated expiration: 2029-12-09

Abstract

The utility model provides an ultra-low power semiconductor power device, it is opened at semiconductor substrate's N type epitaxial layer upper surface has three slot, the ditch inslot fills up the field oxide layer, electrically conductive polycrystalline silicon is filled in the field oxide layer, first slot upper half inner wall and periphery, the second, third slot top and peripheral cover gate oxide layer, gate polycrystalline silicon is filled up in the gate oxide layer of first slot, gate oxide layer top covers the oxide layer, first slot peripheral oxide layer top covers source electrode metal downthehole to first source electrode, first slot top covers gate electrode metal downthehole to the gate electrode, second slot top covers source electrode metal downthehole to second source electrode, the lower surface of N type substrate covers back electrode. The utility model discloses a 4 layers of light cover number of piles, compare the light cover technique on current 6-7 layers, reduced the light cover number of piles, under the prerequisite of guaranteeing the performance, effectively reduced manufacturing cost.

Description

Ultra-low power semiconductor power device

Technical Field

The utility model belongs to the technical field of the semiconductor, especially, ultra-low power semiconductor power device.

Background

The groove power device has the advantages of high integration level, low on-resistance, high switching speed, small switching loss and wide application in various power management and switching. With the increasing importance of the country on energy conservation and emission reduction, the requirements on the loss and the conversion efficiency of a power device are higher and higher, and the conduction loss is mainly influenced by the size of the conduction resistance; wherein, the smaller the characteristic on-resistance is, the smaller the conduction loss is; switching losses are mainly affected by the gate charge, the smaller the switching losses. Therefore, reducing the on-resistance and the gate charge is two effective ways to reduce the power consumption of the power device, so that the energy can be used more efficiently, and more consumed electric energy can be reduced.

There are generally two methods to reduce the characteristic on-resistance:

the first method is to increase the total effective width of the unit cell by improving the unit cell density, thereby achieving the purpose of reducing the characteristic on-resistance. However, after the unit cell density is increased, the corresponding gate charge is also increased, and the on-resistance and the gate charge cannot be reduced simultaneously;

the second method is realized by improving the doping concentration of the epitaxial wafer and reducing the thickness of the epitaxial layer, but the method can reduce the source-drain breakdown voltage, so that the method is limited by the breakdown voltage by only depending on reducing the doping concentration/reducing the thickness of the epitaxial layer.

The prior art is a power device capable of reducing on-resistance and grid charge, namely a trench type double-layer Gate power field effect transistor (Split Gate MOSFET), and the prior patent ZL 201110241526.5 discloses a power MOSFET device with a novel trench structure and a manufacturing method thereof, wherein cells in an element area adopt a trench structure, an insulating oxide layer is arranged in the trench of the cells, and the thickness of a second insulating Gate oxide layer in the trench of the cells is larger than that of a first insulating Gate oxide layer; conductive polysilicon is deposited in the cell trench, and the extending distance of the first conductive polysilicon in the cell trench is greater than the extending distance of the second conductive polysilicon; the notch of the cellular groove is covered by the insulating medium layer, a second contact hole filling metal is filled in the source contact hole, and the second contact hole filling metal is in ohmic contact with the first conduction type injection region and the second conduction type layer; a source metal is arranged above the cellular trench and is electrically connected with the second contact hole filling metal; the first conductive polysilicon is connected with the source electrode metal in an equipotential manner, so that low on-resistance is realized, gate leakage charges Qgd are small, switching speed is high, switching loss is low, the process is simple, and cost is low.

SUMMERY OF THE UTILITY MODEL

The utility model solves the technical problem that: the ultra-low power semiconductor power device adopts 4 layers of light shield layers, reduces the number of the light shield layers compared with the prior light shield technology of 6-7 layers, and effectively reduces the manufacturing cost on the premise of ensuring the performance.

Realize the utility model discloses the technical solution of purpose does:

an ultra-low power semiconductor power device comprises a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped N-type substrate and a lightly doped N-type epitaxial layer, the first surface is the upper surface of the N-type epitaxial layer, the second surface is the lower surface of the N-type substrate, and the second surface is covered with a back electrode; the first surface is provided with a first groove, a second groove and a third groove in the vertical direction, the lower half part in the first groove, the second groove and the third groove are filled with field oxide layers, and conductive polycrystalline silicon is filled in the field oxide layers; the upper part of the inner wall of the upper half part of the first groove and the first surface at the periphery of the inner wall, the first surface above the field oxide layer in the second groove and the first surface at the periphery of the field oxide layer in the second groove, the field oxide layer in the third groove and the first surface at the periphery of the field oxide layer in the third groove are covered with gate oxide layers, gate polycrystalline silicon is filled in the gate oxide layer of the first groove, the oxide layer is covered above the gate oxide layer, and P-type impurity injection layers are arranged below the first surface at the periphery of the first groove, below the first surface at the periphery of the second groove and below the first surface at the periphery of the third groove; a source electrode metal covers the oxide layer on the periphery of the first groove, the source electrode metal extends downwards into the first source electrode hole, and the first source electrode hole penetrates through the oxide layer and the gate oxide layer to reach the upper part of the P-type impurity injection layer on the periphery of the first groove; a grid metal covers the upper part of the first groove, the grid metal extends downwards into a grid hole, and the grid hole penetrates through the oxide layer until reaching the grid polysilicon; a source electrode metal covers the second groove, the source electrode metal extends downwards into a second source electrode hole, and the second source electrode hole penetrates through the oxide layer, the gate oxide layer and the field oxide layer on the upper half part in the second groove to reach the conductive polycrystalline silicon in the second groove; the source electrode metal is not connected with the grid electrode metal; an N + type impurity layer is arranged between the first source electrode hole and the first groove and between the first source electrode hole and the second groove, and a P + type impurity layer is arranged at the bottom of the first source electrode hole.

Compared with the prior art, the utility model adopts the above technical scheme, the technical effect who has is: the utility model discloses on the performance of guaranteeing the device and the basis of reliability, reduce the light shield number of piles to 4 layers, the low power dissipation, manufacturing process is simple, effectively reduces manufacturing cost.

Drawings

FIG. 1 is a schematic diagram of the structure after deposition of conductive polysilicon;

fig. 2 is a schematic structural diagram after the field oxide layer is etched back;

FIG. 3 is a schematic diagram of the structure after gate polysilicon deposition and impurity implantation;

FIG. 4 is a schematic diagram of the structure after an oxide layer is deposited and impurities are implanted;

figure 5 is a schematic view of the structure after metal deposition.

Reference signs mean: 1: n-type substrate, 2: n-type epitaxial layer, 3: first trench, 4: second trench, 5: third groove, 6: field oxide layer, 7: conductive polysilicon, 8: gate oxide, 9: gate polysilicon, 10: p-type impurity implantation layer, 11: oxide layer, 12: first source hole, 13: second source hole, 14: gate hole, 15: n + -type impurity layer, 16: p + type impurity layer, 17: source metal, 18: gate metal, 19: and a back electrode.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention, and should not be construed as limiting the present invention.

An ultra-low power semiconductor power device, as shown in fig. 5, comprises a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped N-type substrate 1 and a lightly doped N-type epitaxial layer 2, a first surface is an upper surface of the N-type epitaxial layer 2, a second surface is a lower surface of the N-type substrate 1, and the second surface is covered with a back electrode 19.

The first surface is provided with a first groove 3, a second groove 4 and a third groove 5 in the vertical direction, the lower half part of the first groove 3, the second groove 4 and the third groove 5 are filled with a field oxide layer 6, and the field oxide layer 6 is filled with conductive polysilicon 7.

The upper half part of the inner wall of the first groove 3 and the first surface at the periphery thereof, the first surface above the field oxide layer 6 and the first surface at the periphery thereof in the second groove 4, the first surface above the field oxide layer 6 and the first surface at the periphery thereof in the third groove 5 are covered with a gate oxide layer 8, the gate oxide layer 8 of the first groove 3 is filled with gate polysilicon 9, the oxide layer 8 is covered with an oxide layer 11, and the P-type impurity injection layers 10 are respectively arranged below the first surface at the periphery of the first groove, below the first surface at the periphery of the second groove and below the first surface at the periphery of the third groove.

A source metal 17 covers the oxide layer 11 at the periphery of the first trench 3, the source metal 17 extends downwards into the first source hole 12, and the first source hole 12 penetrates through the oxide layer 11 and the gate oxide layer 8 to reach the upper part of the P-type impurity injection layer 10 at the periphery of the first trench 3; the gate metal 18 covers the first trench 3, the gate metal 18 extends downwards into the gate hole 14, and the gate hole 14 penetrates through the oxide layer 11 to the gate polysilicon 9; the second trench 4 is covered with a source metal 17, the source metal 17 extends downwards into the second source hole 13, the second source hole 13 penetrates through the oxide layer 11, the gate oxide layer 8, the field oxide layer 6 on the upper part in the second trench 4 to the conductive polysilicon 7 in the second trench 4, and the source metal 17 is not connected with the gate metal 18.

An N + type impurity layer 15 is arranged between the first source hole 12 and the first groove 3 and between the first source hole 12 and the second groove 4, and a P + type impurity layer 16 is arranged at the bottom of the first source hole 12.

The utility model also provides a method of preparing above-mentioned ultralow power semiconductor power device, including following step:

step 1, providing an N-type semiconductor substrate with two opposite surfaces, wherein the N-type semiconductor substrate comprises a heavily doped N-type substrate 1 and a lightly doped N-type epitaxial layer 2, the upper surface of the N-type epitaxial layer 2 is defined as a first surface, the lower surface of the N-type substrate 1 is defined as a second surface, the first surface is etched to form a groove in the vertical direction, and the groove comprises a first groove 3, a second groove 4 and a third groove 5;

step 2: growing a field oxide layer 6 on the first surface, wherein the field oxide layer 6 covers the inner wall of the first groove 3 and the first surface of the periphery thereof, the inner wall of the second groove 4 and the first surface of the periphery thereof, and the inner wall of the third groove 5 and the first surface of the periphery thereof;

and step 3: depositing and etching back the conductive polysilicon 7, so that the lower parts of the first trench 4, the second trench 5 and the third trench 6 are filled with the conductive polysilicon 7, as shown in fig. 1;

and 4, step 4: depositing and etching back a field oxide layer 6 in the first trench 3, the second trench 4 and the third trench 5, so that the field oxide layer 6 is filled above the conductive polysilicon 7 in the first trench 3, the second trench 4 and the third trench 5, as shown in fig. 2;

and 5: performing secondary etching on the field oxide layer 6 at the upper half part in the first trench 3 to remove the field oxide layer 6 at the upper half part in the first trench 3;

step 6: growing a gate oxide layer 8 on the first surface, wherein the gate oxide layer 8 covers the upper half inner wall of the first groove 3 and the first surface on the periphery thereof, the first surface on the upper side and the periphery of the field oxide layer 6 in the second groove 4, and the first surface on the upper side and the periphery of the field oxide layer 6 in the third groove 5;

and 7: depositing and etching back the gate polysilicon 9 in the first trench 3 to fill the gate polysilicon 9 in the upper half part of the first trench 4;

and 8: injecting P-type impurities from the gate oxide layer 8 and annealing, and forming a P-type impurity layer 10 below the first surface at the periphery of the first trench 3, below the first surface at the periphery of the second trench 4 and below the first surface at the periphery of the third trench 5, wherein the P-type impurity injection layer 10 is positioned at the upper part of the N-type epitaxial layer 2, as shown in FIG. 3;

and step 9: depositing an oxide layer 11 above the gate oxide layer 8 and above the gate polysilicon 9, defining a lead hole region through hole photoetching, etching and penetrating the oxide layer 11 and the gate oxide layer 8 to the upper part of a P-type impurity layer 10 on the periphery of the first groove 3 to form a first source hole 12, etching and penetrating the oxide layer 11, the gate oxide layer 8 and a field oxide layer 6 on the upper half part in the second groove 4 to a conductive polysilicon 7 in the second groove 4 to form a second source hole 13, and etching the oxide layer 11 to the gate polysilicon 9 to form a gate hole 14;

step 10: injecting N + type impurities at an angle from the inside of the first source hole 12 and annealing, forming an N + type impurity layer 15 between the first source hole 12 and the first trench 3 and between the first source hole 12 and the second trench 4, injecting P + type impurities from the bottom of the first source hole 12 and annealing, and forming a P + type impurity layer 16 at the bottom of the first source hole 12, as shown in fig. 4;

step 11: metal is deposited in the first source hole 12 and its peripheral portion of the oxide layer 11, in the second source hole 13 and its peripheral portion of the oxide layer 11 to form a source metal 17, metal is deposited in the gate hole 14 and its peripheral portion of the oxide layer 11 to form a gate metal 18, and metal is deposited on the second surface to form a back electrode 19, as shown in fig. 5.

The foregoing is only a part of the embodiments of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements can be made without departing from the principles of the present invention, and these improvements should be regarded as the protection scope of the present invention.

Claims

1. The ultra-low power semiconductor power device is characterized by comprising a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped N-type substrate (1) and a lightly doped N-type epitaxial layer (2), the first surface is the upper surface of the N-type epitaxial layer (2), the second surface is the lower surface of the N-type substrate (1), and the second surface is covered with a back electrode (19);

the first surface is provided with a first groove (3), a second groove (4) and a third groove (5) in the vertical direction, the lower half part of the first groove (3), the second groove (4) and the third groove (5) are filled with field oxide layers (6), and the field oxide layers (6) are filled with conductive polysilicon (7);

the upper half part of the inner wall of the first groove (3) and the first surface of the periphery of the inner wall, the first surface of the upper part of the field oxide layer (6) in the second groove (4) and the first surface of the periphery of the field oxide layer, the upper part of the field oxide layer (6) in the third groove (5) and the first surface of the periphery of the field oxide layer are covered with a gate oxide layer (8), the gate oxide layer (8) of the first groove (3) is filled with grid polysilicon (9), the oxide layer (11) is covered on the gate oxide layer (8), and P-type impurity injection layers (10) are arranged below the first surface of the periphery of the first groove (3), the first surface of the periphery of the second groove (4) and the first surface of the periphery of the third groove (5);

a source metal (17) covers the oxide layer (11) on the periphery of the first trench (3), the source metal (17) extends downwards into a first source hole (12), and the first source hole (12) penetrates through the oxide layer (11) and the gate oxide layer (8) to reach the upper part of a P-type impurity injection layer (10) on the periphery of the first trench (3); a grid metal (18) covers the first groove (3), the grid metal (18) extends downwards into a grid hole (14), and the grid hole (14) penetrates through the oxide layer (11) to reach the grid polycrystalline silicon (9); a source metal (17) covers the second trench (4), the source metal (17) extends downwards into a second source hole (13), and the second source hole (13) penetrates through the oxide layer (11), the gate oxide layer (8), the field oxide layer (6) on the upper half part in the second trench (4) and reaches the conductive polysilicon (7) in the second trench (4); the source metal (17) is not connected with the gate metal (18);

an N + type impurity layer (15) is arranged between the first source electrode hole (12) and the first groove (3) and between the first source electrode hole (12) and the second groove (4), and a P + type impurity layer (16) is arranged at the bottom of the first source electrode hole (12).