CN210467836U

CN210467836U - Voltage-adjustable bidirectional ESD protection device

Info

Publication number: CN210467836U
Application number: CN201921284851.8U
Authority: CN
Inventors: 杨珏琳; 宋文龙; 张鹏
Original assignee: Chengdu Jilaixin Technology Co ltd
Current assignee: Chengdu Jilaixin Technology Co ltd; Jiangsu Jilai Microelectronics Co ltd
Priority date: 2019-08-09
Filing date: 2019-08-09
Publication date: 2020-05-05
Anticipated expiration: 2029-08-09

Abstract

The utility model discloses a two-way ESD protection device of voltage adjustable, including N type substrate, it has first P type epitaxial layer to grow on the N type substrate, and the P type barrier layer that diffusion formed is poured into to first P type epitaxial layer, and the second time P type epitaxial layer of growth on the P type barrier layer, the N + doping layer that diffusion formed is poured into to second time P type epitaxial layer surface, and the isolated groove runs through NPN structure, is equipped with insulating medium layer on the isolated groove, is equipped with positive metal electrode on N + doping layer and the insulating medium layer, and N type substrate bottom is equipped with back metal electrode. Greatly reducing chip cost and improving process compatibility.

Description

Voltage-adjustable bidirectional ESD protection device

Technical Field

The utility model relates to an electron science and technical field specifically are a voltage adjustable two-way ESD protection device.

Background

The electrostatic discharge (ESD) phenomenon is widely present in daily environments, and is a real fatal threat to precise integrated circuits, and is one of the important causes for damage and even failure of integrated circuit products. Integrated circuit products are highly susceptible to ESD during their manufacture, fabrication, assembly, and operation, resulting in internal damage and reduced reliability. And the application environment of the capacitor has corresponding requirements on parameters such as capacitance, breakdown voltage, clamping characteristics and the like.

The parameter requirements of the system for the ESD protection device are different for different applications. The corresponding ESD protection levels are also classified into voltage levels of 3, 5V, 7V, 12V, 24V, 36V, and the like according to the operating voltage. Different requirements are also imposed on the capacitor according to the speed of data transmission, and the cost can be reduced by adopting an ESD protection device of a common capacitor series aiming at direct current transmission or low-speed data transmission; and for the requirement of telling the AC transmission of USD3.0 and above, an ESD protection device with ultra-low capacitance is needed. For different application environments, the clamping voltage of the ESD is required according to the load working area of the system, for example, for automobile bus network protection application, the clamping voltage of the ESD is required to be low but cannot be lower than the power supply voltage.

As devices commonly used for ESD protection for integrated circuits, there are diodes, GGNMOS (gate grounded NMOS), BJT (triode), SCR (silicon controlled rectifier), etc. In certain applications, however, it is desirable to have ESD protection devices with a specific trigger voltage and a high current sinking capability, while also maintaining a voltage level greater than the voltage level of the device to be used to prevent system startup failure. Because the flyback voltage of the SCR is very low, the SCR structure cannot be used for ESD protection of this kind of specific requirements, so the BJT structure is used to meet the requirement of large leakage current.

SUMMERY OF THE UTILITY MODEL

The utility model aims at not enough among the prior art, provide a manufacturing approach of the controllable two-way ESD protection device of high symmetry performance and flyback voltage, through the concentration of adjusting twice P type epitaxial layer in the vertical NPN structure and the N type concentration of cominging in and going out on surface, match the physical characteristic of positive reverse PN junction as far as possible to obtain high symmetry. The amplification factor of the NPN tube is adjusted by adjusting the implantation dose of the boron buried layer after the first time of epitaxy, so that the voltage can be kept controllable.

The technical scheme of the utility model is that: a voltage-adjustable bidirectional ESD protection device comprises an N-type substrate, a first P-type epitaxial layer, a second P-type epitaxial layer, a P-type barrier layer, an N + doping region, an isolation groove, an isolation dielectric layer, a front metal electrode and a back metal electrode, wherein the first P-type epitaxial layer grows on the N-type substrate, the P-type barrier layer formed by injecting and diffusing the first P-type epitaxial layer, the second P-type epitaxial layer grows on the P-type barrier layer, the N + doping layer formed by injecting and diffusing the surface of the second P-type epitaxial layer penetrates through an NPN structure, an insulation dielectric layer is arranged on the isolation groove, the front metal electrode is arranged on the N + doping layer and the insulation dielectric layer, and the back metal electrode is arranged at the bottom of the N-type substrate.

A manufacturing method of a voltage-adjustable bidirectional ESD protection device comprises the following steps:

step 1: preparing an N-type substrate, and growing a first P-type epitaxial layer on the N-type substrate;

step 2: growing a primary sacrificial oxide layer on the primary P-type epitaxial layer, injecting primary P-type impurities at high energy, entering a furnace tube for primary high-temperature propulsion, and increasing the high-concentration junction depth of the P-type impurities on the epitaxial surface of the P-type base region to form a P-type potential barrier layer;

and step 3: firstly, purging HCL gas in the furnace, removing a surface oxide layer, and growing a second P-type epitaxial layer;

and 4, step 4: growing a sacrificial oxide layer on the surface of the base region of the P-type epitaxial layer for the second time, injecting N-type impurities of high-energy large beam for one time to form an N + doped layer, annealing at high temperature, enhancing diffusion by adopting OED (organic optical diode) oxidation, increasing the junction depth of a PN junction on the surface, and growing an oxide layer with a certain thickness;

and 5: photoetching to form a deep groove area pattern, and depositing an isolation medium layer to form a deep groove isolation area and an isolation medium layer;

step 6: and photoetching and etching the front surface to open a contact hole area, depositing a metal layer, photoetching and etching the front surface metal, depositing a passivation layer, photoetching and etching a lead wire welding area, namely a front surface metal electrode, and thinning the wafer to finish the back surface metal alloy, namely a back surface metal electrode.

Preferably, the high-temperature annealing temperature in the step 2 is 1000-1100 ℃, preferably 1050 ℃, the annealing time is 30-120 min, preferably 60min, the implanted impurities can be boron, gallium and indium, the implanted impurities are boron, the implantation angle is 7 degrees, the implantation energy is 600-950 Kev, preferably 800Kev, and the implantation dose is 5e 14-2 e15/cm 2.

Preferably, in the second P-type epitaxial layer in step 3, the doping elements are boron, gallium and indium, preferably boron, the thickness of the second P-type epitaxial layer is 5-10 um, preferably 8um, the resistivity of the second P-type epitaxial layer is 0.2-1 Ω · cm, and preferably the resistivity of the second P-type epitaxial layer is 0.5 Ω · cm.

Preferably, the high-temperature annealing condition in the step 4 is 1050-1150 ℃, preferably 1100 ℃, for 60-150 min, preferably 90min, the implanted impurity element can be phosphorus or arsenic, preferably phosphorus, the implantation energy is 100-200 Kev, preferably 160Kev, and the implantation dose is 1e 15-5 e15/cm²Preferably 2e15/cm²And carrying out oxidation enhanced diffusion under the condition of 1050 ℃ wet oxygen, wherein the temperature is 1000-1100 ℃, the preferential 1050 ℃ wet oxygen grows an oxide layer with the thickness of 3000 Å -5000 Å, the preferential thickness is 4000 Å, and the silicon dioxide with the thickness of 4000 Å is grown as a deep groove mask while the N + junction depth is further increased.

Preferably, in the step 5, a dry etching deep groove is adopted, 600-1500 Å silicon dioxide is grown, the preferable thickness is 1000 Å, then an isolation medium layer is deposited by adopting a low-pressure tetraethoxysilane growth process, and then a layer of PSG isolation medium is deposited.

The utility model discloses a two-way 24V ESD protection device, the vertical NPN triode structure of tradition relatively has improved still kept the characteristic that the triode discharge capacity is strong when flyback voltage crosses the characteristic low excessively. Compared with the traditional two-diode packaging mode, the chip cost is greatly reduced, and the packaging cost is reduced.

The utility model discloses an useful part: 1. the utility model discloses an amplification factor of NPN pipe can be adjusted to P type potential barrier layer, makes NPN flyback voltage controllable, prevents that overvoltage pulse from coming and keeping the open mode after the temporary protection device flyback is less than mains voltage to provide the protection to the power.

2. The utility model discloses the controllable ESD protection device's of two-way flyback voltage method of making compares with the device of present same performance, and chip area can reduce 40%, and only needs to adopt single chip, and the cost reduces by a wide margin.

3. The utility model discloses the controllable ESD protection device's of two-way flyback voltage method of making can make and hang down to from 5V, high two-way structure to operating voltage more than 36V to only need adjust first, second time P type epitaxial layer concentration and thickness, alright realize the regulation of two electric voltages. Some unconventional specific ESD protection requirements (such as 7V/12V) with bidirectional voltage asymmetry can be completed on one vertical chip, thereby greatly reducing the chip cost and improving the process compatibility.

4. The utility model discloses the controllable ESD protection device's of two-way flyback voltage method of making can more cross chip area's method, can use in the protection of general high-speed signal, provides a solution for low-cost two-way protection.

Drawings

FIG. 1 is a sectional structure diagram of the ESD protection device with controllable bidirectional voltage

FIG. 2 is a schematic diagram of a conventional dual-chip packaged bi-directional ESD protection device package layout;

FIG. 3 is a cross-sectional view of a conventional single-chip packaged bi-directional ESD protection device structure;

FIG. 4 is a comparison of I-V curves of the three structures shown in FIG. 1, FIG. 2, and FIG. 3.

FIG. 5 illustrates the first step of the process of the present invention, i.e., preparing the N-type substrate, cleaning the wafer, and growing the first P-type epitaxial layer;

FIG. 6 is a second step of the process of the present invention, i.e. high energy implantation of P-type impurities and high temperature annealing to form a P-type barrier layer;

FIG. 7 shows the third step of the process of the present invention, that is, the wafer is fed into the furnace to grow the second P-type epitaxial layer

FIG. 8 shows the fourth step of the process of the present invention, i.e. injecting high energy beam of N + impurities, annealing at high temperature and promoting diffusion by combining with oxidation, and growing an oxide layer with a certain thickness on the surface;

FIG. 9 shows a fifth step of the process of the present invention, wherein the oxide layer is grown in the double deep trenches and the insulating dielectric layer is deposited

Fig. 10 shows a sixth step of the process of the present invention, which is to open the metal contact hole, deposit the front metal to form the electrode by photolithography, thin and metalize the back.

Fig. 11 is a sectional view of an improved structure of the present invention.

The structure comprises a substrate 101, a substrate 102, a first P-type epitaxial layer, a barrier layer 103, a second P-type epitaxial layer 104, an N + doped layer 105, an isolation groove 106, an oxide layer 107B, an insulating medium layer 107, a front metal electrode 108 and a back metal electrode 109.

Detailed Description

In order to deepen the understanding of the present invention, the following detailed description is given with reference to the accompanying drawings, which are only used for explaining the present invention and do not constitute a limitation to the protection scope of the present invention.

As shown in fig. 1, a voltage-adjustable bidirectional ESD protection device includes an N-type substrate 101, a first P-type epitaxial layer, a second P-type epitaxial layer, a P-type barrier layer, an N + doped region, an isolation trench, an isolation dielectric layer, a front metal electrode, and a back metal electrode, where the first P-type epitaxial layer 102 is grown on the N-type substrate 101, the first P-type barrier layer 103 is formed by injecting and diffusing the first P-type epitaxial layer 102, the second P-type epitaxial layer 104 is grown on the P-type barrier layer 103, and the N + doped layer 105 is formed by injecting and diffusing the second P-type epitaxial layer 104, the isolation trench 106 penetrates through an NPN structure, the isolation trench 106 is provided with an insulation dielectric layer 107, the N + doped layer 105 and the insulation dielectric layer 107 are provided with the front metal electrode, and the bottom of the N-type.

step 1: as shown in fig. 5, an N-type substrate 101 is prepared, a doping element is boron, the thickness of the doping element is 8um, the resistivity of the doping element is 0.5 Ω · cm, a first P-type epitaxial layer 102 grows on the N-type substrate at 1180 ℃, and the N-type substrate 101 and the first P-type epitaxial layer form a back PN junction;

step 2, as shown in FIG. 6, a sacrificial oxide layer of 1000 Å is grown once on the first P-type epitaxial layer 102, and a P-type impurity is implanted once with high energy, preferably boron, at an implantation angle of 7 DEG and an implantation energy of 800Kev, at an implantation dose of 1e15/cm²And then the silicon wafer enters a furnace tube to carry out high-temperature propulsion, the high-temperature annealing temperature is 1050 ℃, the annealing time is one hour, the high-concentration junction depth of a P-type impurity on the epitaxial surface of the P-type base region is increased, a P-type potential barrier layer is formed, the amplification coefficient of the NPN tube can be adjusted by the P-type potential barrier layer, the flyback voltage of the NPN tube is controllable, and the situation that an overvoltage pulse temporarily protects the device from keeping an on state after the flyback is lower than the power voltage is prevented, so that the power supply is protected;

and step 3: as shown in fig. 7, the HCL gas of the advanced furnace is purged to remove the surface oxide layer, and a second P-type epitaxial layer 104 is grown, and the resistivity and N + doped layer of the second P-type epitaxial layer form a front PN junction, preferably, the doping element is boron, the thickness of which is 8um, and the resistivity of which is 0.5 Ω · cm, so as to achieve bidirectional voltage uniformity;

and 4, step 4: as shown in fig. 8, a sacrificial oxide layer is grown once again on the surface of the base region of the second P-type epitaxial layer 104, and an N-type impurity with high energy and large beam current is implanted once to form an N + doped layer 105, the implanted impurity element is phosphorus, the implantation energy is 160Kev, and the implantation dose is 2e15/cm²Annealing at high temperature and adopting OED oxidation to enhance diffusion at 1100 ℃ for 90min, then, turning the furnace temperature to 1050 ℃, growing an oxide layer of 4000 Å by wet oxygen, wherein the oxide layer provides a hard mask for subsequent deep trench etching, and oxidation propulsion can further push an N + diffusion junction by using an oxidation enhanced diffusion effect, increase the junction depth of a surface PN junction and grow an oxide layer 107B with a certain thickness;

step 5, as shown in FIG. 9, photoetching to form a deep groove area pattern, etching the groove with the width of 1um, the interval of 2um and the depth of 25um, completely isolating the longitudinal NPN, growing a layer of silicon dioxide in a thermal sample after the deep groove etching is finished, adopting wet oxygen to grow with the thickness of 600 Å, then adopting a low-pressure tetraethoxysilane growth process (LPTEOS) to deposit a medium layer of 6000 Å, then depositing a layer of phosphosilicate glass PSG of 6000 Å, depositing an isolation medium layer to form a deep groove isolation area 106 and an isolation medium layer 107 isolation area, penetrating the whole N + doped area to the N-type substrate, and the combination method can improve the filling effect of the isolation medium and improve the reliability of the medium layer;

step 6: as shown in fig. 10, a contact hole region is defined by lithography and etched by a wet and dry process, a Ti/TiN metal layer is deposited, then 4um AlSiCu alloy is deposited on the contact hole region, the contact resistance is reduced, the failure proportion of metal overheating can be effectively reduced, the front metal is etched and etched, a passivation layer is deposited, a lead wire welding region, namely the front metal electrode 108 is etched and etched, an insulating medium layer is positioned between an isolation groove and the front electrode, and the back metal alloy, namely the back metal electrode 109 is finished by thinning the sheet.

As shown in fig. 4, fig. 4 is a comparison of the I-V characteristics of the three structures, and the breakdown voltages of the three structures are all 26V. It can be seen that the current-voltage relationship of the structure in the third layer in the large current region is very different (the curve is a two-dimensional simulated line current), wherein the current capability of a single PN junction is obviously weaker than that of a triode structure because of no amplification effect of the triode; the NPN structure with the P-type barrier layer provided by the utility model has the advantages of strong current capability of the conventional NPN structure and no negative resistance effect of the diode.

Fig. 11 is a sectional view of an improved structure of the present invention. The P-type barrier layer 103 and the N + doped layer 105 are directly implanted without photolithography to define the region, so that the lowest cost can be realized under the basic structure.

Utilize above-mentioned the utility model discloses a controllable ESD protection device's of two-way voltage manufacturing method only needs concentration and thickness that the first time of adjustment, second time P type base region epitaxial layer, can produce and hang down to 5V, and the controllable two-way ESD protection device of flyback voltage more than up to 50V can realize the two-way ESD protection of several amperes to several hundred amperes's each current capability simultaneously through adjusting the domain.

Claims

1. The utility model provides a voltage adjustable two-way ESD protection device, includes N type substrate, first P type epitaxial layer, second P type epitaxial layer, P type potential barrier layer, N + doping area, isolation groove, isolation dielectric layer, front metal electrode, back metal electrode, its characterized in that: the high-power-consumption N-type epitaxial growth device comprises an N-type substrate, and is characterized in that a first P-type epitaxial layer grows on the N-type substrate, the first P-type epitaxial layer is injected into a P-type barrier layer formed by diffusion, a second P-type epitaxial layer grows on the P-type barrier layer, an N + doped layer formed by diffusion is injected into the surface of the second P-type epitaxial layer, an isolation groove penetrates through an NPN structure, an insulating medium layer is arranged on the isolation groove, front metal electrodes are arranged on the N + doped layer and the insulating medium layer, and a back metal electrode is arranged at the bottom.