CN110444541A - A kind of adjustable bidirectional ESD protective device of voltage and preparation method thereof - Google Patents
A kind of adjustable bidirectional ESD protective device of voltage and preparation method thereof Download PDFInfo
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- 230000001681 protective effect Effects 0.000 title claims abstract description 27
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005036 potential barrier Methods 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000001012 protector Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention discloses a kind of adjustable bidirectional ESD protective device of voltage; including N-type substrate; growth has first time p-type epitaxial layer in N-type substrate; first time p-type epitaxial layer injects the p-type potential barrier barrier layer diffuseed to form; second of the p-type epitaxial layer grown on p-type potential barrier barrier layer, second of p-type epi-layer surface inject the N+ doped layer diffuseed to form, and isolation channel is equipped with insulating medium layer; N+ doped layer and insulating medium layer are equipped with front metal electrode, and N-type substrate bottom is equipped with back metal electrode.Step: 1: preparing N-type substrate, first time p-type epitaxial layer is grown in N-type substrate；2: on first time p-type epitaxial layer, growing a sacrificial oxide layer, form p-type potential barrier barrier layer；Step 3: carrying out second of p-type outer layer growth；4: second p-type epitaxial layer base region surfaces regrow a sacrificial oxide layer；5: deposit spacer medium floor forms deep trench isolation area and spacer medium floor；6: deposited metal.
Description
Technical field
The present invention relates to Electronics Science and Technology field, the adjustable bidirectional ESD protective device of specifically a kind of voltage and its
Production method.
Background technique
Static discharge (ESD) phenomenon is widely present in surroundings, it is caused really for accurate integrated circuit
The threat of life is to cause IC products the damage even one of the major reasons of failure.IC products are in its production, system
Make, assemble and the course of work in be highly prone to the influence of ESD, cause interiors of products damage, reliability to reduce.And it is applied
Environment can be right, also can have corresponding requirements to parameters such as capacitor, breakdown voltage, clamping performances.
For different application, system is also different to the parameter request of ESD protective device.According to operating voltage difference, phase
The ESD protection class answered is also classified into the voltage class such as 3,5V, 7V, 12V, 24V, 36V.It is also right according to the speed of data transmission bauds
Capacitor has different requirements, and for direct current transmission or slow data transmission, the ESD protective device drop of conventional capacitive series can be used
Low cost；And exchange transmission demand is told for USD3.0 or more, need the ESD protective device of ultra-low capacitance.And it is directed to
Different application environments also has corresponding requirements to the clamp voltage of ESD, such as automobile according to the loaded work piece area of system
Bus network protection application, it is necessary to which the clamp voltage of ESD is low but cannot be below supply voltage.
For integrated circuit, be typically used as ESD protection device have diode, the GGNMOS NMOS of ground connection (grid),
BJT (triode), SCR (silicon-controlled) etc..But in certain specific applications, need ESD protective device that there is specific triggering electricity
Pressure, electric current relieving capacity is stronger, while also requiring the voltage class for keeping voltage to be greater than its application, leads to prevent locking system unlatching
Cause failure.Since the flyback voltage of SCR is extremely low, so the ESD for this kind of particular requirements is protected, SCR structure cannot be used,
Therefore reach the requirement of big leakage current using BJT structure.
Summary of the invention
The purpose of the present invention is aiming at the shortcomings in the prior art, provide a kind of high symmetrical performance and flyback voltage is controllable
The manufacturing method of bidirectional ESD protective device, by adjusting the concentration of the epitaxial layer of p-type twice in longitudinal NPN structure and the N on surface
Type enters and leaves concentration, the physical characteristic of forward and reverse PN junction is matched as far as possible, to obtain high symmetry.By adjusting outer for the first time delay
Boron buried layer implantation dosage, adjust NPN pipe amplification coefficient, thus reach keep voltage it is controllable.
The technical solution of the present invention is as follows: a kind of adjustable bidirectional ESD protective device of voltage, including N-type substrate, first time P
Type epitaxial layer, second of p-type epitaxial layer, p-type potential barrier barrier layer, N+ doped region, isolation channel, spacer medium layer, front metal electricity
Pole, back metal electrode, growth has first time p-type epitaxial layer in N-type substrate, and first time p-type epitaxial layer injects the P diffuseed to form
Type potential barrier barrier layer, second of the p-type epitaxial layer grown on p-type potential barrier barrier layer, second of p-type epi-layer surface injection diffusion
The N+ doped layer of formation, isolation channel run through NPN structure, and isolation channel is equipped with insulating medium layer, N+ doped layer and insulating medium layer
It is equipped with front metal electrode, N-type substrate bottom is equipped with back metal electrode.
A kind of production method of the adjustable bidirectional ESD protective device of voltage, including the following steps:
Step 1: preparing N-type substrate, first time p-type epitaxial layer is grown in N-type substrate；
Step 2: on first time p-type epitaxial layer, growing a sacrificial oxide layer, and p type impurity of high energy ion implantation, and enter
Boiler tube carries out a high temperature and promotes, and increases p type impurity in the high concentration junction depth of p-type base area epitaxial surface, forms p-type potential barrier and stop
Layer；
Step 3: advanced furnace HCL gas purging removes surface oxide layer, carries out second of p-type outer layer growth；
Step 4: second of p-type epitaxial layer base region surface regrows a sacrificial oxide layer, and injects a big line of high energy
N-type impurity inject to form N+ doped layer, high annealing and simultaneously use OED OXIDATION ENHANCED DIFFUSION, increase surface PN junction knot
It is deep, and grow certain thickness oxide layer；
Step 5: being lithographically formed deep trouth area figure, and deposit spacer medium floor and form deep trench isolation area and spacer medium floor；
Step 6: in positive photoetching and opening contact bore region is etched, deposited metal carries out photoetching, etching to front metal,
Passivation layer is deposited, photoetching simultaneously etches wire bond pad areas, i.e. front metal electrode, and Wafer Thinning completes back metal alloy, i.e.,
Back metal electrode.
Preferably, the high temperature anneal temperature in step 2 is 1000 ~ 1100 DEG C, and preferably 1050 DEG C, annealing time is
30min ~ 120min, preferably 60min, implanted dopant can be boron, gallium, indium, and implanted dopant is boron, 7 ° of implant angle, inject
Energy is 600 ~ 950Kev, and preferably 800Kev, implantation dosage is 5e14 ~ 2e15/cm2.
Preferably, second of p-type epitaxial layer in step 3, doped chemical is boron, gallium, indium, preferably boron, with a thickness of 5
~ 10um, preferably 8um, resistivity are 0.2 ~ 1 Ω cm, and preferably resistivity is 0.5 Ω cm.
Preferably, the high temperature annealing condition in step 4 be 1050 ~ 1150 DEG C, preferably 1100 DEG C, the time be 60min ~
150min, preferably 90min, implanted dopant element can be phosphorus, arsenic, preferably phosphorus, and Implantation Energy is 100 ~ 200Kev, preferably
For 160Kev, implantation dosage 1e15 ~ 5e15/cm2, preferably 2e15/cm2, and oxidation increasing is carried out under the conditions of 1050 DEG C of wet oxygens of combination
Strong diffusion, temperature are 1000 ~ 1100 DEG C, and preferably 1050 DEG C, wet oxygen grows 3000 ~ 5000 oxide layer, and preferred thickness is
4000, the silica of growth 4000 is as deep trouth exposure mask while further increasing N+ junction depth.
Preferably, dry etching deep trouth is used in step 5, and grows 600 ~ 1500 silica, and preferred thickness is
1000, then spacer medium layer is deposited using low pressure tetraethoxysilane growth technique, then deposit one layer of PSG spacer medium.
Two-way 24V ESD protection protection device of the invention, compares traditional longitudinal NPN triode structure, improves flyback
Triode through-current capability strong characteristic is also maintained while the characteristic of brownout.Compare the shape of traditional two diode packages
Formula significantly reduces chip cost and reduces packaging cost.
Usefulness of the present invention: 1, the amplification coefficient of the adjustable NPN pipe in p-type potential barrier barrier layer of the invention makes NPN
Flyback voltage it is controllable, prevent overvoltage pulse from carrying out interim protector part flyback lower than keeping it turned on after supply voltage, thus
Protection is provided to power supply.
2, the method for the controllable ESD protective device of two-way flyback voltage produced by the present invention, with existing same performance
Device is compared, and chip area can reduce 40%, and need to only use single chip, and cost is greatly reduced.
3, the method that the present invention manufactures the controllable ESD protective device of two-way flyback voltage can make down to from 5V, up to
The bi-directional configuration of 36V or more operating voltage, and first, second p-type epitaxial layer concentration and thickness need to be only adjusted, it can realize
The adjusting of double piezoelectric voltages.Some asymmetric specific ESD of unconventional bi-directional voltage protect (such as 7V/12V) demand, Ke Yi
It is completed on one longitudinal chip, greatly reduces chip cost and improve processing compatibility.
4, the method that the present invention manufactures the controllable ESD protective device of two-way flyback voltage can more cross the side of chip area
The two-way prevention in the protection of general high speed signal, for low cost can be used to provide a solution for method.
Detailed description of the invention
Fig. 1 is the controllable ESD protective device sectional structure chart of bi-directional voltage of the invention
Fig. 2 is the bidirectional ESD protective device package layout schematic diagram of conventional dual chip encapsulation；
Fig. 3 is the bidirectional ESD protective device structural profile illustration of conventional single-chip package；
Fig. 4 is Fig. 1, Fig. 2, Fig. 3, three kinds of structure I-V curve comparisons.
Fig. 5 is the first step process of the invention, i.e., N-type substrate prepares, former piece cleans and grows first layer p-type epitaxial layer；
Fig. 6 is the second step process of the invention, i.e. p type impurity high energy ion implantation, and high annealing forms p-type potential barrier barrier layer；
Fig. 7 is third step process of the invention, i.e. disk grows second of p-type epitaxial layer into furnace
Fig. 8 is the 4th step process of the invention, i.e. the big line injection of N+ impurity high energy, high annealing simultaneously combines OXIDATION ENHANCED DIFFUSION
Knot, surface grow certain thickness oxide layer；
Fig. 9 is the 5th step process of the invention, and double deep trouths simultaneously grow oxide layer and deposit insulating medium layer
Figure 10 be the 6th step process of the invention, open metal contact hole, deposit front metal be lithographically formed electrode, thinning back side is simultaneously
Metallization.
Figure 11 is a kind of improved structure sectional view of the invention.
Wherein 101 be N-type substrate, and 102 be first time p-type epitaxial layer, and 103 be p-type potential barrier barrier layer, and 104 be second of P
Type epitaxial layer, 105 be N+ doped layer, and 106 be isolation channel, and 107B is oxide layer, and 107 be insulating medium layer, 108 front metals electricity
Pole, 109 back metal electrodes.
Specific embodiment
In order to deepen the understanding of the present invention, it describes the specific embodiments of the present invention in detail with reference to the accompanying drawing, the reality
It applies example for explaining only the invention, does not restrict the protection scope of the present invention.
As shown in Figure 1, a kind of adjustable bidirectional ESD protective device of voltage, including N-type substrate 101, first time p-type extension
Layer, second of p-type epitaxial layer, p-type potential barrier barrier layer, N+ doped region, isolation channel, spacer medium layer, front metal electrode, the back side
Metal electrode, growth has first time p-type epitaxial layer 102 in N-type substrate 101, and the injection of first time p-type epitaxial layer 102 diffuses to form
P-type potential barrier barrier layer 103, second of the p-type epitaxial layer 104 grown on p-type potential barrier barrier layer 103, second of p-type epitaxial layer
The N+ doped layer 105 diffuseed to form is injected on 104 surfaces, and isolation channel 106 runs through NPN structure, and isolation channel 106 is equipped with dielectric
107, N+ of layer doped layer 105 and insulating medium layer 107 are equipped with front metal electrode, and 101 bottom of N-type substrate is equipped with back metal
Electrode.
A kind of production method of the adjustable bidirectional ESD protective device of voltage, including the following steps:
Step 1: as shown in figure 5, preparing N-type substrate 101, doped chemical is boron, and with a thickness of 8um, resistivity is 0.5 Ω
Cm, with 1180 DEG C of temperature growth first time p-type epitaxial layer 102, N-type substrate 101 and first layer p-type extension in N-type substrate
Layer forms back side PN junction；
Step 2: as shown in fig. 6, on first time p-type epitaxial layer 102, the sacrificial oxide layer that growth is one time 1000, and high energy is infused
Entering a p type impurity, preferred implanted dopant is boron, 7 ° of implant angle, Implantation Energy 800Kev, implantation dosage 1e15/
cm2, and enter boiler tube and carry out a high temperature propulsion, high temperature anneal temperature is 1050 DEG C, and annealing time is a hour, increases P
Type impurity forms p-type potential barrier barrier layer in the high concentration junction depth of p-type base area epitaxial surface, and p-type potential barrier barrier layer is adjustable
The amplification coefficient of NPN pipe keeps the flyback voltage of NPN controllable, prevents overvoltage pulse from carrying out interim protector part flyback lower than power supply electricity
It is kept it turned on after pressure, to provide protection to power supply；
Step 3: as shown in fig. 7, advanced furnace HCL gas purges, removing surface oxide layer, it is raw to carry out second of p-type epitaxial layer 104
Long, the resistivity and N+ doped layer of second p-type extension form front PN junction, it is preferable that and doped chemical is boron, with a thickness of
8um, resistivity is 0.5 Ω cm, to realize bi-directional voltage consistency；
Step 4: as shown in figure 8, second of 104 base region surface of p-type epitaxial layer regrows a sacrificial oxide layer, and injecting one
The N-type impurity of the secondary big line of high energy is injected to form N+ doped layer 105, and implanted dopant element is phosphorus, Implantation Energy 160Kev, injection
Dosage 2e15/cm2, high annealing simultaneously uses OED OXIDATION ENHANCED DIFFUSION simultaneously, and 1100 DEG C of temperature, time 90min, then by furnace temperature
Near 1050 degrees Celsius, the oxide layer of wet oxygen growth 4000, and oxide layer provides hard mask for subsequent deep etching, oxidation pushes away
N+ diffusion junctions further being pushed away into depth into can use OXIDATION ENHANCED DIFFUSION effect, increasing the junction depth of surface PN junction, and are grown certain
The oxide layer 107B of thickness；
Step 5: as shown in figure 9, being lithographically formed deep trouth area figure, groove etched width 1um is spaced 2um, depth 25um, will be longitudinal
NPN is isolated entirely from, and after the completion of deep etching, hot sample grows layer of silicon dioxide, uses wet oxygen growth thickness for 600, then adopt
With the dielectric layer of low pressure tetraethoxysilane growth technique (LPTEOS) deposit 6000, then one layer 6000 of phosphorus silicon is being deposited
Glass PSG, deposit spacer medium floor forms deep trench isolation area 106 and 107 isolated area of spacer medium floor runs through entire N+ doped region
To N-type substrate, this combination can be improved the filling effect of spacer medium, improve the reliability of dielectric layer；
Step 6: as shown in Figure 10, lithographic definition simultaneously etches contact bore region using wet plus dry technique, deposits one layer of Ti/TiN
Meet metal layer, then on it deposit 4um AlSiCu alloy, metal mistake can be effectively reduced while reducing contact resistance
The failure ratio of heat carries out photoetching, etching to front metal, deposits passivation layer, and photoetching simultaneously etches wire bond pad areas, i.e., positive
Metal electrode 108, for insulating medium layer between isolation channel and front electrode, piece, which is thinned, completes back metal alloy, the i.e. back side
Metal electrode 109.
As shown in figure 4, Fig. 4 is the I-V characteristic comparison of three kinds of structures, the breakdown voltage of three is 26V.As can be seen that
Structure is widely different (line current that curve is two-dimensional simulation) in the current-voltage correlation of high current region in three, wherein single PN
The enlarge-effect due to not no triode is tied, so current capacity is markedly less than triode structures；And it is proposed by the present invention with P
The NPN structure on type potential barrier barrier layer has had both the advantages of conventional NPN structure current capacity is strong and diode is without negative resistance effect.
Figure 11 is a kind of improved structure sectional view of the invention.Wherein p-type potential barrier barrier layer 103 and N+ doped layer 105
Reticle definition region is not used, is directly injected into, and can realize least cost under basic structure in this way.
Using the manufacturing method of the controllable ESD protective device of the bi-directional voltage of aforementioned present invention, only need to will adjustment for the first time,
The concentration and thickness of second of p-type base epitaxial layer can produce down to 5V, and the up to flyback voltage of 50V or more is controllable
Bidirectional ESD protective device, while by adjusting domain, the two-way of several amperes to several hundred amperes of each current capacity may be implemented
ESD protection.
Claims (6)
1. a kind of adjustable bidirectional ESD protective device of voltage, including N-type substrate, first time p-type epitaxial layer, second of p-type extension
Layer, p-type potential barrier barrier layer, N+ doped region, isolation channel, spacer medium layer, front metal electrode, back metal electrode, feature
Be: growth has first time p-type epitaxial layer in the N-type substrate, and the first time p-type epitaxial layer injects the p-type diffuseed to form
Potential barrier barrier layer, second of the p-type epitaxial layer grown on p-type potential barrier barrier layer, second of p-type epi-layer surface note
Enter the N+ doped layer diffuseed to form, the isolation channel runs through NPN structure, and the isolation channel is equipped with insulating medium layer, the N+
Doped layer and insulating medium layer are equipped with front metal electrode, and the N-type substrate bottom is equipped with back metal electrode.
2. a kind of production method of the adjustable bidirectional ESD protective device of voltage according to claim 1, which is characterized in that
Include the following steps:
Step 1: preparing N-type substrate, first time p-type epitaxial layer is grown in N-type substrate；
Step 2: on first time p-type epitaxial layer, growing a sacrificial oxide layer, and p type impurity of high energy ion implantation, and enter
Boiler tube carries out a high temperature and promotes, and increases p type impurity in the high concentration junction depth of p-type base area epitaxial surface, forms p-type potential barrier and stop
Layer；
Step 3: advanced furnace HCL gas purging removes surface oxide layer, carries out second of p-type outer layer growth；
Step 4: second of 104 base region surface of p-type epitaxial layer regrows a sacrificial oxide layer, and injects a big beam of high energy
The N-type impurity of stream is injected to form N+ doped layer, and high annealing simultaneously uses OED OXIDATION ENHANCED DIFFUSION simultaneously, increases surface PN junction
Junction depth, and grow certain thickness oxide layer；
Step 5: being lithographically formed deep trouth area figure, and deposit spacer medium floor and form deep trench isolation area and spacer medium floor；
Step 6: in positive photoetching and opening contact bore region is etched, deposited metal carries out photoetching, etching to front metal,
Passivation layer is deposited, photoetching simultaneously etches wire bond pad areas, i.e. front metal electrode, and Wafer Thinning completes back metal alloy, i.e.,
Back metal electrode.
3. a kind of production method of the adjustable bidirectional ESD protective device of voltage according to claim 2, it is characterised in that:
High temperature anneal temperature described in step 2 is 1000 ~ 1100 DEG C, and preferably 1050 DEG C, annealing time is 30min ~ 120min, excellent
It is selected as 60min, implanted dopant can be boron, gallium, indium, and implanted dopant is boron, 7 ° of implant angle, Implantation Energy is 600 ~
950Kev, preferably 800Kev, implantation dosage are 5e14 ~ 2e15/cm2.
4. a kind of production method of the adjustable bidirectional ESD protective device of voltage according to claim 2, it is characterised in that:
Second of p-type epitaxial layer described in step 3, doped chemical be boron, gallium, indium, preferably boron, with a thickness of 5 ~ 10um, preferably
For 8um, resistivity is 0.2 ~ 1 Ω cm, and preferably resistivity is 0.5 Ω cm.
5. a kind of production method of the adjustable bidirectional ESD protective device of voltage according to claim 2, it is characterised in that:
High temperature annealing condition in step 4 is 1050 ~ 1150 DEG C, and preferably 1100 DEG C, the time is 60min ~ 150min, preferably
90min, implanted dopant element can be phosphorus, arsenic, preferably phosphorus, and Implantation Energy is 100 ~ 200Kev, preferably 160Kev, injection
Dosage 1e15 ~ 5e15/cm2, preferably 2e15/cm2, and OXIDATION ENHANCED DIFFUSION is carried out under the conditions of 1050 DEG C of wet oxygens of combination, temperature is
1000 ~ 1100 DEG C, preferably 1050 DEG C, the oxide layer of wet oxygen growth 3000 ~ 5000, preferred thickness 4000 further increase
The silica of growth 4000 is as deep trouth exposure mask while adding N+ junction depth.
6. a kind of production method of the adjustable bidirectional ESD protective device of voltage according to claim 2, it is characterised in that:
Dry etching deep trouth is used in step 5, and grows 600 ~ 1500 silica, preferred thickness 1000, then use low pressure
Tetraethoxysilane growth technique deposits spacer medium layer, then deposits one layer of PSG spacer medium.
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| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
| CN115939132A (en) * | 2023-02-28 | 2023-04-07 | 成都吉莱芯科技有限公司 | Low-capacitance bidirectional ESD protection device and manufacturing method thereof |
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