CN210405257U - Self-locking circuit - Google Patents
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- CN210405257U CN210405257U CN201921301527.2U CN201921301527U CN210405257U CN 210405257 U CN210405257 U CN 210405257U CN 201921301527 U CN201921301527 U CN 201921301527U CN 210405257 U CN210405257 U CN 210405257U
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Abstract
A self-locking circuit is disclosed. This self-locking circuit includes: the input unit provides a first input signal and a second input signal; the feedback unit provides a first feedback signal and a second feedback signal according to the first input signal, the second output signal and the first output signal; the first trigger provides a third feedback signal and a fourth feedback signal according to the first feedback signal and the second feedback signal; the power-on unit provides a first set signal, a second set signal and a reset signal according to the second input signal, the third feedback signal, the fourth feedback signal and the initial set signal; the second flip-flop provides a second output signal and a first output signal according to the first set signal, the second set signal and the reset signal, the state of the first output signal changes when the first input signal is converted from a high level to a low level, and the state of the first output signal does not change when the first input signal is converted from the low level to the high level. The circuit realizes that a lock-free switch replaces a self-locking switch, reduces the volume and saves the cost.
Description
Technical Field
The utility model relates to an electronic circuit technical field, more specifically relates to a self-locking circuit.
Background
With the continuous maturity of electronic circuit technology, the area of circuit board is littleer and littleer, and the tool is towards the multi-functionalization, high pleasing to the eye degree, high integration, low-cost orientation development. In an electronic circuit, a switch key with a self-locking function plays a crucial role, for example, a start-up key, an HVA key, an NTSC key and other functional keys need to use the self-locking key to switch functions, while a mechanical self-locking key has the advantages of generally larger volume, small size, few types, high price, short service life and poor hand feeling, and further development of a jig is severely restricted. Therefore, there is a need for further improvement of the prior art self-locking circuit to solve the above-mentioned problems.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a self-locking circuit, wherein, the state of the first output signal of state control of the first input signal is adopted, and the adoption of the non-lock switch to replace the self-locking switch is realized, thereby reducing the product volume and saving the cost.
According to the utility model discloses an aspect provides a self-locking circuit, include: an input unit for providing a first input signal and a second input signal; a feedback unit connected to the input unit for the first input signal, the first output signal and the second output signal and providing a first feedback signal and a second feedback signal; a first flip-flop connected to the feedback unit for providing a third feedback signal and a fourth feedback signal according to the first feedback signal and the second feedback signal; a power-on unit connected to the input unit and the first flip-flop, configured to provide a first set signal, a second set signal, and a reset signal according to the second input signal, the third feedback signal, the fourth feedback signal, and an initial set signal; and a second flip-flop, connected to the power-on unit, for providing the first output signal and the second output signal according to the first set signal, the second set signal, and the reset signal, and an output end of the second flip-flop is connected to the feedback unit and provides the first output signal and the second output signal, wherein when the first input signal is converted from a high level to a low level, a state of the first output signal changes, and when the first input signal is converted from a low level to a high level, a state of the first output signal does not change.
Preferably, the input unit includes: a switch having a first terminal connected to a power supply and receiving a power supply voltage and a second terminal providing an initial signal; a first nand gate, a first input end and a second input end of which are commonly connected to the second end of the switch, for providing the first input signal according to the initial signal; and a second nand gate, a first input end and a second input end of the second nand gate being commonly connected to an output end of the first nand gate, for providing the second input signal according to the first input signal.
Preferably, the feedback unit includes: a third nand gate, a first input end of which is connected to the first output end of the second flip-flop, and a second input end of which is connected to the first output end of the input unit, for providing the first feedback signal according to the first input signal and the first output signal; and a fourth nand gate, a first input end of the fourth nand gate being connected to the second output end of the second flip-flop, a second input end of the fourth nand gate being connected to the first output end of the input unit, and configured to provide the second feedback signal according to the first input signal and the second output signal.
Preferably, the first flip-flop includes: a fifth nand gate, a first input end of which is connected to the first output end of the feedback unit, and configured to provide the fourth feedback signal according to the first feedback signal and the third feedback signal; and a sixth nand gate, a first input end of the sixth nand gate being connected to the output end of the fifth nand gate, a second input end of the sixth nand gate being connected to the second output end of the feedback unit, and configured to provide the third feedback signal according to the second feedback signal and the fourth feedback signal, wherein an output end of the sixth nand gate is connected to the second input end of the fifth nand gate and provides the third feedback signal.
Preferably, the power-on unit includes: a seventh nand gate, a first input end of which is connected to the first output end of the feedback unit, and a second input end of which is connected to the second output end of the input unit, for providing a first set signal according to the second input signal and the fourth feedback signal; the first output end and the second input end of the eighth NAND gate are connected to the initial set signal, and the output end of the eighth NAND gate is connected to the first end of the first resistor and used for providing the second set signal according to the initial set signal; and a ninth nand gate, a first input end of the ninth nand gate being connected to the second output end of the feedback unit, and a second input end of the ninth nand gate being connected to the second input end of the input unit, for providing the reset signal according to the second input signal and the third feedback signal.
Preferably, the second flip-flop includes: a tenth nand gate, a first input end of which is connected to an output end of the seventh nand gate and a second end of the first resistor, and configured to provide the second output signal according to the first set signal, the second set signal and the first output signal; and an eleventh nand gate, a first input end of which is connected to the output end of the tenth nand gate, a second input end of which is connected to the output end of the ninth nand gate, and configured to provide the first output signal according to the reset signal and the second output signal, wherein an output end of the eleventh nand gate is connected to the second input end of the tenth nand gate and provides the first output signal.
Preferably, the input unit includes: a switch having a first terminal connected to a power supply and receiving a power supply voltage and a second terminal providing an initial signal; an integration circuit connected to the second terminal of the switch for providing an integration signal in accordance with the initial signal; a first nand gate, a first input end and a second input end of which are commonly connected to an output end of the integrating circuit, for providing the first input signal according to the integrating signal; and a second nand gate, a first input end and a second input end of the second nand gate being commonly connected to an output end of the first nand gate, for providing the second input signal according to the first input signal.
Preferably, the integration circuit includes: a second resistor having a first end connected to the switch and receiving the initial signal and a second end connected to the first NAND gate and providing the integration signal; a third resistor, a first end of the third resistor being connected to a first end of the second resistor, a second end of the third resistor being connected to a reference ground; and a first end of the first capacitor is connected to the second end of the second resistor, and a second end of the first capacitor is connected to the reference ground.
Preferably, the method further comprises the following steps: and the power-on circuit is used for providing the first setting signal.
Preferably, the power-up circuit comprises: a fourth resistor, a first end of the fourth resistor being connected to a supply voltage; and a second capacitor, a first end of the second capacitor is connected to a second end of the fourth resistor and provides the initial set signal, and a second end of the second capacitor is connected to a reference ground.
The utility model provides a self-locking circuit adopts the state of the first output signal of state control of first input signal, has realized adopting the no lock switch to replace self-locking switch, has reduced the product volume and has practiced thrift the cost. Furthermore, the same gate circuit is used, so that the unification of components and parts is facilitated, the utilization rate of a gate circuit is high, and the cost is saved.
Furthermore, the lock-free switch in the existing jig is modified by the self-locking circuit, so that the lock-free key of the small-volume signed indicating lamp can be uniformly used, the product volume is more simplified, the appearance is more attractive, the circuit and the program of the jig board do not need to be modified, and the human resources are saved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a connection schematic diagram of a self-locking circuit according to an embodiment of the present invention.
Fig. 2 shows a schematic circuit diagram of a voltage stabilizing circuit according to an embodiment of the present invention.
Fig. 3 shows waveforms at node a, node B, and node C of the voltage stabilizing circuit according to an embodiment of the present invention.
Fig. 4 shows a circuit schematic of a logic circuit according to an embodiment of the invention.
Fig. 5 shows an input/output waveform diagram of the self-locking circuit according to an embodiment of the present invention.
Fig. 6 shows an input/output simulation waveform diagram of the self-locking circuit according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 1 shows a connection schematic diagram of a self-locking circuit according to an embodiment of the present invention.
As shown in fig. 1, the self-locking circuit includes an integrating circuit 110, a logic circuit 120, and a power-up circuit 130.
The integrating circuit 110 is connected to the switch KEY, and is configured to eliminate an influence of jitter of a KEY of the switch KEY on a subsequent circuit, and perform an integrating process on an input signal provided by the switch KEY.
The logic circuit 120 includes a plurality of nand gates, which are provided by a nand gate chip U1, a nand gate chip U2, and a nand gate chip U3, each of which includes three sets of nand gates, and the specific connection and operation of the plurality of nand gates are shown in fig. 4.
The connection manner of the logic circuit 120 is not limited to this, and the connection of the nand gate chips may implement the connection relationship between the nand gates as shown in fig. 4.
The power-up circuit 130 is used to provide an initial set signal set to set the logic circuit 120. The power-up circuit 130 includes, for example, a resistor R4 (a fourth resistor) and a capacitor C2 (a second capacitor), the resistor R4 is connected in series with the capacitor C2 (the second capacitor), one end of the resistor R4 is connected to the capacitor C2, the other end of the resistor R4 is connected to the power source VCC, one end of the capacitor C2, which is not connected to the resistor R4, is connected to the ground reference, and one end of the capacitor C2, which is connected to the resistor R4, provides the initial set signal set.
Fig. 2 shows a schematic circuit diagram of a voltage stabilizing circuit according to an embodiment of the present invention.
As shown in fig. 2, the voltage regulator circuit includes an integration circuit and nand gates U3-Y2 (first nand gate) in the logic circuit, the integration circuit is used to eliminate the influence of the jitter of the KEY on the subsequent circuit, and performs integration processing on the input signal provided by the KEY, that is, performs integration processing on the input signal at the node a to obtain the integrated signal at the node B. The nand gates U3-Y2 are configured to process the integrated signal at the node B after the integration process, and when the level of the integrated signal at the node B is higher than the high threshold voltage of the nand gates U3-Y2, the level of the input signal at the node C jumps, and when the level of the integrated signal at the node B is lower than the low threshold voltage of the nand gates U3-Y2, the input signal at the node C jumps, and the first input signal input1 having a standard waveform is output.
The integrating circuit comprises a resistor R2 (a second resistor), a resistor R3 (a third resistor) and a capacitor C1 (a first capacitor), one end of the resistor R2 is connected to a power supply VCC, the other end of the resistor R2 is connected to one end of a capacitor C1, one end of the capacitor C1 connected with the resistor R2 provides a node B, one end of the capacitor C1 disconnected with the resistor R2 is connected to a reference ground, a switch KEY is further connected between the resistor R2 and the power supply VCC, one end of the switch KEY connected with the resistor R2 provides a node A, the node A is further connected with a resistor R3, and the other end of the resistor R3 is connected to the reference ground.
The nand gates U3-Y2 have input a2 and input B2 commonly connected to node B, an output providing node C, and a first input signal input1 having a standard waveform.
Fig. 3 shows waveforms at node a, node B, and node C of the voltage stabilizing circuit according to an embodiment of the present invention.
As shown in fig. 3, when the switch KEY is pressed, the switch is closed, the a node provides a high level VDD, and when the switch KEY bounces, the switch is turned off, and the a node provides a low level 0V.
After the voltage at the node A is subjected to integration processing by the integrating circuit, the voltage at the node B gradually increases or decreases along with time, the lowest voltage at the node B is 0V, the highest voltage is VDD, and the highest voltage VDD is higher than the high-level threshold voltage of the NAND gates U3-Y2.
The nand gates U3-Y2 process the voltage at the node B, and when the voltage level at the node B is higher than the high threshold voltage of the nand gates U3-Y2, the voltage level at the node C jumps, and when the voltage level at the node B is lower than the low threshold voltage of the nand gates U3-Y2, the voltage level at the node C jumps, so that the first input signal input1 with a standard waveform is output.
Fig. 4 shows a circuit schematic of a logic circuit according to an embodiment of the invention.
As shown in fig. 4, the logic circuit 120 includes an input unit 121, a feedback unit 122, a first flip-flop 123, a power-on unit 124, and a second flip-flop 125.
The input unit 121 includes, for example, a switch KEY (see fig. 1) and nand gates U3-Y1 (second nand gates). One end of the switch KEY is connected to the power VCC, the other end of the switch KEY is used for providing an input signal, the input signal is stabilized by the voltage stabilizing circuit shown in fig. 2 and then outputs a first input signal input1 with a standard waveform, and the first input end and the second input end of the nand gates U3-Y1 both receive the first input signal input1 and provide a second input signal input2 of the input signal.
The feedback unit 122 comprises nand gates U1-Y1 (a third nand gate) and U1-Y2 (a fourth nand gate), second inputs of the nand gates U1-Y1 and U1-Y2 respectively receive the first input signal input1, first inputs of the nand gates U1-Y1 are connected to the first output of the second flip-flop 125 to receive the first output signal output1 of the second flip-flop 125, first inputs of the nand gates U1-Y2 are connected to the second output of the second flip-flop 125 to receive the second output signal output2 of the second flip-flop 125, outputs of the nand gates U1-Y1 (i.e. the first output of the feedback unit 122) provide the first feedback signal Y1, and outputs of the nand gates U1-Y2 (i.e. the second output of the feedback unit 122) provide the second feedback signal Y2.
The first flip-flop 123 includes NAND gates U1-Y3 (sixth NAND gate) and NAND gates U1-Y4 (fifth NAND gate). The first input terminal of the nand gates U1-Y4 is connected to the first output terminal of the feedback unit 122 and receives the first feedback signal Y1, the second input terminal thereof is connected to the output terminals of the nand gates U1-Y3 and receives the third feedback signal Y3, and the output terminals of the nand gates U1-Y4 (i.e., the first output terminal of the first flip-flop 123) provide the fourth feedback signal Y4; the first inputs of the nand gates U1-Y3 are connected to the outputs of the nand gates U1-Y4 and receive the fourth feedback signal Y4, the second inputs are connected to the second outputs of the feedback unit 122 and receive the second feedback signal Y2, and the outputs of the nand gates U1-Y3 (i.e., the first outputs of the second flip-flops 123) provide the third feedback signal Y3.
The power-up unit 124 includes NAND gates U2-Y1 (seventh NAND gate), U2-Y2 (ninth NAND gate), and U3-Y4 (eighth NAND gate). A first input end of the nand gate U2-Y1 is connected to the first output end of the first flip-flop 123 and receives the fourth feedback signal Y4, a second input end is connected to the second output end of the input unit 121 and receives the second input signal input2, and the output end generates a first set signal set 1; a first input terminal of the nand gate U2-Y2 is connected to the second output terminal of the first flip-flop 123 and receives the third feedback signal Y3, a second input terminal thereof is connected to the second output terminal of the input unit 121 and receives the second input signal input2, and an output terminal thereof generates the reset signal reset; the first input and the second input of the nand gate U3-Y4 both receive the initial set signal set, and the output is connected to a resistor R1 (a first resistor) and generates a second set signal set 2.
The second flip-flop 125 includes NAND gates U2-Y3 (eleventh NAND gate) and NAND gates U2-Y4 (tenth NAND gate). The first input terminal of the nand gates U2-Y3 is connected to the output terminals of the nand gates U2-Y4 and receives the second output signal output2, the second input terminal thereof is connected to the output terminals of the nand gates U2-Y2 and receives the reset signal reset, and the output terminals of the nand gates U2-Y3 (i.e., the first output terminal of the second flip-flop 125) generate the first output signal output 1; the first input terminals of the nand gates U2-Y4 are connected to the output terminals of the nand gates U2-Y1 and the second terminal of the resistor R1 to receive the first set signal set1 and the second set signal set2, the second input terminals are connected to the output terminals of the nand gates U2-Y3 and receive the first output signal output1, and the output terminals of the nand gates U2-Y4 (i.e., the second output terminal of the second flip-flop 125) generate the second output signal output 2.
Fig. 5 shows an input/output waveform diagram of the self-locking circuit according to an embodiment of the present invention. Fig. 6 shows an input/output simulation waveform diagram of the self-locking circuit according to an embodiment of the present invention. Table 1 shows the signal relationship of the logic circuit of the embodiment of the present invention at each stage with reference.
Table 1:
in the initial state, when the initial set signal set is 1, the first input signal input1 is also 1, and at this time, the second input signal input2 is 0, the first set signal set1 and the reset signal reset are 1, the second set signal set2 is 0, the first output signal output1 is 0, and the second output signal output2 is 1. At this time, the first feedback signal y1 is 1, the second feedback signal y2 is 0, the third feedback signal y3 is 1, and the fourth feedback signal y4 is 0.
In the first stage: when the system is powered on, the initial set signal set provided by the power-on unit is changed from 1 to 0. The second set signal set2 becomes 1, and at this time, the signals received by the first input terminal and the second input terminal of the second flip-flop are both 1, the output signal remains unchanged, except for the second set signal set2, the signal states of the rest of the circuits are the same as the initial state, and the first output signal output1 is 0.
In the second stage: when the switch is pressed, the initial set signal set is 1, the first input signal input1 is changed from 1 to 0, at this time, the second input signal input2 is 1, then the first feedback signal y1 and the second feedback signal y2 are both 1, and the signals received by the first input end and the second input end of the first flip-flop are both 1, so that the output signals remain unchanged, that is, the third feedback signal y3 is 1, the fourth feedback signal y4 is 0, the first set signal set1 is 1, the second set signal set2 is 0, the reset signal reset is 0, the first output signal output1 output by the second flip-flop is 1, and the second output signal output2 is 0.
In stage three: the switch rebounds, the initial set signal set is 1, the first input signal input1 changes from 0 to 1, at this time, the second input signal input2 is 0, the first set signal set1 and the reset signal reset are both 1, the second set signal set2 is 0, the signal received by the input end of the second flip-flop is 1, the output signal remains unchanged, the first output signal output1 is 1, and the second output signal output2 is 0.
In stage four: when the switch is pressed, the initial set signal set is 1, the input signal output1 is 1 and becomes 0, at this time, the complementary signal input1 is 1, both the first feedback signal y1 and the second feedback signal y2 are 1, both the signals received by the first input end and the second input end of the first flip-flop are 1, the output signal of the first flip-flop is unchanged, that is, the third feedback signal y3 is 1, the fourth feedback signal y4 is 0, the first set signal set1 is 0, the second set signal 35set 45 is 0, the reset signal reset is 1, the first output signal output1 output by the second flip-flop is 0, and the second output signal output2 is 1.
In stage five: the switch rebounds, the initial set signal set is 1, the first input signal input1 changes from 0 to 1, at this time, the second input signal input2 is 0, the first set signal set1 and the reset signal reset are both 1, the second set signal set2 is 0, the signal received by the input end of the second flip-flop is 1, the output signal remains unchanged, the first output signal output1 is 0, and the second output signal output2 is 1.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A self-locking circuit, comprising:
an input unit providing a first input signal and a second input signal;
a feedback unit connected to the input unit, receiving the first input signal, the first output signal and the second output signal, and providing a first feedback signal and a second feedback signal;
a first flip-flop connected to the feedback unit and providing a third feedback signal and a fourth feedback signal according to the first feedback signal and the second feedback signal;
the power-on unit is connected to the input unit and the first trigger and provides a first set signal, a second set signal and a reset signal according to the second input signal, the third feedback signal, the fourth feedback signal and an initial set signal; and
a second flip-flop connected to the power-on unit and providing the first output signal and the second output signal according to the first set signal, the second set signal, and the reset signal, an output terminal of the second flip-flop being connected to the feedback unit and providing the first output signal and the second output signal,
when the first input signal is converted from a high level to a low level, the state of the first output signal is changed, and when the first input signal is converted from a low level to a high level, the state of the first output signal is not changed.
2. The self-locking circuit of claim 1, wherein the input unit comprises:
a switch having a first terminal connected to a power supply and receiving a power supply voltage and a second terminal providing an initial signal;
a first NAND gate, a first input end and a second input end of which are commonly connected to a second end of the switch, for providing the first input signal according to the initial signal; and
and a first input end and a second input end of the second NAND gate are commonly connected to the output end of the first NAND gate, and the second input signal is provided according to the first input signal.
3. The self-locking circuit of claim 1, wherein the feedback unit comprises:
a third nand gate, a first input end of which is connected to the first output end of the second flip-flop, a second input end of which is connected to the first output end of the input unit, and which provides the first feedback signal according to the first input signal and the first output signal; and
and a first input end of the fourth nand gate is connected to the second output end of the second flip-flop, a second input end of the fourth nand gate is connected to the first output end of the input unit, and the fourth nand gate provides the second feedback signal according to the first input signal and the second output signal.
4. The self-locking circuit of claim 1, wherein the first flip-flop comprises:
a fifth nand gate, a first input end of which is connected to the first output end of the feedback unit, and which provides the fourth feedback signal according to the first feedback signal and the third feedback signal; and
a sixth NAND gate, a first input end of the sixth NAND gate being connected to the output end of the fifth NAND gate, a second input end of the sixth NAND gate being connected to the second output end of the feedback unit, the sixth NAND gate providing the third feedback signal according to the second feedback signal and the fourth feedback signal,
wherein an output of the sixth nand gate is connected to a second input of the fifth nand gate and provides the third feedback signal.
5. The self-locking circuit of claim 1, wherein the power-up unit comprises:
a seventh nand gate, a first input end of which is connected to the first output end of the feedback unit, and a second input end of which is connected to the second output end of the input unit, for providing a first set signal according to the second input signal and the fourth feedback signal;
the first output end and the second input end of the eighth NAND gate are connected to the initial set signal, and the output end of the eighth NAND gate is connected to the first end of the first resistor and used for providing the second set signal according to the initial set signal; and
and a ninth nand gate, a first input end of which is connected to the second output end of the feedback unit, and a second input end of which is connected to the second input end of the input unit, for providing the reset signal according to the second input signal and the third feedback signal.
6. The self-locking circuit of claim 5, wherein the second flip-flop comprises:
a tenth nand gate, a first input end of which is connected to an output end of the seventh nand gate and a second end of the first resistor, and configured to provide the second output signal according to the first set signal, the second set signal and the first output signal;
an eleventh NAND gate, a first input of the eleventh NAND gate being connected to the output of the tenth NAND gate, a second input of the eleventh NAND gate being connected to the output of the ninth NAND gate, for providing the first output signal according to the reset signal and the second output signal,
wherein an output of the eleventh nand gate is connected to a second input of the tenth nand gate and provides the first output signal.
7. The self-locking circuit of claim 1, wherein the input unit comprises:
a switch having a first terminal connected to a power supply and receiving a power supply voltage and a second terminal providing an initial signal;
an integration circuit connected to the second terminal of the switch for providing an integration signal in accordance with the initial signal;
a first nand gate, a first input end and a second input end of which are commonly connected to an output end of the integrating circuit, for providing the first input signal according to the integrating signal; and
and a first input end and a second input end of the second NAND gate are commonly connected to the output end of the first NAND gate and used for providing the second input signal according to the first input signal.
8. The self-locking circuit of claim 7, wherein the integration circuit comprises:
a second resistor having a first end connected to the switch and receiving the initial signal and a second end connected to the first NAND gate and providing the integration signal;
a third resistor, a first end of the third resistor being connected to a first end of the second resistor, a second end of the third resistor being connected to a reference ground; and
a first end of the first capacitor is connected to the second end of the second resistor, and a second end of the first capacitor is connected to the reference ground.
9. The self-locking circuit of claim 1, further comprising: and the power-on circuit provides the first set signal.
10. The self-locking circuit of claim 9, wherein the power-up circuit comprises:
a fourth resistor, a first end of the fourth resistor being connected to a supply voltage; and
a second capacitor, a first terminal of the second capacitor being connected to a second terminal of the fourth resistor and providing the initial set signal, a second terminal of the second capacitor being connected to a reference ground.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921301527.2U CN210405257U (en) | 2019-08-12 | 2019-08-12 | Self-locking circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921301527.2U CN210405257U (en) | 2019-08-12 | 2019-08-12 | Self-locking circuit |
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| CN210405257U true CN210405257U (en) | 2020-04-24 |
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| CN201921301527.2U Active CN210405257U (en) | 2019-08-12 | 2019-08-12 | Self-locking circuit |
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