CN220105549U - Singlechip button multiplexing circuit - Google Patents
Singlechip button multiplexing circuit Download PDFInfo
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- CN220105549U CN220105549U CN202321150840.7U CN202321150840U CN220105549U CN 220105549 U CN220105549 U CN 220105549U CN 202321150840 U CN202321150840 U CN 202321150840U CN 220105549 U CN220105549 U CN 220105549U
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The utility model provides a singlechip key multiplexing circuit which comprises a key, a starting circuit, a holding circuit and a functional circuit, wherein the starting circuit is connected with the key; in the starting-up circuit, a first end of a first electronic switch is connected to a first power end, a second end of the first electronic switch is connected to a second power end, and a third end of the first electronic switch is connected to a first end of a first capacitor; the anode of the second diode is connected to the third end of the first electronic switch, and the cathode of the second diode is connected to the first end of the second capacitor; in the holding circuit, a second end of the second electronic switch is connected to a third end of the first electronic switch, and the third end of the second electronic switch is connected to a grounding end through a second resistor; in the functional circuit, the cathode of the third diode is connected to the cathode of the second diode, and the anode of the third triode is connected to the second input/output end. The singlechip key multiplexing circuit provided by the utility model enables one key to realize a starting function and be used for other functions.
Description
Technical Field
The utility model belongs to the technical field of multiplexing circuits, and particularly relates to a single-chip microcomputer key multiplexing circuit.
Background
When designing an electronic product, a setting function needs to be realized by a key. However, due to the limitation of the design, the number of settable keys is limited, which brings great difficulty to the circuit design. It is highly desirable to design a circuit that allows multiplexing of keys.
Disclosure of Invention
Aiming at the defects, the utility model provides the singlechip key multiplexing circuit, so that one key can realize the starting function and can be used for other functions.
In order to solve the technical problems, the utility model adopts the following technical scheme:
the utility model provides a singlechip key multiplexing circuit which comprises a key, a starting circuit, a holding circuit and a functional circuit, wherein the starting circuit is connected with the key;
the starting circuit comprises a first electronic switch, a first resistor, a first capacitor, a second diode and a second capacitor, wherein a first end of the first electronic switch is connected to a first power end, a second end of the first electronic switch is connected to a second power end, a third end of the first electronic switch is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to a ground end; two ends of the first resistor are respectively connected to a first end and a third end of the first electronic switch; the anode of the second diode is connected to the third end of the first electronic switch, the cathode of the second diode is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the ground end;
the first end of the key is connected to the grounding end, and the second end of the key is connected to the cathode of the second diode;
the holding circuit comprises a second electronic switch, a first diode and a second resistor, wherein the first end of the second electronic switch is connected to the grounding end, the second end of the second electronic switch is connected to the third end of the first electronic switch, and the third end of the second electronic switch is connected to the grounding end through the second resistor; the cathode of the first diode is connected to the third end of the second electronic switch, and the anode of the first diode is connected to the first input and output end;
the functional circuit comprises a third diode, wherein the cathode of the third diode is connected to the cathode of the second diode, and the anode of the third triode is connected to the second input and output end.
As a further improvement of the utility model, the first electronic switch is a P-channel MOS tube.
As a further improvement of the utility model, the first end of the first electronic switch corresponds to the source electrode of the P-channel MOS transistor, the second end of the first electronic switch corresponds to the drain electrode of the P-channel MOS transistor, and the third end of the first electronic switch corresponds to the gate electrode of the P-channel MOS transistor.
As a further improvement of the utility model, the second electronic switch is an N-channel MOS transistor.
As a further improvement of the utility model, the first end of the second electronic switch corresponds to the source electrode of the N-channel MOS transistor, the second end of the second electronic switch corresponds to the drain electrode of the N-channel MOS transistor, and the third end of the second electronic switch corresponds to the gate electrode of the N-channel MOS transistor.
Compared with the prior art, the technical scheme of the utility model has the following beneficial effects: according to the singlechip key multiplexing circuit provided by the utility model, the first capacitor, the second diode and the second capacitor are arranged at the third end of the first electronic switch, so that the first electronic switch is controlled to be cut off before the key is closed, and the first electronic switch is controlled to be turned on after the key is closed, and the starting-up function of the singlechip is realized by the key. And the second electronic switch and the first diode are arranged at the third end of the first electronic switch, so that the first electronic switch is controlled to be turned off after the singlechip is started, and the key is closed and output to the singlechip through the third diode, so that other functions of the key are realized. The singlechip key multiplexing circuit provided by the utility model enables one key to realize a starting function and be used for other functions.
Drawings
Fig. 1 is a schematic structural diagram of a single chip microcomputer key multiplexing circuit in this embodiment.
Description of the main reference signs
First power supply terminal VCC
Second power supply terminal VCC_1
First electronic switch Q1
Second electronic switch Q2
First resistor R1
Second resistor R2
First capacitor C1
Second capacitor C2
First diode D1
Second diode D2
Third diode D3
Button S1
First input/output terminal IO_1
A second input/output terminal IO_2
Ground end GND
Detailed Description
The technical scheme of the utility model is described in detail below with reference to the accompanying drawings.
The utility model provides a singlechip key multiplexing circuit which is applied to a main board of a singlechip product to realize key multiplexing, and the keys can realize the starting-up function of the singlechip and can also be used for other functions.
As shown in fig. 1, a preferred embodiment is shown. In the single-chip microcomputer key multiplexing circuit of the embodiment, the first power end is connected with a power supply. The second power end of the power supply is connected with the singlechip to provide starting voltage for starting the singlechip. The first input and output end of the power supply is connected with a control pin of the singlechip, and the control pin is set to output high level when the singlechip is started. The second input and output end is connected with another control pin of the singlechip, and the control pin is set to be other functional signals when the input low level is input.
The singlechip key multiplexing circuit of the embodiment, as shown in fig. 1, comprises a key, a starting circuit, a holding circuit and a functional circuit.
The power-on circuit comprises a first electronic switch Q1, a first resistor R1, a first capacitor C1, a second diode D2 and a second capacitor C2, wherein a first end of the first electronic switch Q1 is connected to a first power end VCC, a second end of the first electronic switch Q1 is connected to a second power end VCC_1, a third end of the first electronic switch Q1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to a ground end GND. The two ends of the first resistor R1 are respectively connected to the first end and the third end of the first electronic switch Q1. An anode of the second diode D2 is connected to the third terminal of the first electronic switch Q1, a cathode of the second diode is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the ground GND. The first terminal of the key S1 is connected to the ground GND, and the second terminal of the key S1 is connected to the cathode of the second diode D2.
The holding circuit comprises a second electronic switch Q2, a first diode D1 and a second resistor R2, wherein a first end of the second electronic switch Q2 is connected to the grounding end GND, a second end of the second electronic switch Q2 is connected to a third end of the first electronic switch Q1, and a third end of the second electronic switch Q2 is connected to the grounding end GND through the second resistor R2. The cathode of the first diode D1 is connected to the third terminal of the second electronic switch Q1, and the anode of the first diode D1 is connected to the first input/output terminal io_1.
The functional circuit includes a third diode D3, a cathode of the third diode D3 is connected to a cathode of the second diode D2, and an anode of the third transistor D3 is connected to the second input/output terminal io_2.
The first electronic switch Q1 is a P-channel MOS transistor. The first end of the first electronic switch Q1 corresponds to the source electrode of the P-channel MOS tube, the second end of the first electronic switch Q1 corresponds to the drain electrode of the P-channel MOS tube, and the third end of the first electronic switch Q1 corresponds to the grid electrode of the P-channel MOS tube. The second electronic switch Q2 is an N-channel MOS tube. The first end of the second electronic switch Q2 corresponds to the source electrode of the N-channel MOS tube, the second end of the second electronic switch Q2 corresponds to the drain electrode of the N-channel MOS tube, and the third end of the second electronic switch Q2 corresponds to the grid electrode of the N-channel MOS tube.
The working flow of the singlechip key multiplexing circuit in this embodiment is as follows:
before the key S1 is closed, the power supply connected to the first power supply terminal VCC charges the first capacitor C1 and the second capacitor C2 through the first resistor R1, so that the gate of the first electronic switch Q1 is continuously at a high level, the first electronic switch Q1 is continuously turned off, and the second power supply terminal vcc_1 does not output, and does not supply power to the singlechip.
After the key S1 is closed, the second diode D2 is turned on, and the first capacitor C1 and the second capacitor C2 are discharged, so that the gate of the first electronic switch Q1 is at a low level, the first electronic switch Q1 is turned on, the second power supply terminal vcc_1 outputs a starting voltage, and the singlechip is started.
After the singlechip is started, a high level is output to a first input and output end IO_1, the first diode D1 is conducted, the grid electrode of the second electronic switch Q2 is high level, the second electronic switch Q2 is conducted, the grid electrode of the first electronic switch Q1 is continuously low level, the first electronic switch is continuously cut off, and the second diode is cut off.
After the key S1 is closed, the third diode D3 is conducted, the second input and output end IO_2 outputs a low level, and the singlechip senses other functional signals, so that corresponding functions are realized.
According to the singlechip key multiplexing circuit, the first capacitor, the second diode and the second capacitor are arranged at the third end of the first electronic switch, so that the first electronic switch is controlled to be cut off before the key is closed, and the first electronic switch is turned on after the key is closed, and the starting-up function of the singlechip is realized by the key. And the second electronic switch and the first diode are arranged at the third end of the first electronic switch, so that the first electronic switch is controlled to be turned off after the singlechip is started, and the key is closed and output to the singlechip through the third diode, so that other functions of the key are realized.
The foregoing has shown and described the basic principles, principal features and advantages of the utility model. It will be understood by those skilled in the art that the present utility model is not limited to the specific embodiments described above, and that the above specific embodiments and descriptions are provided for further illustration of the principles of the present utility model, and that various changes and modifications may be made therein without departing from the spirit and scope of the utility model as defined in the appended claims.
Claims (5)
1. The singlechip key multiplexing circuit is characterized by comprising a key, a starting circuit, a holding circuit and a functional circuit;
the starting circuit comprises a first electronic switch, a first resistor, a first capacitor, a second diode and a second capacitor, wherein a first end of the first electronic switch is connected to a first power end, a second end of the first electronic switch is connected to a second power end, a third end of the first electronic switch is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to a ground end; two ends of the first resistor are respectively connected to a first end and a third end of the first electronic switch; the anode of the second diode is connected to the third end of the first electronic switch, the cathode of the second diode is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the ground end;
the first end of the key is connected to the grounding end, and the second end of the key is connected to the cathode of the second diode;
the holding circuit comprises a second electronic switch, a first diode and a second resistor, wherein the first end of the second electronic switch is connected to the grounding end, the second end of the second electronic switch is connected to the third end of the first electronic switch, and the third end of the second electronic switch is connected to the grounding end through the second resistor; the cathode of the first diode is connected to the third end of the second electronic switch, and the anode of the first diode is connected to the first input and output end;
the functional circuit comprises a third diode, wherein the cathode of the third diode is connected to the cathode of the second diode, and the anode of the third triode is connected to the second input and output end.
2. The single chip microcomputer key multiplexing circuit of claim 1, wherein the first electronic switch is a P-channel MOS transistor.
3. The single-chip microcomputer key multiplexing circuit according to claim 2, wherein the first end of the first electronic switch corresponds to a source electrode of the P-channel MOS transistor, the second end of the first electronic switch corresponds to a drain electrode of the P-channel MOS transistor, and the third end of the first electronic switch corresponds to a gate electrode of the P-channel MOS transistor.
4. The single chip microcomputer key multiplexing circuit of claim 1, wherein the second electronic switch is an N-channel MOS transistor.
5. The single-chip microcomputer key multiplexing circuit according to claim 4, wherein the first end of the second electronic switch corresponds to a source electrode of the N-channel MOS transistor, the second end of the second electronic switch corresponds to a drain electrode of the N-channel MOS transistor, and the third end of the second electronic switch corresponds to a gate electrode of the N-channel MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321150840.7U CN220105549U (en) | 2023-05-15 | 2023-05-15 | Singlechip button multiplexing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321150840.7U CN220105549U (en) | 2023-05-15 | 2023-05-15 | Singlechip button multiplexing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220105549U true CN220105549U (en) | 2023-11-28 |
Family
ID=88845022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321150840.7U Active CN220105549U (en) | 2023-05-15 | 2023-05-15 | Singlechip button multiplexing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220105549U (en) |
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2023
- 2023-05-15 CN CN202321150840.7U patent/CN220105549U/en active Active
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