CN116743136A - Self-adaptive power-on delay reset circuit system - Google Patents

Abstract

The application provides a self-adaptive power-on delay reset circuit system, and relates to the technical field of electronic circuits. The self-adaptive power-on delay reset circuit system of the application relies on an input signal processing unit to primarily process an external programming control signal; the power-on delay programmable unit is used for obtaining and outputting a decoding signal by processing the external programming control signal; the power-on reset delay unit is used for obtaining the delay time corresponding to the decoding signal; the multiplexing unit is used for selecting and outputting the decoding signals corresponding to the required delay time; the power-on selection unit supports two power supplies and is compatible with two starting modes, and the power-on selection unit is used for realizing power-on delay reset through the decoding signals corresponding to the required delay time, overcomes the defects of simple circuit, easy failure and no self-adaptive characteristic of the prior art, and has the advantages of being applicable to different application environments, being selectable in power supply mode and being accurate and adjustable in power-on delay.

Description

Self-adaptive power-on delay reset circuit system

Technical Field

The application relates to the technical field of electronic circuits, in particular to a self-adaptive power-on delay reset circuit system.

Background

In a chip-level starting circuit, voltage sampling is performed during chip power-on, and when the sampled voltage exceeds a certain voltage value, the voltage is turned over, and the turned-over signal is used as a power-on reset (set) signal. The mode is characterized by simple circuit, rough structure and lower precision. The biggest disadvantage is that the circuit is easy to fail, and the circuit has poor applicability to different power supply systems.

In some complex systems, a period of time is required to wait after the power-on is completed, so that the later-stage system has enough time to stabilize the power supply voltage, and then the reset operation is performed on the later-stage system. In a chip-level starting circuit, a long-time reset (setting) function is realized by a mode of increasing a capacitor and adding a special delay circuit, and the method is single in function, has no self-adaptive characteristic and can only meet specific application requirements.

Disclosure of Invention

In order to solve the above-mentioned prior art problems, the present application provides an adaptive power-on delay reset circuit system, which includes: the power-on control device comprises an input signal processing unit, a power-on delay programmable unit, a power-on reset delay unit, a multi-path selection unit and a power-on selection unit; the input signal processing unit is used for primarily processing an external programming control signal and outputting the external programming control signal to the power-on delay programmable unit; the power-on delay programmable unit is used for obtaining and outputting a decoding signal to the power-on reset delay unit by processing the external programming control signal; the power-on reset delay unit is used for obtaining the corresponding delay time of the decoding signal; the multi-path selection unit is used for selecting and outputting the decoding signals corresponding to the required delay time to the power-on selection unit; the power-on selection unit is used for realizing power-on delay reset through the corresponding decoding signals of the required delay time. The power-on selection unit supports two power supplies and is compatible with two starting modes, the defects of simple circuit, coarse structure, low precision, easy failure and no self-adaptive characteristic in the prior art are overcome, and the power-on selection unit has the advantages of being applicable to different application environments, selectable in power supply mode and accurate and adjustable in power-on delay.

Further, the input signal processing unit is further configured to primarily process a CTRL control signal, where the CTRL control signal is used to select a desired one of the power supplies through the power-on selection unit.

Further, the input signal processing unit is further configured to primarily process a signal of the start-up mode, where the signal of the start-up mode is used to select a desired one of the start-up modes by the power-on selecting unit.

Further, the power-on delay programmable unit includes a decoding circuit for obtaining and outputting the decoding signal by processing the external programming control signal.

Further, the power-on reset delay unit comprises an oscillator and a DFF trigger, wherein the oscillator is used for outputting a clock signal; the DFF flip-flop is configured to obtain the delay time by dividing the clock signal.

Further, the DFF flip-flop continuously divides the clock signal until a desired delay time is obtained.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a self-adaptive power-on delay reset circuit system according to the present application;

FIG. 2 is a circuit diagram of an adaptive power-on delay reset circuit system provided by the application;

FIG. 3 is a schematic diagram of a decoding circuit;

FIG. 4 is a schematic diagram of a power-on reset delay circuit;

reference numerals: 1. an input signal processing unit; 2. a power-on delay programmable unit; 3. a power-on reset delay unit; 4. a multiplexing selection unit; 5. a power-on selection unit; 21. a power supply; 22. a comparator; 23. an inverter; 31. an inverter; 32. a NOT circuit; 41. an oscillator; 42. a status input signal; 43. outputting a signal; 44. a clock signal; 45. outputting an inverse of the signal; 46. DFF flip-flop.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to make the person skilled in the art better understand the solution of the present application, the technical solution of the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings.

Example 1

Referring to fig. 1, an embodiment of the present application provides an adaptive power-on delay reset circuit system, which includes: the power-on delay control circuit comprises an input signal processing unit 1, a power-on delay programmable unit 2, a power-on reset delay unit 3, a multi-path selection unit 4 and a power-on selection unit 5; the input signal processing unit 1 is configured to primarily process an external programming control signal, and output the external programming control signal to the power-on delay programmable unit 2, where the primary process is to perform filtering processing on the external programming control signal, and filter out unwanted noise; the power-on delay programmable unit 2 is configured to obtain and output a decoding signal to the power-on reset delay unit 3 by processing the external programming control signal; the power-on reset delay unit 3 is used for obtaining the corresponding delay time of the decoding signal; the multi-path selection unit 4 is configured to select and output the decoding signal corresponding to the required delay time to the power-on selection unit 5; the power-on selection unit 5 is used for realizing power-on time-delay reset through the corresponding decoding signals of the required delay time, and the power-on selection unit 5 supports two power supplies 21 and is compatible with two starting modes, so that the defects of simple circuit, rough structure, low precision, easy failure and no self-adaptive characteristic in the prior art are overcome, and the power-on time-delay reset circuit has the advantages of being applicable to different application environments, being selectable in power supply modes and being accurate and adjustable in power-on time delay.

The external programming control signals A1, A2, A3 are input to the input signal processing unit 1, the input signal processing unit 1 performs primary signal filtering processing on the external programming control signals A1, A2, A3 and inputs the primary signal filtering processing to the Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 bit decoding signals obtained through a decoding circuit of the power-on delay programmable unit 2, wherein the external programming control signals A1, A2, A3 and the Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 bit decoding signals belong to external 2bit control signals.

Referring to fig. 3, the step of processing the external programming control signal by the decoding circuit includes inputting the external programming control signal A1, A2, A3 to the decoding circuit through the inverter 31, and obtaining the decoding signal Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 by combining with the not gate circuit 32 in the decoding circuit, and the decoding circuit is only described in brief in the embodiments of the present application because the decoding circuit belongs to the prior art.

Referring to fig. 4, the power-on reset delay unit 3 receives Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 bit decoding signals, the power-on reset delay unit 3 includes an oscillator 41 and a DFF flip-flop 46, and the oscillator 41 is configured to output a clock signal 44; the DFF flip-flop 46 is 42, 43 is an output signal, 45 is an inverse signal of the output signal, the DFF flip-flop 46 is combined with and continuously divides the clock signal 44 until obtaining the required delay time, for example, CK is the clock signal 44, the function of the DFF flip-flop 46 is to divide the CK, for example, the CK signal of 1MHz becomes 500KHz after passing through the first DFF flip-flop 46, then becomes 250KHz after passing through the DFF flip-flop 46, the delay time after passing through the frequency division is T1, T2, … …, tn, so that the finally required delay time Tn is obtained by this way, the signal frequency of the clock signal 44 is converted into a period as the reference time, no reference voltage source circuit is needed, the circuit can realize no reference comparison, the structure is simple, the occupied area is small, the cost is low, and different decoding signals correspond to different delay times, wherein the different delay times are selected through programmable settings, thereby adapting to different application requirements, realizing a wider range and more accurate power-up delay time, the delay time after passing through the DFF flip-flop 46, the delay time is needed by the different decoding units are selected by the different decoding units, the required delay time is realized by the application, the method is realized by the method of selecting the required decoding unit, and the decoding unit is realized by the method.

The power-on selection unit 5 realizes 4-gear coding selection (00, 01,10, 11) through two external byte control signal bits, and respectively corresponds to 4 starting mechanisms of low-voltage power supply, high-voltage power supply, quick start and slow start to realize stable control of the multi-power supply 21 system, so that the range of the power supply 21 is widened, and the working reliability and the application flexibility of the whole system are improved. The CTRL control signal may be set to a selection bit when the low voltage power supply and the high voltage power supply are respectively powered, referring to fig. 2, R1, R2, and the lower end of C1 is grounded, VCC is the power supply 21 (may be low voltage or high voltage), if the chip is powered by the low voltage power supply, the CTRL control signal corresponds to the code (00); if the system is powered by a high voltage source, the CTRL control signal is correspondingly encoded (01), COMP is the no-reference comparator 22.

When the chip is required to be started quickly, CTRL floats and corresponds to the code (10), the pull-up resistor is pulled up to be at a high level at the moment, the switch MP0 is disconnected, and the switch MP0 is characterized in that the switch is turned on when the gate voltage is 0, and the high voltage is turned off. At this time, the resistor R2 is not connected to the circuit. After VCC is powered up, current flows through resistor R1, and simultaneously charges capacitor C1, the voltage of the upper plate of the capacitor increases gradually, and when the threshold value of comparator 22 (COMP) is reached, the voltage of OUT is inverted, which is the reset (set) primary control signal. The comparator 22 (COMP) is followed by two inverters 23 for signal shaping and enhancement.

If the chip is required to be started slowly, CTRL is connected with GND and the corresponding code (11) is low. At this time, the switch MP0 will be connected to the circuit, at this time, the resistor R1 and the resistor R2 are connected in parallel, the equivalent resistor becomes small, the flowing current becomes large, the charging current to the capacitor C1 is reduced, at this time, in a slow power-up state, the voltage rise of the upper polar plate of the capacitor C1 is slowed down, at this time, the primary control signal for resetting (setting) is turned over slowly.

By means of the quick start and the slow start, the chip reliably works in an application environment needing quick and slow power-on start, and start failure is avoided.

It should be noted that, in the embodiment of the present application, the technical content that is not specifically described in the embodiment of the present application may be implemented by using the existing related technology, which belongs to the prior art, and is not described in detail in the embodiment of the present application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof. It is apparent that the above-described embodiments are only some embodiments of the present application, but not all embodiments, and the preferred embodiments of the present application are shown in the drawings, which do not limit the scope of the patent claims. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a thorough and complete understanding of the present disclosure. Although the application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing description, or equivalents may be substituted for elements thereof. All equivalent structures made by the content of the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the scope of the application.

Claims (6)

1. An adaptive power-on delay reset circuitry comprising: the power-on control device comprises an input signal processing unit, a power-on delay programmable unit, a power-on reset delay unit, a multi-path selection unit and a power-on selection unit; the input signal processing unit is used for primarily processing an external programming control signal and outputting the external programming control signal to the power-on delay programmable unit; the power-on delay programmable unit is used for obtaining and outputting a decoding signal to the power-on reset delay unit by processing an external programming control signal; the power-on reset delay unit is used for obtaining delay time corresponding to the decoding signal; the multi-path selection unit is used for selecting and outputting the decoding signals corresponding to the required delay time to the power-on selection unit; the power-on selection unit is used for realizing power-on delay reset through the decoding signals corresponding to the required delay time, and supports two power supplies and is compatible with two starting modes.

2. An adaptive power-on-delay reset circuitry as recited in claim 1, wherein said input signal processing unit is further configured to primarily process a CTRL control signal for selecting a desired one of said power supplies by said power-on selection unit.

3. An adaptive power-on delay reset circuitry as recited in claim 1, wherein said input signal processing unit is further configured to primarily process signals of said start-up mode for selecting a desired one of said start-up modes by said power-on selection unit.

4. An adaptive power-up delay reset circuitry as recited in claim 1, wherein said power-up delay programmable unit comprises a decoding circuit for deriving and outputting said decoded signal by processing said external programming control signal.

5. An adaptive power-on delay reset circuitry as recited in claim 1, wherein said power-on reset delay unit comprises an oscillator and a DFF flip-flop, said oscillator configured to output a clock signal; the DFF flip-flop is configured to obtain the delay time by dividing the clock signal.

6. An adaptive power-on delay reset circuitry as recited in claim 5, wherein said DFF flip-flop continuously divides said clock signal until a desired delay time is obtained.