CN210297544U - Multi-energy fusion booster circuit applied to energy collection system - Google Patents
Multi-energy fusion booster circuit applied to energy collection system Download PDFInfo
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- CN210297544U CN210297544U CN201920282203.2U CN201920282203U CN210297544U CN 210297544 U CN210297544 U CN 210297544U CN 201920282203 U CN201920282203 U CN 201920282203U CN 210297544 U CN210297544 U CN 210297544U
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Abstract
The utility model discloses a multi-energy fusion booster circuit applied to an energy collection system, which comprises 2 multi-energy booster units; each multi-energy boosting unit is composed of 1 high-voltage clamping circuit, 1 low-voltage clamping branch circuit and 1 output circuit. Each of the 2 high voltage clamp circuits includes 1 capacitor and 1 NMOS transistor. Each of the 2 low voltage clamp circuits includes 1 capacitor and 1 NMOS transistor. The 2 output circuits respectively comprise 1 PMOS tube and 1 NMOS tube. The utility model discloses an energy to two kinds of forms is integrated, solves prior art and requires the problem strictly to single energy, reduces minimum starting voltage. The utility model discloses application range is wide, but the wide application reduces the required magnitude of voltage of self-starting in energy collecting system.
Description
Technical Field
The utility model relates to an integrated circuit technical field, concretely relates to be applied to energy collecting system's multi-energy fusion boost circuit.
Background
With the rapid development of wireless charging technology, people require equipment to have a lower starting voltage during operation. One of the core technologies of the energy collection system is a low-voltage self-starting circuit design. And the system control circuit is enabled to work through the low-voltage self-starting circuit under the condition of low input, so that the work of the whole energy collection system is started. The low voltage self-starting technique determines the minimum value of the system starting work, and because the micro-energy for supplying energy to the energy collecting system is low, the aim of further reducing the minimum starting voltage is difficult. At present, in the prior art, a self-starting mode is generally realized by using single energy, for example, a self-starting mode of a system is realized by using radio frequency energy, or boosting is performed by using temperature difference energy and the like. If the two kinds of energy are combined to supply energy to the self-starting circuit together, a complementary effect is achieved, the boosting effect is improved, and the voltage value of the lowest starting voltage is reduced.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve is the higher problem of low voltage self-starting circuit's minimum starting voltage value among the current energy collecting system, provides a be applied to energy collecting system's multi-energy fusion boost circuit.
In order to solve the above problems, the utility model discloses a realize through following technical scheme:
a multi-energy fusion booster circuit applied to an energy collection system comprises 2 multi-energy booster units; each multi-energy boosting unit is composed of 1 high-voltage clamping circuit, 1 low-voltage clamping branch and 1 output circuit;
the first high voltage clamp circuit includes a capacitor C1And NMOS transistor CMN1(ii) a NMOS tube CMN1The substrate is connected with the drain electrode; differential radio frequency input signal RF-linkA capacitor C1The upper panel of (1); capacitor C1Lower level board of (3) is connected with NMOS tube CMN1And forming an output of the first high voltage clamp; NMOS tube CMN1The drain electrode and the grid electrode of the grid electrode are simultaneously connected with a direct current signal DC +;
the first low voltage clamp circuit includes a capacitor C2And NMOS transistor CMN2(ii) a NMOS tube CMN2The substrate is connected with the drain electrode; differential radio frequency input signal RF-connection capacitor C2The upper panel of (1); capacitor C2Lower level board of (3) is connected with NMOS tube CMN2A drain and a gate forming an output of the first low voltage clamp; NMOS tube CMN2The source electrode is connected with a direct current signal DC-;
the first output circuit comprises an NMOS transistor MN1And PMOS transistor MP1(ii) a NMOS tube MN1The substrate is connected with the source electrode; PMOS pipe MP1The substrate is connected with the source electrode; PMOS pipe MP1The source of the first high-voltage clamping circuit is connected with the output end of the first high-voltage clamping circuit; NMOS tube MN1The source of the first low-voltage clamping circuit is connected with the output end of the first low-voltage clamping circuit; differential radio frequency input signal RF + is simultaneously connected with NMOS (N-channel metal oxide semiconductor) transistor MN1And PMOS transistor MP1A gate electrode of (1); NMOS tube MN1And PMOS transistor MP1Is connected and outputs a differential output signal Out-;
the second high voltage clamp circuit comprises a capacitor C3And NMOS transistor CMN3(ii) a NMOS tube CMN3The substrate is connected with the drain electrode; differential radio frequency input signal RF + connecting capacitor C3The upper panel of (1); capacitor C3Lower level board of (3) is connected with NMOS tube CMN3And forming an output terminal of the second high voltage clamp circuit; NMOS tube CMN3The drain electrode and the grid electrode of the grid electrode are simultaneously connected with a direct current signal DC +;
the second low voltage clamp circuit includes a capacitor C4And NMOS transistor CMN4(ii) a NMOS tube CMN4The substrate is connected with the drain electrode; differential radio frequency input signal RF + connecting capacitor C4The upper panel of (1); capacitor C4Lower level board of (3) is connected with NMOS tube CMN4A drain and a gate and forming an output of the second low voltage clamp; NMOS tube CMN4The source electrode is connected with a direct current signal DC-;
the second output circuit comprises an NMOS transistor MN2And PMOS transistor MP2(ii) a NMOS tube MN2The substrate is connected with the source electrode; PMOS pipe MP2The substrate is connected with the source electrode; PMOS pipe MP2The source of the first high-voltage clamping circuit is connected with the output end of the second high-voltage clamping circuit; NMOS tube MN2The source of the first low-voltage clamping circuit is connected with the output end of the first low-voltage clamping circuit; differential radio frequency input signal RF + is simultaneously connected with NMOS (N-channel metal oxide semiconductor) transistor MN2And PMOS transistor MP2A gate electrode of (1); NMOS tube MN2And PMOS transistor MP2Is connected to output a differential output signal Out +.
In the above scheme, the capacitor C1～C4The parameters of (3) are the same.
In the above scheme, the NMOS transistor CMN1～CMN4The parameters of (3) are the same.
In the above scheme, PMOS tube MP1Width to length ratio of NMOS transistor MN1The width to length ratio is 3 times.
In the above scheme, PMOS tube MP2Width to length ratio of NMOS transistor MN2The width to length ratio is 3 times.
Compared with the prior art, the utility model has the characteristics of as follows:
1. alternating current energy (radio frequency energy) and direct current energy (temperature difference energy and the like) are combined and work cooperatively, so that the requirement on the lowest starting voltage can be reduced.
2. Alternating current energy and direct current energy are coordinated, and the high requirement of single energy when the single energy is collected in the prior art is reduced. The radio frequency energy requirement is low when the direct current energy is high; when the rf energy is high enough, the dc energy can be as low as 0.
3. The method has strong practicability and can be widely applied to energy collection systems. At VDC100mV, with an RF power of-11 dBm, the output peak is about 30% higher than the input amplitude; at an RF power of-9.5 dBm, VDCThe demand may be as low as 0V, so that the output range exceeds the input amplitude by about 15%.
4. The output range of the circuit is adjustable, and the output end of the circuit is connected with a corresponding rectifying and voltage stabilizing circuit to obtain a required direct current voltage value.
Drawings
Fig. 1 is a circuit diagram of a multi-energy fusion booster circuit applied to an energy collection system.
Fig. 2 is an input differential waveform C: (V)RF+And VRF-) And output differential wave B: (Out + and Out-) form a comparison graph.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, a multi-energy fusion boost circuit applied to an energy collection system utilizes 2 multi-energy boost units to form a differential input and differential output structure, so as to implement a multi-energy boost function. The first multi-energy boosting unit is connected with a differential radio frequency input signal RF-serving as an alternating current energy source, is connected with direct current signals DC + and DC-serving as direct current energy sources, and is connected with a differential radio frequency input signal RF + serving as a control signal. The second multi-energy boosting unit is connected with a differential radio frequency input signal RF + as an alternating current energy source, is connected with direct current signals DC + and DC-as direct current energy sources, and is connected with a differential radio frequency input signal RF-as a control signal.
The first multi-energy boosting unit and the second multi-energy boosting unit are respectively composed of 1 high-voltage clamping circuit, 1 low-voltage clamping circuit and 1 output circuit.
Each of the 2 high voltage clamp circuits includes 1 capacitor and 1 NMOS transistor. The NMOS transistor is used as a switch controlled by an input signal to increase the potential of the lower electrode plate of the capacitor, so that a high potential output is obtained.
The first high voltage clamp circuit includes a capacitor C1And NMOS transistor CMN1Wherein the capacitance C1Capacity value of 5p, CMN1The size is 55u/0.18 um. NMOS tube CMN1The substrate of which is connected to the drain. Differential radio frequency input signal RF-connection capacitor C1The upper plate of (1). Capacitor C1Lower level board of (3) is connected with NMOS tube CMN1And forming an output of the first high voltage clamp circuit. NMOS tube CMN1The drain and the gate of the transistor are connected to a direct current signal DC +.
In the first placeIn the high voltage clamp circuit, when the RF-is low, the capacitor C1Upper plate is low, capacitance C1Lower plate is also low, CMN1The gate voltage is higher than CMN1Source voltage of (CMN)1On, DC + charge flows to the capacitor C1So that C is1Lower plate voltage of VDCAt this time C1The voltage difference between the two ends is VDC+VRFThe potential at point A is VDC. When RF-is high, the capacitance C1Upper plate of high capacitance C1Lower plate is also high, CMN1Gate voltage lower than CMN1Source voltage, CMN1Cut-off, capacitance C1The voltage difference over is kept constant, C1The lower plate has a voltage of VDC+2VRFAt this time, the potential at the point A is VDC+2VRFThus, by input control of the differential radio frequency input signal RF-, the A-point potential range (V) is obtainedDC，VDC+2VRF)。
The second high voltage clamp circuit comprises a capacitor C3And NMOS transistor CMN3Wherein the capacitance C3Capacity value of 5p, CMN3The size is 55um/0.18 um. NMOS tube CMN3The substrate of which is connected to the drain. Differential radio frequency input signal RF + connecting capacitor C3The upper plate of (1). Capacitor C3Lower level board of (3) is connected with NMOS tube CMN3And forming an output of the second high voltage clamp circuit. NMOS tube CMN3The drain and the gate of the transistor are connected to a direct current signal DC +.
In the second high voltage clamp, when RF + is low, the capacitor C3Upper plate is low, capacitance C3Lower plate is also low, CMN3The gate voltage is higher than CMN3Source voltage of (CMN)3On, DC + charge flows to the capacitor C3So that C is3Lower plate voltage of VDCAt this time C3The voltage difference between the two ends is VDC+VRFPotential at point C is VDC. When RF + is high, the capacitance C3Upper plate of high capacitance C3Lower plate is also high, CMN3Gate voltage lower than CMN3Source voltage, CMN3Cut-off, capacitance C3Voltage ofThe difference remains the same, C3The lower plate has a voltage of VDC+2VRFAt this time, the potential at the point C is VDC+2VRFTherefore, the potential range (V) of the point C is obtained through the input control of the differential radio frequency input signal RF +DC，VDC+2VRF)。
Each of the 2 low voltage clamp circuits includes 1 capacitor and 1 NMOS transistor. The NMOS tube is used as a switch controlled by an input signal to reduce the potential of the lower electrode plate of the capacitor, so that a low potential output is obtained.
The first low voltage clamp circuit includes a capacitor C2And NMOS transistor CMN2Wherein the capacitance C2Capacity value of 5p, CMN2The size is 55u/0.18 um. NMOS tube CMN2The substrate of which is connected to the drain. Differential radio frequency input signal RF-connection capacitor C2The upper plate of (1). Capacitor C2Lower level board of (3) is connected with NMOS tube CMN2A drain and a gate and forming an output of the first low voltage clamp. NMOS tube CMN2The source is connected with a direct current signal DC-.
In the first low voltage clamp, when RF-is low, the capacitor C2Upper plate is low, capacitance C2Lower plate is also low, CMN2Gate voltage lower than CMN2Source voltage, CMN2Cut-off, capacitance C2The voltage difference above is kept constant, and the following analysis shows that C2Voltage difference of VDC+VRFTherefore, the potential of B is — (V) at this timeDC+2VRF). When RF-is high, the capacitance C2Upper pole plate is high, lower pole plate is also high, CMN2The gate voltage is higher than CMN2Source voltage, CMN2On, the capacitance C2Upper charge flows to DC-, so that C2The lower plate voltage of the lower plate is gradually reduced and is equal to-VDCAt this time C2The voltage difference between the two ends is VDC+VRFAt this time C2The lower polar plate has a potential of-VDCI.e. the potential at point B is-VDC. Therefore, the potential range (-V) of the point BDC，-(VDC+2VRF))。
The second low voltage clamp circuit includes a capacitor C4And NMOS tube CMN4Wherein the capacitance C4Capacity value of 5p, CMN4The size is 55u/0.18 um. Differential radio frequency input signal RF + connecting capacitor C4The upper plate of (1). Capacitor C4Lower level board of (3) is connected with NMOS tube CMN4A drain and a gate and forming an output of the second low voltage clamp. NMOS tube CMN4The source is connected with a direct current signal DC-.
In the second low voltage clamp, when RF + is low, the capacitor C4Upper plate is low, capacitance C4Lower plate is also low, CMN4Gate voltage lower than CMN4Source voltage, CMN4Cut-off, capacitance C4The voltage difference above is kept constant, and the following analysis shows that C4Voltage difference of VDC+VRFTherefore, the D potential is — (V) at this timeDC+2VRF). When RF + is high, the capacitance C4Upper pole plate is high, lower pole plate is also high, CMN4The gate voltage is higher than CMN4Source voltage, CMN4On, the capacitance C4Upper charge flows to DC-, so that C4The lower plate voltage of the lower plate is gradually reduced and is equal to-VDCAt this time C4The voltage difference between the two ends is VDC+VRFAt this time C4The lower polar plate has a potential of-VDCI.e. the potential at point D is-VDC. Therefore, the potential range (-V) of the point DDC，-(VDC+2VRF))。
The 2 output circuits respectively comprise 1 PMOS tube and 1 NMOS tube. The 2 MOS tubes are used for selecting high potential and low potential in the four voltage clamping circuits to output through the control of input signals, and differential output signals Out-and Out + with larger output ranges are obtained.
The first output circuit comprises an NMOS transistor MN1And PMOS transistor MP1Wherein MN1MP with the size of 3um/0.18um1The size is 9um/0.18 um. NMOS tube MN1The substrate of which is connected to the source. PMOS pipe MP1The substrate of which is connected to the source. PMOS pipe MP1The source of which is connected to the output of the first high voltage clamp. NMOS tube MN1The source of which is connected to the output of the first low voltage clamp. Differential radio frequency input signal RF + homodyneTime-connected NMOS (N-channel Metal oxide semiconductor) transistor MN1And PMOS transistor MP1A gate electrode of (1). NMOS tube MN1And PMOS transistor MP1Is connected and outputs a differential output signal Out-.
In the first output circuit, MN is controlled when the differential radio frequency input signal RF + is controlled to be high1Conducting, MP1Cut-off, output voltage VOut-Equal to the voltage at point B, i.e. VOut-＝-(VDC+2VRF). Controlling differential RF input signal RF + low, MN1Cutoff, MP1On, output voltage VOut-Equal to the voltage at point A, i.e. VOut-＝VDC+2VRF. I.e. an output range of (- (V)DC+2VRF)，VDC+2VRF)。
The second output circuit comprises an NMOS transistor MN2And PMOS transistor MP2Wherein MN2MP with the size of 3um/0.18um2The size is 9um/0.18 um. NMOS tube MN2The substrate of which is connected to the source. PMOS pipe MP2The substrate of which is connected to the source. PMOS pipe MP2The source of which is connected to the output of the second high voltage clamp. NMOS tube MN2The source of which is connected to the output of the second low voltage clamp. Differential radio frequency input signal RF + is simultaneously connected with NMOS (N-channel metal oxide semiconductor) transistor MN2And PMOS transistor MP2A gate electrode of (1). NMOS tube MN2And PMOS transistor MP2Is connected to output a differential output signal Out +.
In the second output circuit, MN is controlled when the differential radio frequency input signal RF-is high2Conducting, MP2Cut-off, output voltage VOut+Equal to the voltage at point D, i.e. VOut+＝-(VDC+2VRF). Controlling differential RF input signal RF-to be low, MN2Cutoff, MP2On, output voltage VOut+Equal to the voltage at point C, i.e. VOut+＝VDC+2VRF. I.e. an output range of (- (V)DC+2VRF)，VDC+2VRF)。
Fig. 2 is an input differential waveform C: (V)RF+And VRF-) And output differential wave B: (Out + and Out-) form a comparison graph. Differential RF transmission according to different inputsPotential information of A, B, C and D point obtained by incoming signal RF +, RF-and output signal VOut-、VOut+The potential relationship is shown in table 1:
TABLE 1
| RF+ | RF- | A | B | C | D | Out- | Out+ | Out+-Out- |
| L | H | VDC+2VRF | -VDC | VDC | -VDC-2VRF | VDC+2VRF | -VDC-2VRF | -2VDC-4VRF |
| H | L | VDC | -VDC-2VRF | VDC+2VRF | -VDC | -VDC-2VRF | VDC+2VRF | 2VDC+4VRF |
In the table: h denotes a control voltage high level; l represents a control signal low level. If the third row of column A indicates that the potential at point A is V when RF + is H and RF-is LDCAnd so on; the voltage relation obtained according to the actual situation is VRF>VDC>0>-VDC>-VRF。
The utility model discloses an energy to two kinds of forms is integrated, solves prior art and requires the problem strictly to single energy, reduces minimum starting voltage. The utility model discloses application range is wide, but the wide application reduces the required magnitude of voltage of self-starting in energy collecting system.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and therefore, the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from the principles thereof.
Claims (5)
1. A multi-energy fusion booster circuit applied to an energy collection system is characterized by comprising 2 multi-energy booster units; each multi-energy boosting unit is composed of 1 high-voltage clamping circuit, 1 low-voltage clamping branch and 1 output circuit;
the first high voltage clamp circuit includes a capacitor C1And NMOS transistor CMN1(ii) a NMOS tube CMN1The substrate is connected with the drain electrode; differential radio frequency input signal RF-connection capacitor C1The upper panel of (1); capacitor C1Lower level board of (3) is connected with NMOS tube CMN1And forming an output of the first high voltage clamp; NMOS tube CMN1The drain electrode and the grid electrode of the grid electrode are simultaneously connected with a direct current signal DC +;
the first low voltage clamp circuit includes a capacitor C2And NMOS transistor CMN2(ii) a NMOS tube CMN2The substrate is connected with the drain electrode; differential radio frequency input signal RF-connection capacitor C2The upper panel of (1); capacitor C2Lower level board of (3) is connected with NMOS tube CMN2A drain and a gate forming an output of the first low voltage clamp; NMOS tube CMN2The source electrode is connected with a direct current signal DC-;
the first output circuit comprises an NMOS transistor MN1And PMOS transistor MP1(ii) a NMOS tube MN1The substrate is connected with the source electrode; PMOS pipe MP1The substrate is connected with the source electrode; PMOS pipe MP1The source of the first high-voltage clamping circuit is connected with the output end of the first high-voltage clamping circuit; NMOS tube MN1The source of the first low-voltage clamping circuit is connected with the output end of the first low-voltage clamping circuit; differential radio frequency input signal RF + is simultaneously connected with NMOS (N-channel metal oxide semiconductor) transistor MN1And PMOS transistor MP1A gate electrode of (1); NMOS tube MN1And PMOS transistor MP1Is connected and outputs a differential output signal Out-;
the second high voltage clamp circuit comprises a capacitor C3And NMOS transistor CMN3(ii) a NMOS tube CMN3The substrate is connected with the drain electrode; differential radio frequency input signal RF + connecting capacitor C3The upper panel of (1); capacitor C3Lower level board of (3) is connected with NMOS tube CMN3And forming an output terminal of the second high voltage clamp circuit; NMOS tube CMN3The drain electrode and the grid electrode of the grid electrode are simultaneously connected with a direct current signal DC +;
the second low voltage clamp circuit includes a capacitor C4And NMOS transistor CMN4(ii) a NMOS tube CMN4The substrate is connected with the drain electrode; differential radio frequency input signal RF + connecting capacitor C4The upper panel of (1); electric powerContainer C4Lower level board of (3) is connected with NMOS tube CMN4A drain and a gate and forming an output of the second low voltage clamp; NMOS tube CMN4The source electrode is connected with a direct current signal DC-;
the second output circuit comprises an NMOS transistor MN2And PMOS transistor MP2(ii) a NMOS tube MN2The substrate is connected with the source electrode; PMOS pipe MP2The substrate is connected with the source electrode; PMOS pipe MP2The source of the first high-voltage clamping circuit is connected with the output end of the second high-voltage clamping circuit; NMOS tube MN2The source of the first low-voltage clamping circuit is connected with the output end of the first low-voltage clamping circuit; differential radio frequency input signal RF + is simultaneously connected with NMOS (N-channel metal oxide semiconductor) transistor MN2And PMOS transistor MP2A gate electrode of (1); NMOS tube MN2And PMOS transistor MP2Is connected to output a differential output signal Out +.
2. The multi-energy fusion voltage boosting circuit applied to the energy collection system as claimed in claim 1, wherein the capacitor C is1～C4The parameters of (3) are the same.
3. The multi-energy fusion voltage boosting circuit applied to the energy collection system as claimed in claim 1, wherein the NMOS transistor CMN is1～CMN4The parameters of (3) are the same.
4. The multi-energy fusion voltage boosting circuit applied to the energy collection system as claimed in claim 1, wherein the PMOS transistor MP1Width to length ratio of NMOS transistor MN1The width to length ratio is 3 times.
5. The multi-energy fusion voltage boosting circuit applied to the energy collection system as claimed in claim 1, wherein the PMOS transistor MP2Width to length ratio of NMOS transistor MN2The width to length ratio is 3 times.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842284A (en) * | 2019-03-06 | 2019-06-04 | 桂林电子科技大学 | A kind of multipotency amount fusion booster circuit applied to energy collecting system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842284A (en) * | 2019-03-06 | 2019-06-04 | 桂林电子科技大学 | A kind of multipotency amount fusion booster circuit applied to energy collecting system |
| CN109842284B (en) * | 2019-03-06 | 2023-11-10 | 桂林电子科技大学 | Multi-energy fusion boost circuit applied to energy collection system |
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Assignee: Nanning Taisu Semiconductor Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2022450000523 Denomination of utility model: A Multi energy Fusion Booster Circuit Applied to Energy Collection System Granted publication date: 20200410 License type: Common License Record date: 20221229 |
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