CN210129335U

CN210129335U - Sequential logic circuit experimental device for teaching

Info

Publication number: CN210129335U
Application number: CN201921058144.7U
Authority: CN
Inventors: 郭立强; 曹翔; 刘恋
Original assignee: Huaiyin Normal University
Current assignee: Huaiyin Normal University
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-03-06
Anticipated expiration: 2029-06-28

Abstract

The utility model discloses a time sequence logic circuit experimental device for teaching, which comprises a base, a panel, a chip pin identification plate and a banana head connecting wire; the panel integrates a light emitting diode unit, a nixie tube unit, a clock signal unit, a chip testing unit, a logic level unit and a UPS unit; the chip pin identification board comprises a CD4027 chip pin identification board, a CD4510 chip pin identification board and a 74LS194 chip pin identification board. The experimental device is flexible to use and easy to realize, and a user can connect all the functional units into a sequential logic chip test circuit through the banana head connecting wire and verify and demonstrate the functions of the sequential logic chip by combining the chip pin identification board; unique jumbo size design makes the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, be convenient for use widely in colleges and universities classroom, have wide application prospect.

Description

Sequential logic circuit experimental device for teaching

Technical Field

The utility model relates to the field of electronic technology, concretely relates to sequential logic circuit experimental apparatus is used in teaching.

Background

The course is a necessary course for the electronic specialties such as electronic science and technology, electronic information engineering, communication engineering and the like in colleges and universities, and the professional basis of non-electronic specialties such as computer science and technology, Internet of things engineering, physics and the like, plays an important role in the whole talent training system, and lays a good foundation for the study of courses such as subsequent digital system design, singlechip, computer composition principle, integrated circuit design and the like. The sequential logic circuit is one of the core contents of the course of digital electronic technology foundation, and some sequential logic chips are explained mainly: CD4027, CD4510 and 74LS194, and the like. Whether the knowledge of the time sequence logic circuit is firmly mastered or not directly influences the learning effect of the course.

At present, the experiment conditions of the electrical major of all colleges and universities are better, and the electrical major laboratories are equipped with digital circuits. However, in the existing course system of colleges and universities, the teaching mode of "theoretical course + experimental course" is adopted in the course, i.e. theoretical teaching is firstly performed in a multimedia classroom, and then experimental teaching is performed in a professional laboratory. The digital electronic technology foundation is a highly practical course, and if knowledge is infused in theoretical teaching, the learning effect of students is poor. If experimental demonstration is alternated in the teaching process, a plurality of problems exist. For example, the laboratory equipment in a professional laboratory is either a large laboratory platform with a large floor space or a relatively heavy laboratory box. The large experiment platform can not be moved to a common multimedia classroom for class demonstration. For the experimental box, because the volume is small, the functional units are many, which results in high element density, and the LED, the nixie tube, the switch and the like all use small-sized elements. During experiment demonstration, only the front two rows of students can clearly see the experiment, and the later students can hardly see the experiment process and results clearly. Meanwhile, the experiment box adopts 220V alternating current for power supply, and the mobility is poor. In addition, if the experiment box is to face the student to perform classroom demonstration, the flip cover on the experiment box can block the sight of the student, and the demonstration is very inconvenient.

For non-electronic specialties such as computer science and technology, Internet of things engineering and physics, the situation is also not optimistic. For colleges and universities with poor experimental conditions, because non-electric professionals do not have specialized laboratories, the experiments of the class usually adopt EDA simulation based on a computer to complete relevant experimental teaching. This is most common for computer-like specialties. Finally, the learning experience of students is poor, the teachers lack intuition in the explanation of knowledge points, and the teaching atmosphere is quite tedious.

According to questionnaires for college student course study by authorities such as Max, students often are most interested in lesson modes with strong interactivity and courses of experimental demonstration, and are most concentrated in energy when attending lessons. But often cannot raise the spirit of PPT infusion type teaching. According to the problem that meets in this kind of course of the digital electronics technology basis gives lessons in-process, can't use hardware equipment conveniently to carry out sequential logic circuit function demonstration on theoretical class promptly, the utility model provides a sequential logic circuit experimental apparatus convenient to classroom teaching demonstration for carry out functional test to sequential logic chip. The device is a teaching instrument for time sequence logic circuit experimental demonstration, is also a good carrier for teacher-student interaction, plays a positive exemplary role in classroom teaching, can improve classroom attention and learning initiative of students, and has good popularization and use prospects.

Disclosure of Invention

To the problem that exists among the prior art, improve the quality of giving lessons in class, the utility model provides a chronogenesis logic circuit experimental apparatus is used in teaching, the utility model discloses the technical scheme who takes as follows:

a sequential logic circuit experimental device for teaching comprises a base, a panel, a chip pin identification plate and a banana head connecting wire; the panel integrates a light emitting diode unit, a nixie tube unit, a clock signal unit, a chip testing unit, a logic level unit and a UPS unit;

the light-emitting diode unit consists of a light-emitting diode, a resistor and a banana head socket, the cathode of the light-emitting diode is connected with the ground port of the UPS unit through the resistor, and the anode of the light-emitting diode is connected with the banana head socket;

the nixie tube unit consists of a nixie tube driving circuit board and a banana head socket; the nixie tube driving circuit board consists of a driving circuit board, a nixie tube and a display decoding chip, wherein the nixie tube and the display decoding chip are welded on the driving circuit board;

the clock signal unit consists of a clock signal circuit board and a banana head socket, wherein the clock signal circuit board is provided with 3 pads, the pads marked as Vcc and GND are respectively welded to a power supply port and a grounding port of the UPS unit through flying wires, and the other pad CP is connected with the banana head socket CP1 and CP2 through flying wires;

the chip testing unit consists of a locking seat and a banana head socket, and a pin of the locking seat is connected with the banana head socket;

the logic level unit is composed of a single-pole double-throw switch, a banana head socket and a resistor divider, wherein the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit, the input end of the other side of the single-pole double-throw switch is connected with the power output port of the UPS unit through the resistor divider, and the middle output end of the single-pole double-throw switch is connected with the banana head socket;

the UPS unit is by 5V supply socket, UPS power module, the lithium cell, switch and banana head socket constitute, 5V supply socket's the positive pole and the negative pole link to each other with UPS power module's power input port, the positive pole and the negative pole of lithium cell link to each other with UPS power module's battery port, UPS power module's the positive output of passing through switch links to each other with banana head socket, for whole experimental apparatus power supply, UPS power module's the output negative pole links to each other with banana head socket, as whole experimental apparatus's earthing terminal.

Preferably, the base is a cuboid structure formed by single-layer acrylic plates, and the panel is a single-layer acrylic plate and is fixed on the base through long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

Preferably, the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

Preferably, the nixie tube is a red 2.3-inch one-bit common-cathode nixie tube, wherein 4 LEDs are arranged in each segment, and the nixie tube is connected in a two-string or two-parallel mode; the model of the display decoding chip is 74LS 48.

Preferably, the output frequency of the clock signal is 0.5 Hz-20 Hz, and the output frequency is continuously adjustable through a potentiometer.

Preferably, when the chip testing unit performs chip testing, the pin identification board of the corresponding chip needs to be used, and the chip pin identification board includes a CD4027 chip pin identification board, a CD4510 chip pin identification board, and a 74LS194 chip pin identification board.

Preferably, the lithium battery is a 14500 lithium battery.

Preferably, each there is a plug at banana head connecting wire both ends, the plug comprises plastics handle and metal lotus flower head, the diameter of metal lotus flower head with the hole diameter of banana head socket is 2 millimeters, the top of plastics handle has the jack that the internal diameter is 2 millimeters.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the utility model discloses in to the test of different model chronogenesis logic chips use the chip pin sign board cooperation of chip test unit and corresponding model, chip pin sign board can clearly show chip pin function, one set of device alright realize the test of different model chips, the commonality is strong.

2. The utility model discloses a functional unit is abundant, easily realizes that user's accessible banana head connecting wire accomplishes the test of the chronogenesis logic chip of different models with each functional unit connection, uses in a flexible way.

3. The utility model discloses a base, panel and chip pin sign board all adopt the preparation of ya keli board, have weatherability and acid and alkali resistance good, advantages such as the impact resistance is strong, easy cleanness and insulating nature are good to the cost is low, the sexual valence relative altitude.

4. The utility model discloses the middle base is 60 centimetres with the panel length, and the width is 45 centimetres, and each unit all prints the jumbo size identification chart that has corresponding chip or component on the panel, and the charactron on the panel adopts 2.3 inches's jumbo size charactron, and emitting diode's diameter is 1 centimetre, and this kind of unique jumbo size design makes the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, the convenience is used widely in colleges and universities classroom, has wide use value and application prospect.

Drawings

Fig. 1 is a schematic view of a base of the present invention;

FIG. 2 is a structural diagram of the middle panel of the present invention;

FIG. 3 is a circuit diagram of each unit on the middle panel of the present invention;

fig. 4 is a schematic view of the driving circuit board of the present invention;

FIG. 5 is a schematic diagram of the clock signal circuit board of the present invention;

fig. 6 is a pin identification plate of the CD4027 chip of the present invention;

FIG. 7 is a pin identification plate of the CD4510 chip of the present invention;

fig. 8 is a pin identification plate of a 74LS194 chip of the present invention;

fig. 9 is a circuit diagram of the CD4027 chip under test according to the present invention;

FIG. 10 is a circuit diagram of a CD4510 chip under test according to the present invention;

fig. 11 is a circuit diagram of a 74LS194 chip under test in accordance with the present invention;

reference numerals: 101-light emitting diode unit, 102-nixie tube unit, 103-clock signal unit, 104-chip test unit, 105-logic level unit, 106-UPS unit, 201-driving circuit board, 202-screw hole position, 203-nixie tube welding area, 204-display decoding chip welding area, 205-bonding pad, 301-clock signal circuit board, 302-component welding area and 303-printed wire.

Detailed Description

In order to facilitate the technical solution of the present invention to be understood by the skilled person, the technical solution of the present invention will be further described with reference to the accompanying drawings.

A sequential logic circuit experimental device for teaching comprises a base, a panel, a chip pin identification plate and a banana head connecting wire. The structure schematic diagram of the base is shown in fig. 1, the base is a box-shaped cuboid made of an acrylic plate with the thickness of 3 mm, the length of the cuboid is 60 cm, the width of the cuboid is 45 cm, and the height of the cuboid is 5 cm. The structure diagram of the panel is shown in fig. 2, and is also made of an acrylic plate with the thickness of 3 mm, 4 corners of the panel and the base are respectively provided with a screw hole position which is aligned up and down, so that the panel is conveniently fixed on the base through long rod screws. The electronic circuit of protection panel back is walked the line for an important effect of base, and another effect is convenient for openly face the student with this experimental apparatus and stand on the podium, makes things convenient for the student to observe the connection and the state of circuit.

As shown in fig. 2, the panel integrates a light emitting diode unit 101, a nixie tube unit 102, a clock signal unit 103, a chip test unit 104, a logic level unit 105, and a UPS unit 106.

The led unit 101 is composed of 4 red leds with a diameter of 1 cm and a banana head socket, as shown in fig. 2. The purpose of selecting the large-diameter light-emitting diode is to facilitate experimental demonstration and observation of students. The light emitting diode is fixed on the corresponding area of the panel through an LED lamp holder with the diameter of an inner hole of 1 cm, and the LED lamp holder is commercially available. When the LED lamp holder is installed, holes are formed in the corresponding area of the panel according to the actual size of the outer diameter of the lamp holder, and then the LED lamp holder is inserted into the panel and fixed to the back of the panel through nuts. In this embodiment, a lamp base with an outer diameter of 1.35 cm is used. The adjacent center spacing of the 4 lamp holders is appropriate to facilitate opening, and in this embodiment, the center spacing of the adjacent lamp holders is 3.5 cm. A round hole with the diameter of 4 mm is formed at a position 5 cm below each lamp holder and is used for mounting the banana head socket. Next, the red led is placed in the lamp holder, the cathode of the led is connected to the ground port of the UPS unit 106 through a resistor with a resistance of 4.7K Ω on the back of the panel (all resistors in the led unit 101 have a resistance of 4.7K Ω, and the connection is made by wire bonding), and the anode of the led is connected to the banana head socket. As shown in the LED unit 101 of fig. 2, "LED 1" to "LED 4" represent 4 red LEDs with a diameter of 1 cm, and anodes of these 4 LEDs are respectively connected to the banana head sockets "L1" to "L4", and the specific circuit is shown in the sub-circuit diagram with reference numeral 101 of fig. 3, in which the element numerals "D1" to "D4" represent the aforementioned 4 LEDs, respectively.

The main function of the led unit 101 is to display the level of the output terminal of the sequential logic circuit, which will be described in detail in the following embodiments. In order to verify whether the mounted leds are successful, one plug of the banana head connecting line may be inserted into the power port of the UPS unit 106 in fig. 2, i.e. into the banana head socket marked as "V1", and the other plug of the banana head connecting line is inserted into the banana head sockets marked as "L1", "L2", "L3" and "L4" in the led unit 101 in sequence, and the power switch is pressed to see whether the corresponding leds are lit, thereby verifying whether the led mounting process is problematic.

The nixie tube unit 102 is composed of a nixie tube driving circuit board and a banana head socket; the nixie tube driving circuit board is composed of a driving circuit board 201, a nixie tube and a display decoding chip 74LS48, wherein the nixie tube and the display decoding chip are welded on the driving circuit board 201; all resistors in the nixie tube unit 102 have a resistance of 330 Ω.

As shown in fig. 4, the driving circuit board 201 is a printed circuit board with a length of 10 cm and a width of 8 cm, and has a screw hole position 202, a nixie tube soldering area 203, a display decoding chip soldering area 204, and pads 205 (there are 6 pads). The circuit schematic diagram of the driving circuit board 201 is shown in the sub-circuit diagram of fig. 3, which is denoted by reference numeral 102.

The screw hole sites 202 are distributed at 4 corners of the driving circuit board 201, and the driving circuit board 201 is fixed at the position of the nixie tube unit 102 on the panel through the hole sites by screws.

A2.3-inch common-cathode nixie tube is welded on the nixie tube welding area 203, and a large-size nixie tube is selected for the purpose of facilitating teaching demonstration. It should be noted that, in the large-size nixie tube, since the length of each segment is long (each segment of the 2.3 inch nixie tube is 3 cm long), in order to make the light emitted from the whole segment uniform, 4 LEDs (referred to as small-size LEDs, and noted as LEDs for distinguishing from the large-size LEDs in the LED unit 101) connected in series are usually used in each segment of the nixie tube. Normally, the forward voltage of one red light emitting LED (the voltage for emitting light from the LED) is 1.6V to 1.8V, 4 LEDs are connected in series, and the required voltage is 6.4V to 7.2V. However, in the experimental apparatus, the model of the display decoder for driving the nixie tube is 74LS48, the operating voltage thereof is 5V, the high level voltage of the decoding output is 4.2V to 4.5V, and the output voltage cannot drive the nixie tube (the corresponding segment of the nixie tube emits light). Therefore, the 2.3 inch nixie tube is selected, and the 4 LEDs in each segment are connected in two series and two parallel. Thus, the driving voltage of the corresponding segment is only 3.2V to 3.6V, which is lower than the output high level voltage of the 74LS48 chip.

And a display decoder with the model number of 74LS48 is welded on the display decoding chip welding area 204 and is used for driving the 2.3-inch common cathode nixie tube, and the 74LS48 chip is packaged by SOP 16.

The driving circuit board 201 has 6 pads 205, and the pads 205 labeled "a", "B", "C", and "D" are directly connected to the decoding input port of the display decoding chip, so that 4-bit binary BCD encoding input can be realized, where "a" is the lowest bit and "D" is the highest bit. The pad 205 labeled "Vcc" is a power supply input port of the driving circuit board 201, and the pad 205 labeled "GND" is a ground port of the driving circuit board 201.

The steps for fixing the driving circuit board 201 on the panel shown in fig. 2 in the area indicated by the nixie tube unit 102 are as follows:

step 1, a row of 6 circular holes with the diameter of 1.5 mm in total are formed in the proper position of the nixie tube unit 102 on the front surface of the panel, the center distance between two adjacent circular holes in the horizontal direction is 6 mm, the 6 circular holes are flying wire through holes of pads with the labels of "a", "B", "C", "D", "Vcc" and "GND" on the driving circuit board 201, a conducting wire passes through the through holes, one end of the conducting wire is welded on a metal welding piece of a banana head socket on the back surface of the panel, and the other end of the conducting wire is welded on a welding piece 205 of the driving circuit board 201 on the front surface of the panel.

Step 2, as shown in fig. 2, a row of 4 circular holes with a diameter of 4 mm (the outer diameter of the metal rod of the banana head socket is 3.8 mm) is formed below the area of the nixie tube unit 102 on the front surface of the panel, the distance between the centers of two adjacent circular holes in the horizontal direction is 2 cm, and the 4 circular holes are used for fixing banana head sockets with the labels of "a", "B", "C" and "D". Note that these 4 banana head sockets are numbered identically to the left 4 pads on the driver board 201 in order to prevent mistaking in flying wire connections. The banana head socket is inserted into a round hole with the diameter of 4 mm from the front side of the panel, a soldering lug (used for carrying out flying wire welding with the banana head socket) is sleeved on a metal rod of the banana head socket on the back side of the panel, and meanwhile, the banana head socket is fixed by a nut. Similarly, as shown in fig. 2, banana head sockets in other functional units on the panel are all fixed by the same method, the positions of the openings of the banana head sockets are determined according to practical situations, and the detailed implementation steps of the subsequent related functional units are not described in detail.

And 3, selecting the banana head socket marked with the mark A, welding one end of a wire at the position corresponding to the soldering lug on the back surface of the panel, wherein the wire penetrates through the 1.5 mm round hole formed in the step 1, and the other end of the wire is welded to the soldering pad marked with the mark A of the driving circuit board 201 on the front surface of the panel. The steps are repeated to complete the welding of the banana head sockets marked with the numbers of B, C and D and the corresponding welding pads of the driving circuit board 201. For pads labeled "Vcc" and "GND" on driver board 201 that do not have corresponding banana head sockets, these two pads 205 are used to power driver board 201. Specifically, the pads labeled "Vcc" are soldered with wires that pass through the panel and are soldered directly to the power port "+ 5V" of the UPS unit 106 on the back of the panel, i.e., to the pads of the UPS unit 106 banana jack "V1". Similarly, the pads labeled "GND" on driver board 201 are wire bonded to the pads of banana head socket "G1" of UPS unit 106.

And 4, after the welding work is finished, fixing the driving circuit board 201 in the area shown by the nixie tube unit 102 on the front surface of the panel by using 4 screws. The above is a specific implementation step of fixing the driving circuit board 201 on the area shown by the nixie tube unit 102 on the panel shown in fig. 2.

The clock signal unit 103 is composed of a clock signal circuit board 301 and a banana head socket, and the functional unit is used for generating a clock signal with adjustable output frequency, and the frequency range of the output signal is as follows: 0.5 Hz-20 Hz. The specific circuit is shown as a sub-circuit diagram with reference number 103 in fig. 3. In the circuit diagram, a clock signal circuit is mainly realized by an NE555 chip, the output frequency is continuously adjustable by changing the resistance value of a potentiometer RV1, and all components in the circuit diagram are welded in a component welding area 302. In the area shown by the clock signal unit 103 on the front surface of the panel, a row of 3 round holes with the diameter of 1 mm in total are formed at a position 8 cm away from the top end of the area, the distance between the centers of two adjacent round holes in the horizontal direction is 2.5 mm, and the 3 round holes are flying wire through holes. 2 round holes with the diameter of 4 mm are arranged 2 cm below the round hole with the diameter of 1 mm and are used for installing banana head sockets CP1 and CP 2. As shown in fig. 5, the clock signal board 301 has 3 pads 205, labeled "Vcc", "GND", and "CP", respectively. A round hole 1 mm in diameter (the leftmost hole) is selected and a wire is passed through the hole, one end of which is soldered to a pad labeled "Vcc" and the other end is soldered to a metal pad labeled "V1" in the back of the panel of the UPS unit 106. Similarly, the bonding pad labeled "GND" on the clock signal board 301 is connected to the banana head socket labeled "G1" in the UPS unit 106 by flying lead bonding. The pads "CP" are soldered to the banana head sockets "CP 1" and "CP 2" by flying leads. After all the flying leads are soldered, the clock signal circuit board 301 is fixed to the area shown by the clock signal unit 103 on the front surface of the panel shown in fig. 2 by 4 screws.

The clock signal unit 103 mainly provides a clock signal for sequential logic. It should be noted that the clock signals output by the banana head sockets "CP 1" and "CP 2" in the unit are the same and originate from the same signal source (i.e. both banana head sockets are connected to the 3 pins of the NE555 chip, see in particular the sub-circuit diagram labeled 103 in fig. 3).

The chip test unit 104 is composed of a locking socket and a banana head socket. It should be noted that, in the process of testing the sequential logic chip by the unit, a chip pin identification plate (as shown in fig. 6 to 8) matching with the chip model needs to be used, so the positions of the banana head socket and the locking seat on the unit need to match with the positions of the chip pin identification plate shown in fig. 6 to 8. That is, the center distance between two adjacent round holes in the horizontal direction of the banana head socket in the chip testing unit 104 is identical to the center distance between two adjacent round holes in the horizontal direction on the chip pin identification plate shown in fig. 6 to 8, and both are 6 cm; the center distance of the banana head socket in the chip test unit 104 in the vertical direction is the same as the center distance of two adjacent circular holes in the vertical direction on the chip pin identification plate shown in fig. 6-8, and both the distances are 15 cm. Meanwhile, it is also necessary to ensure that the locking seat in the chip testing unit 104 matches with the rectangular hole site with the label of "17" on the chip pin identification plate shown in fig. 6 to 8, that is, when the chip pin identification plate is embedded into the banana head socket in the chip testing unit 104, the locking seat in the chip testing unit 104 can pass through the rectangular hole site with the label of "17" on the chip pin identification plate shown in fig. 6 to 8, so as to facilitate the fixing of the chip, and the banana head socket can pass through the corresponding round hole and play a role in fixing the chip pin identification plate.

In this embodiment, a locking socket with 16 pins is used, the diameter of the pin is 0.8 mm, the length of the pin is 1 cm, and the locking socket is commercially available. Two rows of 16 circular holes with the diameter of 1 mm are arranged at the left side of the chip testing unit 104 on the front surface of the panel for fixing the locking seat. The center distance between two adjacent round holes in the horizontal direction is 2.5 mm, and the center distance between two adjacent round holes in the vertical direction is 10 mm. And (4) coating 101 glue on the bottom of the locking seat, inserting the locking seat into the two rows of round holes, and fixing the locking seat and the panel together through the 101 glue. Note that the position of the fixed locking seats should match the rectangular holes labeled "17" on the chip pin identification plate (as shown in fig. 7 and 8). The 16 pins of the locking socket are connected with the corresponding banana head socket by adopting a flying wire form at the back of the panel, and the specific circuit is shown as a sub-circuit diagram with the reference number 104 in fig. 3.

The chip testing unit 104 is mainly used for testing 3 models of sequential logic chips, such as CD4027, CD4510, and 74LS194, and the testing process is described in detail in the following embodiments.

The chip pin identification board comprises a CD4027 chip pin identification board (shown in FIG. 6), a CD4510 chip pin identification board (shown in FIG. 7) and a 74LS194 chip pin identification board (shown in FIG. 8). The three types of chip pin identification plates are all made of acrylic plates with the length of 50 cm, the width of 20 cm and the thickness of 2 mm, and the length and the width of the plates are matched with the size of the chip test unit 104 on the panel shown in fig. 2, so that the chip test is convenient.

As shown in fig. 6, two rows of round holes marked as "1" to "8" and "9" to "16" are formed in the pin identification plate of the CD4027 chip, the inner diameter of each round hole is 7.8 mm, which is slightly larger than the outer diameter (7.6 mm) of the plastic round head at the top end of the banana head socket used by the chip testing unit 104 on the panel, so that the pin identification plate of the chip can be conveniently embedded into the chip testing unit 104 through the banana head socket. In the circular holes 1 to 8 and the circular holes 9 to 16, the distance between the centers of two adjacent circular holes in the horizontal direction is 6 cm, and the distance between the centers of two rows of circular holes in the vertical direction is 15 cm. The pin identification plate of the CD4027 chip is provided with a rectangular hole marked as '17', the length of the hole is 6.5 cm, and the width of the hole is 2.5 cm. The dimension of the rectangular hole is larger than the dimension (5.8 cm × 1.8 cm) of the locking seat of the chip testing unit 104 on the panel, so that the locking seat passes through the rectangular hole on the chip pin identification plate, and the chip is conveniently fixed.

The CD4027 chip is a JK trigger, and two independent JK triggers are integrated in the chip, as shown in FIG. 6

The pin corresponds to the input/output port of the first JK trigger;

the pin corresponds to the input/output port of the second JK flip-flop. An enlarged version of the schematic diagram of the CD4027 chip and the pin identification text are printed in the middle area of the pin identification board shown in fig. 6. Of a chip

The pin is an asynchronous set port and is identified by the letter "S1"; of a chip

The pin is an asynchronous reset port, identified by the letter "R1"; of a chip

The pin is a clock signal input port and is identified by the letter "cp 1"; of a chip

And

the pins are synchronous data input ports, identified by letters "J1" and "K1", respectively; of a chip

And

the pins are complementary output ports, respectively designated by the letters "Q1" and

to identify. The above is the function of the input/output port of the first JK flip-flop inside the CD4027 chip, and similarly,

input/output port function and of the second JK flip-flop corresponding to the pin

The pins have the same function, and for the purpose of distinguishing, the identifiers of the two groups of pins are distinguished by Arabic numerals "1" and "2", respectively. Of a chip

The pin is a grounding port and is in letter shape"GND"; of a chip

The pin is a power port, identified by the letter "Vcc". The chip schematic diagram, the pin identification and the connecting dotted lines between the chip pins and the upper and lower rows of round holes can be printed on the acrylic plate in a UV printing mode (entrusted to relevant UV printing merchants for customization). Through the design, the functions of all pins of the CD4027 chip are clear and visible, and teaching demonstration is facilitated.

Similarly, the pin identification plate of the CD4510 chip shown in fig. 7 and the pin identification plate of the 74LS194 chip shown in fig. 8 are identical in structure to the pin identification plate of the CD4027 chip, and the only difference is that the identification characters of the chip pins are different, which is not repeated here.

The logic level unit 105 is composed of a single-pole double-throw switch, a banana head socket and 2 5Pin exclusion circuits. In this embodiment, the single pole double throw switch is a toggle switch model MTS102, which is commercially available. The main reason for using the button switch is that the nut is arranged on the button switch, so that the button switch is convenient to fix on a panel. As shown by logic level cells 105 in FIG. 2, "SW 1" through "SW 8" represent 8 single pole double throw switches. A row of 8 round holes with the diameter of 7 mm is arranged in the area of the logic level unit 105 on the front surface of the panel, and the distance between the centers of two adjacent round holes in the horizontal direction is 4 cm. The leftmost hole is selected, the handle of a single-pole double-throw switch (toggle switch) is inserted into the hole from the back of the panel, and the switch is fixed to the panel by a nut on the front of the panel. The specific circuit is shown in the sub-circuit diagram 105 of FIG. 3, in which both resistors RP1 and RP2 have a resistance of 5.1K Ω. On the back of the panel, the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit 106, the input end of the other side of the single-pole double-throw switch is connected with the 2 pin of the exclusion, the common end (1 pin) of the exclusion is connected with the power output port of the UPS unit 106, and the middle output end of the single-pole double-throw switch is connected with the banana head socket O1. In the same way, the remaining 7 SPDT switches SW 2-SW 8 are connected to the exclusion circuit, UPS unit 106 and corresponding banana head sockets in sequence.

The output end of the logic level unit 105 provides a high level or a low level for the circuit, as shown in the sub-circuit diagram labeled 105 in fig. 3, when the single-pole double-throw switch SW1 is pulled to the upper end, the output end is connected to the power supply through the exclusion, that is, the banana head socket O1 outputs a high level at this time; when the single-pole double-throw switch SW1 is turned to the lower end, the output end is directly connected with the ground, namely the banana head socket O1 outputs low level. The level output by the banana head socket O1 can also be verified by the LED unit 101, i.e. a banana head connecting wire is used, one end of which is inserted into the banana head socket O1 of the logic level unit 105, and the other end of which is inserted into the banana head socket L1 of the LED unit 101, and the single-pole double-throw switch is toggled to observe whether the LED1 is turned on, if so, it indicates that the banana head socket O1 of the logic level unit 105 outputs a high level, otherwise, it outputs a low level. In verifying the logic function of the sequential logic chip, the logic level unit 105 is required, which can be seen in the above embodiments.

The UPS unit 106 is composed of a 5V power socket, a UPS power module, a 14500 lithium battery, a power switch, and a banana head socket, and is specifically arranged as the UPS unit 106 in fig. 2. In this embodiment, the 5V power socket is a pure copper socket with a nut, model number QZ7034-M9-2.1, and the diameter of the opening is 9 mm. The UPS power module is a miniature circuit board with a size of 3.5 cm × 1.5 cm, and the circuit board has 6 ports, specifically, as shown in a sub-circuit diagram with reference number 106 in fig. 3, the corresponding device is named as "UPS", where two ports with reference numbers "1" and "2" are power input terminals and are connected with the positive electrode and the negative electrode of a 5V power socket; the positive pole of the 5V power socket is connected with the port 1, and the negative pole is connected with the port 2; the two ports with the labels of 3 and 4 are battery input ends and are respectively connected with the anode and the cathode of a 14500 lithium battery; the two ports marked as '5' and '6' are power output ports, the '5' port is the grounding end of the whole circuit system, the '6' port outputs standard 5V voltage and maximum output current 1A, and the '6' port is connected with the banana head socket through a power switch to supply power to the whole device. All of the components of the UPS unit 106 are commercially available in which the 14500 lithium battery is secured to the front of the faceplate by a battery compartment with screw holes in the bottom.

The main functions of the UPS unit 106 are two, one is that, in the case of an external power input (the power of a computer or a mobile power source can be connected to a 5V power socket through a USB patch cord), the external power can charge the 14500 lithium battery in the UPS unit 106 and also supply power to the whole experimental apparatus. And secondly, when no external power supply is available, the UPS module automatically converts the voltage of the 14500 lithium battery into standard 5V voltage to be output and supplies power to the whole experimental device. The UPS unit 106 thus provides uninterruptible power supply for the entire experimental apparatus, and has the advantages of flexibility and convenience, and is convenient for experimental operations without power supply.

Next, a functional test of the sequential logic chips CD4027 and CD4510 will be described based on two embodiments of the present invention, which correspond to the circuits shown in fig. 9 and 10, respectively. The testing of the 74LS194 chip (corresponding to the circuit shown in FIG. 11) is similar to the testing of the CD4027 chip and will not be described again here.

As mentioned above, two independent JK flip-flops are integrated inside the CD4027 chip, and in the circuit shown in fig. 9, the two JK flip-flops are respectively controlled by "U1: a "and" U1: b ". Next, with reference to the sub-circuit diagrams of fig. 3 labeled 101, 103, 104, 105 and 106, the application of the present invention (on the panel shown in fig. 2) to the JK flip-flop "U1" in the CD4027 chip will be described: a "(since the testing procedure of another JK flip-flop" U1: B "is similar, it is omitted in this embodiment) includes the following steps:

step 1, placing a CD4027 chip in a locking seat in a chip testing unit 104 (note that the notch direction of the chip is towards the left) on a panel shown in fig. 2, and pressing a locking rod to fix the chip; the pin identification plate of the CD4027 chip shown in fig. 6 is embedded into the chip testing unit 104, that is, 16 circular holes on the pin identification plate are embedded into the banana head socket in the chip testing unit 104 and kept stable, and the locking seat in the chip testing unit 104 is exposed from the rectangular hole on the pin identification plate;

step 2, according to the circuit shown in fig. 9 and by combining the pin identifier on the pin identifier board of the CD4027 chip in fig. 6, the 1 pin and the 2 pin of the chip are JK flip-flops "U1: a complementary output port a, which connects banana head sockets labeled "1" and "2" on the chip test unit 104 with banana head sockets labeled "L1" and "L2" on the light emitting diode unit 101, respectively, i.e., the complementary output end level of the JK flip-flop is connected to 2 LEDs in the light emitting diode unit 101, and whether the flip-flop stores a high level or a low level is tested according to whether the LEDs are turned on;

step 3, according to the pin identifier on the pin identifier board of the CD4027 chip in fig. 6, the 8 pins and the 16 pins of the chip are the ground port and the power port, on the panel shown in fig. 2, the banana head socket "G1" of the UPS unit 106 is connected with the banana head socket labeled "8" in the chip test unit 104 by using the banana head connection wire, and the banana head socket "V1" of the UPS unit 106 is connected with the banana head socket labeled "16" in the chip test unit 104 by using the banana head connection wire, so that the power supply to the CD4027 chip is completed;

and 4, testing the functions of the asynchronous set port and the asynchronous reset port of the CD4027 chip. According to the circuit shown in fig. 9 and in combination with the pin identification on the pin identification board of the CD4027 chip in fig. 6, banana head connection wires are used to connect banana head sockets labeled "O1" and "O4" on the logic level unit 105 to banana head sockets labeled "7" and "4" on the chip test unit 104, respectively, that is, the logic levels of the "O1" and "O4" ports are connected to the 7 pin (set port) and the 4 pin (reset port) of the CD4027 chip, respectively, the switch of the UPS unit 106 is pressed to turn on the power supply, the single-pole double-throw switches SW1 and SW4 in the logic level unit 105 are toggled to different levels, and the states of the LED1 and LED2 in the LED unit 101 on the panel are observed, so as to verify the asynchronous set and asynchronous reset functions of the chip (note that no clock signal is needed for verifying the asynchronous port functions);

step 5, verifying the functions of the synchronous data input ports (J port and K port) under the condition that the asynchronous set port and the asynchronous reset port of the CD4027 chip are both invalid levels (namely, the 7 pins and the 4 pins of the chip are both connected with low levels), and at the moment, accessing a clock signal: according to fig. 6 and 9, on the panel shown in fig. 2, banana head socket labeled "CP 1" in clock signal unit 103 is connected to banana head socket labeled "3" in chip test unit 104 using banana head connection line, i.e. the clock signal is connected to pin 3 of CD4027 chip; subsequently, banana head sockets marked with "O2" and "O3" on the logic level unit 105 are connected with banana head sockets marked with "6" and "5" on the chip test unit 104 by using banana head connecting wires, namely, the logic levels of the ports of "O2" and "O3" are respectively connected to the 6 pin (J port) and the 5pin (K port) of the CD4027 chip, the single-pole double-throw switches SW2 and SW3 in the logic level unit 105 are switched to different levels, and the states of the LED1 and the LED2 in the light emitting diode unit 101 on the panel are observed, so that the J port and K port functions of the chip are verified.

The circuit construction on the panel of the utility model is completed by the above steps for the CD4027 chip test circuit shown in FIG. 9. Note that: the above steps are only performed for one set of JK flip-flops "U1: a 'test circuit construction is carried out, and for another JK trigger' U1: b ", the same procedure can be used for the test. Similarly, the testing of the chip 74LS194 also involves led units, and the testing process is substantially similar, and therefore is not described in detail here. Finally, it should be noted that all circuit diagrams in the present invention are drawn by using the software of Proteus, the software ignores the power pins and the ground pins of all digital chips (taking fig. 9 as an example, there are no 8 pins and 16 pins in the circuit diagram), and defaults to automatically power on the circuit, but this does not affect the function introduction and demonstration of the circuit.

Next, another embodiment according to the present invention, that is, testing the CD4510 chip, will be described. As shown in fig. 10, the specific steps of building a counter chip CD4510 functional test circuit on the panel shown in fig. 2 by combining the sub-circuit diagrams marked with

reference numerals

102, 103, 104, 105 and 106 in fig. 3 are as follows:

step 1, placing a CD4510 chip into a locking seat in a chip testing unit 104 (note that the notch direction of the chip is towards the left) on a panel shown in fig. 2, and pressing a locking rod to fix the chip; embedding the pin identification plate of the CD4510 chip shown in FIG. 7 into the chip testing unit 104, that is, the 16 circular holes on the pin identification plate are embedded into the banana head sockets in the chip testing unit 104 and kept stable, and the locking seats in the chip testing unit 104 are exposed from the rectangular holes on the pin identification plate;

step 2, according to the circuit shown in fig. 10, the input port of the CD4510 chip is set on the panel shown in fig. 2: banana head sockets marked with "O1", "O2", "O3" and "O4" on the logic level unit 105 are connected with banana head sockets marked with "4", "12", "13" and "3" on the chip test unit 104, respectively, using banana head connection lines, that is, the levels of the banana head sockets marked with "O1", "O2", "O3" and "O4" are sequentially connected to the synchronous set data input ports (pins 4, 12, 13 and 3) of the CD4510 chip; the banana head socket marked with the number "O5" on the logic level unit 105 is connected with the banana head socket marked with the number "10" on the chip test unit 104 by using a banana head connection wire, i.e. the level of the banana head socket marked with the number "O5" is connected to the "addition/subtraction" count control port (10 pins) of the CD4510 chip; a banana head socket marked with 'O6' on the logic level unit 105 is connected with a banana head socket marked with '1' on the chip test unit 104 by using a banana head connecting wire, namely, the level of the banana head socket marked with 'O6' is connected to a synchronous setting control port (pin 1) of the CD4510 chip; a banana head socket marked with 'O7' on the logic level unit 105 is connected with a banana head socket marked with '9' on the chip test unit 104 by using a banana head connecting wire, namely, the level of the banana head socket marked with 'O7' is connected to an asynchronous zero clearing control port (9 pins) of a CD4510 chip; the synchronous setting, asynchronous clearing and counting functions of the CD4510 chip are mainly tested in the next steps. It should be noted that the carry input port (5 pins) of the chip needs to be connected to a low level to verify the relevant functions of the CD4510, specifically, the banana head socket labeled "5" in the chip test unit 104 is connected to the banana head socket labeled "G1" in the UPS unit 106 through the banana head connection line;

step 3, according to the circuit shown in fig. 10, the banana head sockets labeled "6", "11", "14" and "2" on the chip testing unit 104 and the nixie tube unit 102 are labeled as follows respectively by using banana head connecting wires: banana head sockets of "a", "B", "C" and "D" are connected, i.e. the count output port (pins 6, 11, 14 and 2) of the CD4510 chip is electrically level-connected to the decode input port (pins 7, 1, 2 and 6) of the display decode chip 74LS48 in the nixie tube unit 102;

step 4, a banana head socket marked with 'CP 1' in the clock signal unit 103 is connected with a banana head socket marked with '15' in the chip test unit 104 by using a banana head connecting wire, namely, a clock signal is accessed to a 15 pin of the CD4510 chip;

step 5, according to the pin identifier on the pin identifier board of the CD4510 chip shown in fig. 7, where 8 pins and 16 pins of the chip are a ground port and a power port, on the panel shown in fig. 2, the banana head socket "G1" of the UPS unit 106 is connected to the banana head socket labeled "8" in the chip test unit 104 by using a banana head connection line, and the banana head socket "V1" of the UPS unit 106 is connected to the banana head socket labeled "16" in the chip test unit 104 by using a banana head connection line, so that power supply to the CD4510 chip is completed (note that, in step 2, the banana head socket labeled "G1" in the UPS unit 106 is already occupied, and in a specific connection process, a jack with a diameter of 2 mm at the top of the banana head plastic handle is used to implement cascade connection of the lines through the jack);

and 6, after the circuit building of the steps is completed, pressing a switch of the UPS unit 106 to switch on a power supply, and testing the synchronous setting function of the CD4510 chip as follows: toggling the single-pole double-throw switch SW7 in the logic level unit 105 to make the banana head socket labeled "O7" output a low level even if the asynchronous clear control port of the CD4510 chip is an invalid level; 4 switches SW 1-SW 4 are toggled, so that the banana head socket labeled as "O1" outputs high level, and the banana head sockets labeled as "O2", "O3" and "O4" output low level; the single-pole double-throw switch SW6 is pulled to enable the banana head socket with the label of O6 to output a high level, at the moment, a synchronous setting number control port (1 pin) of a CD4510 chip is an effective level, the level of a synchronous setting number data input port (namely the output level of the banana head socket with the labels of O1 to O4) is read into the CD4510 chip under the action of a clock signal rising edge, the output level of a counting output port is the level of the synchronous setting number data input port, and the level drives a nixie tube on the nixie tube unit 102 to display an Arabic number '1' through a display decoder; different level access can be realized by toggling 4 switches SW 1-SW 4, and the number displayed by the nixie tube can be observed;

and 7, testing the asynchronous zero clearing function: the single-pole double-throw switch SW7 in the logic level unit 105 is toggled, so that the banana head socket labeled "O7" outputs a high level, since the 9 pin of the CD4510 chip is an asynchronous port, no clock signal is needed to cooperate, as long as the pin is connected to the high level, the CD4510 chip executes a clear operation, and at this time, the nixie tube on the nixie tube unit 102 displays an arabic numeral "0";

and 8, finally testing the counting function: at this time, the asynchronous clear control port and the synchronous count control port (pin 9 and pin 1) of the CD4510 chip are required to be at low level, that is, the single-pole double-throw switches SW7 and SW6 in the logic level unit 105 are toggled, so that the banana head sockets labeled as "O7" and "O6" both output low level, and thus the CD4510 chip counts under the action of the clock signal. Note that the CD4510 chip is an up-down counter, and can perform both up-counting and down-counting, and the up-counting and down-counting function selection is realized through the "up/down" count control port (10 pins) of the chip. Specifically, the single-pole double-throw switch SW5 in the logic level unit 105 is toggled, so that the banana head socket labeled "O5" outputs a high level, and at this time, the nixie tube on the nixie tube unit 102 will sequentially display several arabic numbers of "0", "1", … "and" 9 "(i.e., perform addition counting); if the banana head socket labeled "O5" outputs a low level, the nixie tube on the nixie tube unit 102 will sequentially display several arabic numerals "9", "8", … "and" 0 "(i.e. perform subtraction counting).

The circuit construction of the CD4510 chip test circuit shown in FIG. 10 on the panel of the present invention is completed through the above steps. The utility model discloses under the unchangeable circumstances of other functional unit, only need change different chips in chip test unit 104's locking seat, refer to corresponding chip pin sign board alright carry out chip logic functional test simultaneously, it is nimble convenient to use. Similarly, according to the actual course requirement, the functional test of other models of sequential logic chips can be completed, for example: a double four digit decimal sequential logic chip 74LS390 and a decimal divide counter chip CD 4017. Here, only the pin identification board of the corresponding chip needs to be manufactured. Since the steps are similar, they are not described in detail here.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The utility model provides a sequential logic circuit experimental apparatus is used in teaching, includes base, panel, chip pin sign board and banana head connecting wire, its characterized in that: the panel integrates a light emitting diode unit, a nixie tube unit, a clock signal unit, a chip testing unit, a logic level unit and a UPS unit;

2. The sequential logic circuit experimental device for teaching of claim 1, wherein: the base is of a cuboid structure formed by single-layer acrylic plates, and the panel is a single-layer acrylic plate and is fixed on the base through long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

3. The sequential logic circuit experimental device for teaching of claim 1, wherein: the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

4. The sequential logic circuit experimental device for teaching of claim 1, wherein: the nixie tube is a red 2.3-inch one-bit common-cathode nixie tube, wherein 4 LEDs are arranged in each segment, and are connected in a two-string and two-parallel mode, namely, every two LEDs are connected in series, and then the two groups of LEDs which are connected in series are connected in parallel; the model of the display decoding chip is 74LS 48.

5. The sequential logic circuit experimental device for teaching of claim 1, wherein: the output frequency of the clock signal is 0.5 Hz-20 Hz, and the output frequency is continuously adjustable through a potentiometer.

6. The sequential logic circuit experimental device for teaching of claim 1, wherein: the chip testing unit needs to use corresponding chip pin identification plates when performing chip testing, and the chip pin identification plates comprise a CD4027 chip pin identification plate, a CD4510 chip pin identification plate and a 74LS194 chip pin identification plate.

7. The sequential logic circuit experimental device for teaching of claim 1, wherein: the lithium battery is a 14500 lithium battery.

8. The sequential logic circuit experimental device for teaching of claim 1, wherein: the banana head connecting wire both ends respectively have a plug, the plug comprises plastics handle and metal lotus flower head, the diameter of metal lotus flower head with the hole diameter of banana head socket is 2 millimeters, the top of plastics handle has the jack that the internal diameter is 2 millimeters.