CN210129334U

CN210129334U - Combined logic circuit experimental device for teaching

Info

Publication number: CN210129334U
Application number: CN201921036877.0U
Authority: CN
Inventors: 郭立强; 刘恋
Original assignee: Huaiyin Normal University
Current assignee: Huaiyin Normal University
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-03-06
Anticipated expiration: 2029-06-28

Abstract

The utility model discloses a combined logic circuit experimental device for teaching, which comprises a base, a panel, a chip pin identification plate and a banana head connecting wire; the panel integrates a nixie tube unit, a light emitting diode unit, a chip testing unit, a logic level unit and a UPS unit; the chip pin identification boards comprise a 74LS138 chip, a 74LS148 chip, a 74LS283 chip, a 74LS48 chip and a 74LS42 chip pin identification board. The experimental device is flexible to use and easy to realize, and a user can connect all the functional units into a combined logic chip test circuit through the banana head connecting wire and verify and demonstrate the function of the combined logic chip by combining the chip pin identification board; the experimental apparatus adopts unique jumbo size design to make the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, be convenient for use widely on colleges and universities classroom, have wide application prospect.

Description

Combined logic circuit experimental device for teaching

Technical Field

The utility model relates to the field of electronic technology, concretely relates to combinatorial logic circuit experimental apparatus is used in teaching.

Background

The course is a necessary course for the electronic specialties such as electronic science and technology, electronic information engineering, communication engineering and the like in colleges and universities, and the professional basis of non-electronic specialties such as computer science and technology, Internet of things engineering, physics and the like, plays an important role in the whole talent training system, and lays a good foundation for the study of courses such as subsequent digital system design, singlechip, computer composition principle, integrated circuit design and the like. The combinational logic circuit plays a role in the beginning and the end of the course of digital electronic technology foundation. In the course of explaining the contents of the combinational logic circuit in a classroom, besides explaining the analysis and design method of the combinational logic circuit, some combinational logic chips are also explained in a focused way, which specifically includes: encoders, decoders, and adders, etc., which are the basic components that make up other types of digital circuits. Meanwhile, the fact that the knowledge of the combinational logic circuit is firm directly influences the learning of the contents of the subsequent sequential logic circuit.

At present, the experiment conditions of the electrical major of all colleges and universities are better, and the electrical major laboratories are equipped with digital circuits. However, in the existing course system of colleges and universities, the teaching mode of "theoretical course + experimental course" is adopted in the course, i.e. theoretical teaching is firstly performed in a multimedia classroom, and then experimental teaching is performed in a professional laboratory. The digital electronic technology foundation is a highly practical course, and if knowledge is infused in theoretical teaching, the learning effect of students is poor. If experimental demonstration is alternated in the teaching process, a plurality of problems exist. For example, the laboratory equipment in a professional laboratory is either a large laboratory platform with a large floor space or a relatively heavy laboratory box. The large experiment platform can not be moved to a common multimedia classroom for class demonstration. For the experimental box, because the volume is small, the functional units are many, which results in high element density, and the LED, the nixie tube, the switch and the like all use small-sized elements. During experiment demonstration, only the front two rows of students can clearly see the experiment, and the later students can hardly see the experiment process and results clearly. Meanwhile, the experiment box adopts 220V alternating current for power supply, and the mobility is poor. In addition, if the experiment box is to face the student to perform classroom demonstration, the flip cover on the experiment box can block the sight of the student, and the demonstration is very inconvenient.

For non-electronic specialties such as computer science and technology, Internet of things engineering and physics, the situation is also not optimistic. For colleges and universities with poor experimental conditions, because non-electric professionals do not have specialized laboratories, the experiments of the class usually adopt EDA simulation based on a computer to complete relevant experimental teaching. This is most common for computer-like specialties. Finally, the learning experience of students is poor, the teachers lack intuition in the explanation of knowledge points, and the teaching atmosphere is quite tedious.

According to questionnaires for college student course study by authorities such as Max, students often are most interested in lesson modes with strong interactivity and courses of experimental demonstration, and are most concentrated in energy when attending lessons. But often cannot raise the spirit of PPT infusion type teaching. According to the problem that meets in this kind of course of the digital electronics technology basis gives lessons in-process, can't use hardware equipment conveniently to carry out the combinational logic circuit function demonstration on theoretical class promptly, the utility model provides a combinational logic circuit experimental apparatus convenient to classroom teaching demonstration for carry out functional test to the combinational logic chip. The device is a teaching instrument for combined logic circuit experimental demonstration, is also a good carrier for teacher-student interaction, plays a positive exemplary role in classroom teaching, can improve classroom attention and learning initiative of students, and has good popularization and use prospects.

Disclosure of Invention

To the problem that exists among the prior art, improve the quality of giving lessons in class, the utility model provides a teaching is with combination logic circuit experimental apparatus, the utility model discloses the technical scheme who takes as follows:

a teaching combinational logic circuit experimental device comprises a base, a panel, a chip pin identification plate and a banana head connecting wire; the panel integrates a nixie tube unit, a light emitting diode unit, a chip testing unit, a logic level unit and a UPS unit; the chip pin identification boards comprise a 74LS138 chip pin identification board, a 74LS148 chip pin identification board, a 74LS283 chip pin identification board, a 74LS48 chip pin identification board and a 74LS42 chip pin identification board;

the nixie tube unit is composed of a 2.3-inch common-cathode nixie tube, a nixie tube adapter plate, a resistor and a banana head socket, a common port of the nixie tube is connected with a ground port of the UPS unit, and segment ports of the nixie tube, which are marked as 'a', 'b', 'c','d', 'e', 'f' and 'g', are connected with the banana head socket through the resistor;

the light-emitting diode unit consists of a light-emitting diode, a resistor and a banana head socket, the cathode of the light-emitting diode is connected with the ground port of the UPS unit through the resistor, and the anode of the light-emitting diode is connected with the banana head socket;

the chip testing unit consists of a locking seat and a banana head socket, and a pin of the locking seat is connected with the banana head socket;

the logic level unit is composed of a single-pole double-throw switch, a banana head socket and a resistor divider, wherein the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit, the input end of the other side of the single-pole double-throw switch is connected with the power output port of the UPS unit through the resistor divider, and the middle output end of the single-pole double-throw switch is connected with the banana head socket;

the UPS unit is by 5V supply socket, UPS power module, the lithium cell, switch and banana head socket constitute, 5V supply socket's the positive pole and the negative pole link to each other with UPS power module's power input port, the positive pole and the negative pole of lithium cell link to each other with UPS power module's battery port, UPS power module's the positive output of passing through switch links to each other with banana head socket, for whole experimental apparatus power supply, UPS power module's the output negative pole links to each other with banana head socket, as whole experimental apparatus's earthing terminal.

Preferably, the base is a cuboid structure formed by single-layer acrylic plates, and the panel is a single-layer acrylic plate and is fixed on the base through long-rod screws; the base and the panel are 60 cm long and 45 cm wide.

Preferably, the nixie tube is a red 2.3-inch one-bit common cathode nixie tube, wherein 4 light-emitting diodes are arranged in each segment and connected in a two-string and two-parallel mode.

Preferably, the nixie tube is fixed in the nixie tube unit area on the panel through the nixie tube adapter plate.

Preferably, the diameter of the light emitting diode is 1 cm, and the light emitting color is red.

Preferably, a pin identification board of a corresponding chip is required to be used when the chip test unit performs a chip test.

Preferably, the lithium battery is a 18650 lithium battery.

Preferably, each there is a plug at banana head connecting wire both ends, the plug comprises plastics handle and metal lotus flower head, the diameter of metal lotus flower head with the hole diameter of banana head socket is 2 millimeters, the top of plastics handle has the jack that the internal diameter is 2 millimeters.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the utility model discloses in the test to different model combinational logic chips is accomplished through the chip pin marking board that uses corresponding model on chip test unit, and the printing has large size chip pin picture on the chip pin marking board, makes chip pin function clear, only needs to change chip pin marking board alright realize the test to different model chips, and the commonality is strong.

2. The utility model discloses a functional unit is abundant, easily realizes that user's accessible banana head connecting wire accomplishes the test of the combinational logic chip of different models with each functional unit connection, uses in a flexible way.

3. The utility model discloses a base, panel and chip pin sign board all adopt the preparation of ya keli board, have weatherability and acid and alkali resistance good, advantages such as the impact resistance is strong, easy cleanness and insulating nature are good to the cost is low, the sexual valence relative altitude.

4. The utility model discloses the base is 60 centimetres with the panel length in, and wide for 45 centimetres, except chip pin sign board, other units on the panel also print the jumbo size identification chart that has the component, adopt 2.3 inches's jumbo size charactron on the panel, and emitting diode's diameter is 1 centimetre, and this kind of unique jumbo size design makes the utility model discloses have good classroom demonstration function, be the interactive good experiment carrier of teachers and students, conveniently use widely on colleges and universities classroom, have wide use value and application prospect.

Drawings

Fig. 1 is a schematic view of a base of the present invention;

FIG. 2 is a structural diagram of the middle panel of the present invention;

FIG. 3 is a circuit diagram of each unit on the middle panel of the present invention;

fig. 4 is a schematic view of a nixie tube adapter plate of the present invention;

FIG. 5 is a pin identification plate of the 74LS138 chip of the present invention;

fig. 6 is a pin identification plate of a 74LS148 chip of the present invention;

fig. 7 is a pin identification plate of 74LS283 chip of the present invention;

fig. 8 is a pin identification plate of the 74LS48 chip of the present invention;

fig. 9 is a pin identification plate of the 74LS42 chip of the present invention;

fig. 10 is a circuit diagram of a 74LS138 chip under test according to the present invention;

fig. 11 is a circuit diagram of the 74LS148 chip under test in the present invention;

fig. 12 is a circuit diagram of a 74LS283 chip under test according to the present invention;

fig. 13 is a circuit diagram of the 74LS48 chip under test in the present invention;

fig. 14 is a circuit diagram of the 74LS42 chip under test in the present invention.

Reference numerals: 101-nixie tube unit, 102-light emitting diode unit, 103-chip test unit, 104-logic level unit, 105-UPS unit, 201-nixie tube adapter plate, 202-screw hole position, 203-nixie tube welding area, 204-printed wire, 205-bonding pad.

Detailed Description

In order to facilitate the technical solution of the present invention to be understood by the skilled person, the technical solution of the present invention will be further described with reference to the accompanying drawings.

A teaching combinational logic circuit experimental device comprises a base, a panel, a chip pin identification plate and a banana head connecting wire. The structure schematic diagram of the base is shown in fig. 1, the base is a box-shaped cuboid made of an acrylic plate with the thickness of 3 mm, the length of the cuboid is 60 cm, the width of the cuboid is 45 cm, and the height of the cuboid is 5 cm. The structure diagram of the panel is shown in fig. 2, and is also made of an acrylic plate with the thickness of 3 mm, 4 corners of the panel and the base are respectively provided with a screw hole position which is aligned up and down, so that the panel is conveniently fixed on the base through long rod screws. The electronic circuit of protection panel back is walked the line for an important effect of base, and another effect is convenient for openly face the student with this experimental apparatus and stand on the podium, makes things convenient for the student to observe the connection and the state of circuit.

As shown in fig. 2, the panel integrates a nixie tube unit 101, a light emitting diode unit 102, a chip test unit 103, a logic level unit 104, and a UPS unit 105. Note that not all details of the units are shown in fig. 2, for example, the core function element of the nixie tube unit is the nixie tube, so the nixie tube adapter plate is simply drawn as a nixie tube label in the nixie tube unit 101 area of the panel.

The chip pin identification boards include a 74LS138 chip pin identification board (shown in FIG. 5), a 74LS148 chip pin identification board (shown in FIG. 6), a 74LS283 chip pin identification board (shown in FIG. 7), a 74LS48 chip pin identification board (shown in FIG. 8) and a 74LS42 chip pin identification board (shown in FIG. 9). The five types of chip pin identification plates are all made of acrylic plates with the length of 50 cm, the width of 20 cm and the thickness of 2 mm, and the length and the width of the five types of chip pin identification plates are matched with the size of the chip test unit 103 on the panel shown in fig. 2, so that the chip test is convenient.

As shown in fig. 5, two rows of round holes labeled "1" to "8" and "9" to "16" are formed in the 74LS138 chip pin identification plate, the inner diameter of each round hole is 7.8 mm, which is slightly larger than the outer diameter (7.6 mm) of the plastic round head at the top end of the banana head socket used by the chip testing unit 103 on the panel, so that the chip pin identification plate can be conveniently embedded into the chip testing unit 103 through the banana head socket. In the circular holes 1 to 8 and the circular holes 9 to 16, the distance between the centers of two adjacent circular holes in the horizontal direction is 6 cm, and the distance between the centers of two rows of circular holes in the vertical direction is 15 cm. The pin identification plate of the 74LS138 chip is provided with a rectangular hole marked as '17', the length of the hole is 6.5 cm, and the width of the hole is 2.5 cm. The overall dimension of the rectangular hole is larger than the overall dimension (5.8 cm × 1.8 cm) of the locking seat of the chip testing unit 103 on the panel, so that the locking seat passes through the rectangular hole on the chip pin identification plate, and the chip is conveniently fixed.

An enlarged version of the 74LS138 chip schematic and pin identification text is printed in the middle area of the 74LS138 chip pin identification board, as shown in FIG. 5, the chip

The pin is a decoding input port and is marked by letters 'A' to 'C'; of a chip

And

the pins are decoding enable ports and are respectively used by letters

And "E1"; of a chip

…、

And

the pins are decoding output ports and are respectively marked by letters

…、

And

to identify; of a chip

The pin is a ground port and is identified by the letter "GND"; of a chip

The pin is a power port, identified by the letter "VCC". The chip schematic diagram, the pin identification and the connecting dotted lines between the chip pins and the upper and lower rows of round holes can be printed on the acrylic plate in a UV printing mode (entrusted to relevant UV printing merchants for customization). Through the design, the functions of all pins of the 74LS138 chip are clearly visible, and teaching demonstration is facilitated.

Similarly, the 74LS148 chip pin id board, the 74LS283 chip pin id board, the 74LS48 chip pin id board and the 74LS42 chip pin id board shown in fig. 6 to 9 are the same as the above 74LS138 chip pin id board in structure, and the only difference is that the identification characters of the chip pins are different, and the description is omitted here.

The nixie tube unit 101 is composed of a 2.3-inch common-cathode nixie tube, a resistor and a banana head socket, a common port of the nixie tube is connected with a ground port of the UPS unit, and ports 'a', 'b', 'c','d', 'e', 'f' and 'g' of the nixie tube are connected with the banana head socket through the resistor. The corresponding circuit diagram of the digital tube unit 101 in fig. 2 is shown as the sub-circuit diagram with reference number 101 in fig. 3, and the circuit diagram is drawn by using the software of Proteus. The purpose of selecting the large-size nixie tube is to facilitate teaching demonstration.

It should be noted that, in the large-sized nixie tube, since the length of each segment is long (each segment of the 2.3 inch nixie tube is 3 cm long), in order to make the whole segment emit light uniformly, 4 LEDs (here, a small-sized LED is used, and a "LED" in the LED unit is a large-sized LED with a diameter of 1 cm) are used inside each segment of the nixie tube, and are connected in series. Normally, the forward voltage of one red light emitting LED (the voltage for emitting light from the LED) is 1.6V to 1.8V, 4 LEDs are connected in series, and the required voltage is 6.4V to 7.2V. However, in the experimental apparatus, the model of the display decoder for driving the nixie tube is 74LS48, the operating voltage thereof is 5V, the high level voltage of the decoding output is 4.2V to 4.5V, and the output voltage cannot drive the nixie tube (the corresponding segment of the nixie tube emits light). Therefore, the 2.3 inch nixie tube is selected, and the 4 LEDs in each segment are connected in two series and two parallel. Thus, the driving voltage of the corresponding segment is only 3.2V to 3.6V, which is lower than the output high level voltage of the 74LS48 chip. In addition, the forward voltage of one emerald LED is 2.0V to 2.3V, and the forward voltage of a blue LED is higher, so that the 74LS48 chip cannot drive the 2.3 inch nixie tube of the two colors.

Because the pin of charactron is thin and comparatively short, inconvenient flying wire welding. Therefore, the utility model discloses a charactron keysets 201 fixes 2.3 inches charactron at charactron unit 101 on the panel.

As shown in fig. 4, the nixie tube interposer 201 is a small circuit board, and has screw hole sites 202 (distributed at 4 corners of the interposer), a nixie tube soldering area 203, printed wires 204 (there are 10 printed wires), and pads 205 (there are 10 pads). Each bonding pad 205 is in good electrical communication with the nixie tube pins, and the bonding pads 205 are connected with the corresponding banana head sockets in the nixie tube unit 101 on the panel through a 330 Ω resistor and in a flying wire welding manner. The nixie tube adapter plate 201 is used for fixing the nixie tube on the panel in the area indicated by the nixie tube unit 101. The specific steps for fixing the nixie tube are as follows:

step 1, welding a nixie tube on a nixie tube adapter plate 201, wherein the nixie tube has 10 pins in total, and each pin is connected with a corresponding bonding pad 205 through a printed wire 204. Each pin of the nixie tube represents the same meaning as the pad label in fig. 4, and "com" represents the ground, and the pad is soldered to the ground port of the UPS unit 105 through a wire on the back of the panel (there are two "com" ports on the nixie tube, and these two ports are connected, only one port needs to be soldered); the 'dp' represents a 'decimal point' on the nixie tube, and the lightening of a segment bit of the 'decimal point' is not involved in the chip testing process, so that the welding pad is not processed at all, namely is suspended; the remaining "a", "b", … "and" g "represent the 7 segments of the nixie tube, and the pads of the 7 segments are connected to the corresponding banana head sockets in the nixie tube unit 101 on the panel through 330 Ω resistors and by flying wire bonding.

And 2, forming a row of 8 round holes with the diameter of 1.5 mm on the nixie tube unit 101 on the front surface of the panel, wherein the center distance between every two adjacent round holes in the horizontal direction is 6 mm, and the 8 round holes are flying wire through holes connected with ' a ', ' b ', … ', ' g ' and ' com ' pads on the nixie tube adapter plate.

Step 3, as shown in fig. 2, a row of 7 circular holes with a diameter of 4 mm (the outer diameter of the metal rod of the banana head socket is 3.8 mm) is formed below the area of the nixie tube unit 101 on the front surface of the panel, the distance between the centers of two adjacent circular holes in the horizontal direction is 2 cm, and the 7 circular holes are used for fixing banana head sockets with the labels "a", "b", … "and" g ". The banana head socket is inserted into a round hole with the diameter of 4 mm from the front side of the panel, a soldering lug (used for carrying out flying wire welding with the banana head socket) is sleeved on a metal rod of the banana head socket on the back side of the panel, and meanwhile, the banana head socket is fixed by a nut. Similarly, the banana head sockets in other functional units on the panel shown in fig. 2 are all fixed by the same method, the positions of the openings of the banana head sockets are determined according to actual conditions, and the implementation steps of the subsequent related functional units are not described in detail.

And 4, selecting the banana head socket marked with the mark "a", welding the position, corresponding to the soldering lug, of the back surface of the panel by using a 330 omega resistor, welding a lead at the other end of the resistor, penetrating the lead through the round hole formed in the step 2, and welding the lead on the bonding pad marked with the mark "a" of the nixie tube adapter plate 201 on the front surface of the panel. Repeating the steps to complete the welding of the banana head sockets marked with the numbers of 'b', 'c' … and 'g' and the corresponding bonding pads of the nixie tube adapter plate. In step 1, a pad labeled "com" on the nixie tube adapter board 201 is soldered with a wire, the wire passes through the last round hole opened in step 2 to the back of the panel, and is soldered directly to the ground port of the UPS unit 105 on the back of the panel, i.e., to a solder pad of a banana head socket at the ground end of the UPS unit 105.

And 5, after the welding work is finished, fixing the nixie tube adapter plate in the area (the position of the nixie tube mark) shown by the nixie tube unit 101 on the front surface of the panel by using 4 screws. The above is a specific implementation procedure for fixing a 2.3-inch nixie tube on the panel in the nixie tube unit 101 area by using the nixie tube adapter plate 201.

After the nixie tube is installed, one plug of the banana head connecting wire is inserted into a power supply port in the UPS unit 105 in fig. 2, namely, the banana head socket marked as "V1" is inserted, the other plug of the banana head connecting wire is sequentially inserted into the banana head sockets marked as "a", "b", … "and" g "in the nixie tube unit 101, a power switch is pressed, whether the corresponding section of the nixie tube is lighted or not is observed, and whether a problem exists in the installation process is verified. When the 74LS48 chip is tested for logic function, the nixie tube unit 101 is used, and the 74LS48 chip is used to drive the nixie tube, and the specific implementation steps are similar to those of the test example of the 74LS138 chip, and are not described again here.

The led unit 102 is composed of 10 red leds with a diameter of 1 cm and a banana head socket, as shown in fig. 2. The purpose of selecting the large-diameter light-emitting diode is to facilitate experimental demonstration and observation of students. The light emitting diode is fixed on the corresponding area of the panel through an LED lamp holder with the diameter of an inner hole of 1 cm, and the LED lamp holder is commercially available. When the LED lamp holder is installed, holes are formed in the corresponding area of the panel according to the actual size of the outer diameter of the lamp holder, and then the LED lamp holder is inserted into the panel and fixed to the back of the panel through nuts. In this embodiment, a lamp base with an outer diameter of 1.35 cm is used. The distance between the centers of the 10 lamp holders is appropriate to facilitate the opening of the holes, and in the embodiment, the distance between the centers of the adjacent lamp holders is 3.5 centimeters. A round hole with the diameter of 4 mm is formed at a position 5 cm below each lamp holder and is used for mounting the banana head socket. Next, the red led is placed in the lamp holder, the cathode of the led is connected to the ground port of the UPS unit 105 through a resistor with a resistance of 10K Ω (specifically, through wire bonding), and the anode of the led is connected to the banana head socket. As shown in the LED unit 102 in fig. 2, "LED 1" to "LED 10" represent 10 red LEDs with a diameter of 1 cm, the anodes of these 10 LEDs are respectively connected to the banana head sockets "L1" to "L10", and the specific circuit is shown in the sub-circuit diagram with reference number 102 in fig. 3, in which the element numbers "D1" to "D10" represent the aforementioned 10 LEDs, respectively.

The main function of the led unit 102 is to display the level of the output terminal of the combinational logic chip. In order to verify whether the mounted leds are successful, one plug of the banana head connecting line may be inserted into the power port of the UPS unit 105 in fig. 2, i.e. into the banana head socket marked with "V1", and the other plug of the banana head connecting line is inserted into the banana head sockets marked with "L1", "L2", … "and" L10 "of the led unit 102 in sequence, and the power switch is pressed to see whether the corresponding leds are lit, so as to verify whether the led mounting process is problematic.

The chip testing unit 103 is composed of a locking seat and a banana head socket. It should be noted that, in the process of testing the combinational logic chip by the unit, a chip identification plate matched with the chip of the corresponding model needs to be used, so the positions of the banana head socket and the locking seat on the unit need to be matched with the positions of the chip identification plate shown in fig. 5 to 9. That is, the center distance between two adjacent round holes in the horizontal direction of the banana head socket in the chip testing unit 103 is identical to the center distance between two adjacent round holes in the horizontal direction on the chip identification plate shown in fig. 5-9, and both are 6 cm; the center distance of the banana head socket in the chip testing unit 103 in the vertical direction is the same as the center distance of two adjacent circular holes in the vertical direction on the chip identification plate shown in fig. 5-9, and the center distances are both 15 cm. Meanwhile, it is also necessary to ensure that the locking seat in the chip testing unit 103 matches with the rectangular hole site with the label of "17" on the chip identification plate shown in fig. 5 to 9, that is, when the chip identification plate is embedded into the banana head socket in the chip testing unit 103, the locking seat in the chip testing unit 103 can pass through the rectangular hole site with the label of "17" on the chip identification plate shown in fig. 5 to 9, so as to facilitate the fixing of the chip, and the banana head socket can pass through the corresponding round hole and play a role in fixing the chip identification plate.

In this embodiment, a locking socket with 16 pins is used, the diameter of the pin is 0.8 mm, the length of the pin is 1 cm, and the locking socket is commercially available. Two rows of 16 circular holes with the diameter of 1 mm are arranged at the left side of the chip testing unit 103 on the front surface of the panel for fixing the locking seat. The center distance between two adjacent round holes in the horizontal direction is 2.5 mm, and the center distance between two adjacent round holes in the vertical direction is 10 mm. And (4) coating 101 glue on the bottom of the locking seat, inserting the locking seat into the two rows of round holes, and fixing the locking seat and the panel together through the 101 glue. Note that the position of the fixed locking seats should match the rectangular holes labeled "17" on the chip label plate (as shown in fig. 5-9). The 16 pins of the locking socket are connected with the corresponding banana head socket by adopting a flying wire form on the back surface of the panel, and the specific circuit is shown as a sub-circuit diagram with the reference number 103 in fig. 3.

The logic level unit 104 is composed of a single-pole double-throw switch, a banana head socket and a 5Pin exclusion. In this embodiment, the single pole double throw switch is a toggle switch model MTS102, which is commercially available. The main reason for using the button switch is that the nut is arranged on the button switch, so that the button switch is convenient to fix on a panel. As shown by the logic level cells 104 in FIG. 2, "SW 1" through "SW 8" represent 8 single pole double throw switches. A row of 8 round holes with the diameter of 7 mm in total are formed in the logic level unit 104 area on the front surface of the panel, and the distance between the centers of two adjacent round holes in the horizontal direction is 4 cm. The leftmost hole is selected, the handle of a single-pole double-throw switch (toggle switch) is inserted into the hole from the back of the panel, and the switch is fixed to the panel by a nut on the front of the panel. The specific circuit is shown in the sub-circuit diagram 104 of FIG. 3, in which the resistor of the resistor bank RP1 is 5.1K Ω. On the back of the panel, the input end of one side of the single-pole double-throw switch is connected with the ground port of the UPS unit 105, the input end of the other side of the single-pole double-throw switch is connected with the 2 pin of the exclusion, the common end (1 pin) of the exclusion is connected with the power output port of the UPS unit 105, and the middle output end of the single-pole double-throw switch is connected with the banana head socket O1. In the same way, the remaining 7 single pole double throw switches SW 2-SW 8 are connected to the exclusion, UPS unit 105 and corresponding banana head sockets in sequence.

The output end of the logic level unit 104 provides a high level or a low level for the circuit, as shown in the sub-circuit diagram labeled 104 in fig. 3, when the single-pole double-throw switch SW1 is pulled to the upper end, the output end is connected to the power supply through the exclusion, that is, the banana head socket O1 outputs a high level at this time; when the single-pole double-throw switch SW1 is turned to the lower end, the output end is directly connected with the ground, namely the banana head socket O1 outputs low level. The level of the output of the banana head socket O1 can also be verified by the LED unit 102, specifically, one end of the banana head connection line is inserted into the banana head socket O1 of the logic level unit 104, and the other end is inserted into the banana head socket L1 of the LED unit 102, and whether the LED1 is turned on is observed by toggling the single-pole double-throw switch, if so, it indicates that the banana head socket O1 of the logic level unit 104 outputs a high level, otherwise, it outputs a low level. The logic level unit 104 is required to verify the logic function of the combinational logic chip, which can be seen in the above embodiments.

The UPS unit 105 is composed of a 5V power socket, a UPS power module, 18650 lithium batteries, a power switch, and a banana head socket, and is specifically arranged as shown in the UPS unit 105 in fig. 2. In this embodiment, the 5V power socket is a pure copper socket with a nut, model number QZ7034-M9-2.1, and the diameter of the opening is 9 mm. The UPS power module is a miniature circuit board with a size of 3.5 cm × 1.5 cm, and the circuit board has 6 ports, specifically, as shown in a sub-circuit diagram with reference number 105 in fig. 3, the corresponding device is named as "UPS", where two ports with reference numbers "1" and "2" are power input terminals and are connected with the positive electrode and the negative electrode of a 5V power socket; the positive pole of the 5V power socket is connected with the port 1, and the negative pole is connected with the port 2; the two ports with the labels of 3 and 4 are battery input ends and are respectively connected with the anode and the cathode of the 18650 lithium battery; the two ports marked as '5' and '6' are power output ports, the '5' port is the grounding end of the whole circuit system, the '6' port outputs standard 5V voltage and maximum output current 1A, and the '6' port is connected with the banana head socket through a power switch to supply power to the whole device. All of the components of the UPS unit 105 are commercially available in which the 18650 lithium battery is secured to the front of the panel by a battery compartment with screw holes in the bottom.

The main functions of the UPS unit 105 are two, one is that in case of an external power input (the power of a computer or a mobile power source can be connected to a 5V power socket through a USB patch cord), the external power can charge the 18650 lithium battery in the UPS unit 105 and also supply power to the whole experimental apparatus. And secondly, when no external power supply is available, the UPS module automatically converts the voltage of the 18650 lithium battery into standard 5V voltage to be output and supplies power to the whole experimental device. The UPS unit 105 thus provides an uninterruptible power supply for the entire experimental apparatus, which is flexible and convenient, and facilitates experimental operations without power supply.

Taking a 74LS138 chip as an example, a circuit diagram for testing the chip on the chip testing unit 103 is shown in fig. 10, and is combined with sub-circuit diagrams denoted by

reference numerals

102, 103, 104, and 105 in fig. 3, and the specific implementation steps are as follows:

① placing the 74LS138 chip in the locking seat of the chip testing unit 103 (note that the chip has a notch facing to the left), pressing the locking rod to fix the chip;

② the chip pin identification board 74LS138 shown in FIG. 5 is inserted into the chip testing unit 103, i.e. the 16 circular holes on the chip pin identification board are inserted into the banana head sockets in the chip testing unit 103 and are kept stable, and the locking seats in the chip testing unit 103 are exposed from the rectangular holes on the chip pin identification board;

③ chip pin identification on the pin identification board of the 74LS138 chip in FIG. 5

The pins are decoding input ports, the 3 pins are connected with 3 banana head sockets labeled from '1' to '3' in the chip test unit 103, and the logic level is connected by using the banana head connecting wire in combination with the test circuit diagram shown in fig. 10The banana head socket ' O1 ' in the unit 104 is connected with the banana head socket marked with ' 1 ' in the chip test unit 103, the banana head socket ' O2 ' in the logic level unit 104 is connected with the banana head socket marked with ' 2 ' in the chip test unit 103, the banana head socket ' O3 ' in the logic level unit 104 is connected with the banana head socket marked with ' 3 ' in the chip test unit 103, namely, the logic levels of the ports ' O1 ' -O3 ' are respectively connected to 1-3 pins of the 74LS138 chip;

④ chip pin identification on the pin identification board of the 74LS138 chip in FIG. 5

And

the pins are decoding enable ports and are respectively used by letters

And "E1", the 3 pins are connected to 3 banana head sockets labeled "4" to "6" in the chip testing unit 103, and in conjunction with the testing circuit diagram shown in fig. 10, banana head sockets labeled "4" and "5" in the chip testing unit 103 are both connected to the banana head socket "G1" of the UPS unit 105 by using banana head connecting wires (note that, in the banana head connecting wires used by us, there is a 2 mm diameter jack on the top of the plastic handle of the banana head, when the banana head socket labeled "4" in the chip testing unit 103 is connected to the banana head socket "G1" of the UPS unit 105 by using banana head connecting wires, the banana head socket labeled "5" is connected to "G1" by inserting the banana head into the jack on the top of the previous banana head), and the banana head socket labeled "6" in the chip testing unit 103 is connected to the banana head socket "V1" of the UPS unit 105 by using banana head connecting wires;

⑤ chip pin identification on the pin identification board of the 74LS138 chip in FIG. 5

…、

And

the pins are decoding output ports and are respectively marked by letters

…、

And

to identify that, these 8 pins are respectively connected to 8 banana head sockets labeled "15", "14", … "," 9 "and" 7 "in the chip testing unit 103, and in conjunction with the testing circuit diagram shown in fig. 10, eight banana head connecting wires are used to respectively connect the banana head sockets labeled" 15 "," 14 ", …", "9" and "7" in the chip testing unit 103 to the banana head sockets labeled "L1", "L2", … "," L7 "and" L8 "in the light emitting diode unit 102, that is, the decoding output of the 74LS138 chip is level-connected to eight LEDs in the light emitting diode unit 102, so as to test whether the decoding output is high level or low level.

The circuit construction of the 74LS138 chip test circuit shown in FIG. 10 on the panel of the present invention is completed through the above steps. The switch of the UPS unit 105 is pressed to switch on the power supply, the single-pole double-throw switches SW 1-SW 3 in the logic level unit 104 are switched to access different levels, and the states of LEDs 1-LED 8 in the light emitting diode unit 102 on the panel are observed, so that the logic function of the 74LS138 chip is tested and verified.

The last example is a specific step of testing the 74LS138 chip using the relevant functional units on the panel. Similarly, the four remaining models of combinational logic chips can be tested in conjunction with the 74LS148 chip pin id board (shown in FIG. 6) and test circuit diagram (shown in FIG. 11), the 74LS283 chip pin id board (shown in FIG. 7) and test circuit diagram (shown in FIG. 12), the 74LS48 chip pin id board (shown in FIG. 8) and test circuit diagram (shown in FIG. 13), and the 74LS42 chip pin id board (shown in FIG. 9) and test circuit diagram (shown in FIG. 14). It should be noted that, since the testing steps of the four types of chips are the same as the testing steps of the 74LS138 chip, the description is omitted here.

The utility model discloses a carry out functional test to these five kinds of combination logic chips of 74LS138, 74LS148, 74LS283, 74LS48 and 74LS42, under the unchangeable condition of other functional unit, only need change different chips in chip test unit 103's locking seat, refer to corresponding chip pin sign board alright carry out chip logic functional test simultaneously, it is nimble convenient to use. Similarly, other types of combinational logic chips can also be added according to the actual course needs, for example: functional verification of the four-bit value comparator 74LS85 chip, functional verification of the one-out-of-eight data selector 74LS251 chip, and functional verification of the nine-bit parity checker 74LS280 chip, and so on. Only the pin identification plate of the corresponding chip is needed to be manufactured. Since the steps are similar, they are not described in detail here.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The utility model provides a teaching is with combinational logic circuit experimental apparatus, includes base, panel, chip pin sign board and banana head connecting wire, its characterized in that: the panel integrates a nixie tube unit, a light emitting diode unit, a chip testing unit, a logic level unit and a UPS unit;

the nixie tube unit is composed of a nixie tube, a nixie tube adapter plate, a resistor and a banana head socket, a public port of the nixie tube is connected with a ground port of the UPS unit, a segment port of the nixie tube is connected with the banana head socket through the resistor, and the nixie tube is fixed in a nixie tube unit area on the panel through the nixie tube adapter plate;

2. The combinational logic circuit experimental device for teaching according to claim 1, wherein the base is a rectangular parallelepiped structure composed of a single-layer acrylic plate, and the panel is a single-layer acrylic plate and fixed on the base by long rod screws; the base and the panel are 60 cm long and 45 cm wide.

3. The combinational logic circuit experimental device for teaching purpose according to claim 1, wherein said nixie tube is a red 2.3 inch one-bit common cathode nixie tube, wherein there are 4 LEDs in each segment, and two series-parallel connection is adopted, that is, each two series-connected LEDs are connected in parallel.

4. The combinational logic circuit experimental device for teaching according to claim 1, wherein the diameter of the light emitting diode used in the light emitting diode unit is 1 cm, and the light emitting color is red.

5. The combinational logic circuit experimental device for teaching of claim 1, wherein the chip testing unit requires the use of corresponding chip pin identification boards for chip testing, and the chip pin identification boards include a 74LS138 chip pin identification board, a 74LS148 chip pin identification board, a 74LS283 chip pin identification board, a 74LS48 chip pin identification board and a 74LS42 chip pin identification board.

6. The combinational logic circuit experimental device for teaching of claim 1, wherein said lithium battery is 18650 lithium battery.

7. The combinational logic circuit experimental device for teaching of claim 1, wherein there is a plug at each end of the banana head connecting line, the plug is composed of a plastic handle and a metal lotus head, the diameter of the metal lotus head and the diameter of the inner hole of the banana head socket are both 2 mm, and the top of the plastic handle is provided with a jack with an inner diameter of 2 mm.